JP4594934B2 - 集積型電子チップ及び相互接続デバイス、並びにそれを製造するための方法 - Google Patents
集積型電子チップ及び相互接続デバイス、並びにそれを製造するための方法 Download PDFInfo
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- JP4594934B2 JP4594934B2 JP2006526869A JP2006526869A JP4594934B2 JP 4594934 B2 JP4594934 B2 JP 4594934B2 JP 2006526869 A JP2006526869 A JP 2006526869A JP 2006526869 A JP2006526869 A JP 2006526869A JP 4594934 B2 JP4594934 B2 JP 4594934B2
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Description
相互接続配線27(好ましくはCu)が透明基板23上の誘電体層26(典型的にはポリイミド又は酸化物)に埋め込まれる(図3参照)。基板23は、典型的には、ホウ素フロート・ガラスのようなガラスから製造され、製造に用いられるウェハのサイズに対応した直径200mmのサイズを有する。導体27を含む層26は単一の層として示されるが、製造を容易にするために、多くの場合、多層構造として設計され製造されることが理解されるであろう。層26における配線のレベルの数は、チップ接続部に適合するのに必要とされる接続部密度によって決まり、典型的には、3から5の金属層が必要とされる。Cu導体27は、典型的には、Ni(しかしCu、Au、Co又はこれらの組み合わせとすることもできる)から形成されるボンディング・パッド27pに接続する。ボンディング・パッド27pは、マザーボードへの接続に必要とされる間隔に応じた間隔を有する。例えば、導体27が、C4コネクタが少なくとも0.5mmだけ離されることが要求されるC4技術を用いてマザーボードに接続される(工程の後の段階で)場合には、パッド27pの間隔は同様に0.5mmになる。図3に示すように、誘電材料の薄層がパッド27pを覆うように与えられて、これによって該パッドを基板23から分離することができる。
本実施形態においては、チップ31と相互接続配線27との間の接続が通常のC4コネクタを用いて実現される。図12に示すように、チップ61は誘電体層62に埋め込まれたBEOL金属配線層を有し、最後の金属層がパッド63に接続され、このパッド63上にC4はんだボール64が形成される。相互接続配線67(好ましくはCu)が、透明な基板68上の誘電体層66(典型的にはポリイミド又は酸化物)に埋め込まれる。第1の実施形態と同様、相互接続配線は、ボンディング・パッド67pにも接続する(図13参照、図3と比較されたい)。補強材41は、その上部に接着層42が設けられ、次いでひっくり返されて層66に接合し、図14の構造を形成する。第1の実施形態と同様に、補強材は、その中央にチップ61よりわずかに大きい穴を有する。
26:第1の層
27:導体の第1の組
27p:ボンディング・パッド
28:接着層
29:スタッド
31:半導体デバイス
32:第2の層
33:導体の第2の組
36:バイア
41:支持構造
45:除去用放射線
47、46、49:コネクタ構造
Claims (7)
- 半導体デバイスと、前記半導体デバイスをマザーボードに接続するためのコネクタ構造とを含む集積構造を製造するための方法であって、
前記マザーボードへの接続に必要とされる間隔に応じた第1の間隔距離だけ互いに離れているボンディング・パッドに接続される第1の導体配線が設けられる第1の層を、除去用放射線が透過するプレート上に形成するステップと、
前記半導体デバイスに接続される第2の導体配線が設けられる第2の層を前記半導体デバイス上に形成するステップと、
前記第1の間隔距離より短い第2の間隔距離だけ互いに離れているスタッドを、前記第1の層及び前記第2の層のいずれか一方の層上に、該一方の層の導体配線に接続するように形成するステップと、
前記第1の層及び前記第2の層のうちの前記スタッドが形成されない他方の層上に誘電体の第3の層を形成するステップと、
前記第2の間隔距離に応じた間隔でバイアを前記第3の層に形成し、前記他方の層の導体配線への接続を与える導体を露出させるステップと、
前記スタッドを前記バイアに位置合わせするステップと、
前記第1の導体配線と前記第2の導体配線とが前記スタッドを介して接続されるように、前記半導体デバイスを前記第1の層に取り付けるステップと、
前記ボンディング・パッドが前記第1の間隔距離で配置されて占められる、前記半導体デバイスより大きな面積を有する前記第1の層の相互接続領域を支持するように、支持構造を前記半導体デバイスを囲むように前記第1の層に取り付けるステップと、
前記半導体デバイスと該半導体デバイスを囲んでいる前記支持構造との間の間隙を充填材料で充填するステップと、
前記プレートを透過する除去用放射線を用いて、前記第1の層と該プレートとの間の界面を除去して、該プレートを分離するステップと、
前記コネクタ構造を前記ボンディング・パッドに取り付けるステップと、
を含む方法。 - 前記コネクタ構造は、ピン・グリッド・アレイ(PGA)、ボール・グリッド・アレイ(BGA)すなわちC4アレイ及びランド・グリッド・アレイ(LGA)からなる群より選択される、請求項1に記載の方法。
- 前記支持構造を取り付けるステップが、前記半導体デバイスを取り付けるステップの前かつ前記分離するステップの前に実行される、請求項1または2に記載の方法。
- 前記支持構造を取り付けるステップが、前記半導体デバイスを取り付けるステップの後かつ前記分離するステップの前に実行される、請求項1または2に記載の方法。
- 前記支持構造が、前記マザーボードの熱膨張係数に近似する熱膨張係数を有する、請求項1〜4のいずれか1項に記載の方法。
- 前記コネクタ構造を取り付けるステップの前に、前記ボンディング・パッドを露出させるステップをさらに含む、請求項1〜5のいずれか1項に記載の方法。
- 前記スタッドが前記第1の層の上に形成され、該第1の層には、前記第3の層に結合するための接着層が形成される、請求項1〜6のいずれか1項に記載の方法。
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US10/605,204 US6864165B1 (en) | 2003-09-15 | 2003-09-15 | Method of fabricating integrated electronic chip with an interconnect device |
PCT/US2004/021327 WO2005036632A1 (en) | 2003-09-15 | 2004-06-29 | Integrated electronic chip and interconnect device and process for making the same |
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TWI328867B (en) | 2010-08-11 |
US20050056942A1 (en) | 2005-03-17 |
EP1668685A1 (en) | 2006-06-14 |
KR100772604B1 (ko) | 2007-11-02 |
WO2005036632A1 (en) | 2005-04-21 |
US20070252287A1 (en) | 2007-11-01 |
KR20060064651A (ko) | 2006-06-13 |
EP1668685A4 (en) | 2012-02-29 |
CN1846302A (zh) | 2006-10-11 |
JP2007506278A (ja) | 2007-03-15 |
TW200524119A (en) | 2005-07-16 |
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