TWI328867B - Integrated structure and method for fabricating the same - Google Patents

Integrated structure and method for fabricating the same Download PDF

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Publication number
TWI328867B
TWI328867B TW093126420A TW93126420A TWI328867B TW I328867 B TWI328867 B TW I328867B TW 093126420 A TW093126420 A TW 093126420A TW 93126420 A TW93126420 A TW 93126420A TW I328867 B TWI328867 B TW I328867B
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TW
Taiwan
Prior art keywords
dielectric layer
layer
semiconductor device
connector
wafer
Prior art date
Application number
TW093126420A
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English (en)
Other versions
TW200524119A (en
Inventor
H Bernhard Pogge
Chandrika Prasad
Roy Yu
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Ibm
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Publication of TW200524119A publication Critical patent/TW200524119A/zh
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Publication of TWI328867B publication Critical patent/TWI328867B/zh

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    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Description

2 九、發明說明： 【發明所屬之技術領域】 本發明係關於包括高效能半導 b干等體裝置（其包括CMOS邏輯 裝置、DRAM記憶體裝詈；5甘相，，， 其類似物）及彼等裝置間之内連 〜的電子裝置模組之製造。 y 子。之，本發明係關於具有改 良的可靠性及降低的成本苒曰 问在度晶片内連結之製造0 【先前技#f】 每7代電子裝置不斷變得更複雜，_其各自的裝置 凡件變得更小。此對更高裝置密度及複純之趨勢對裝置 封裝技術人員提出了特殊的挑戰。半導體裝置目前利用導 線結合焊墊或C4焊墊加以製造從而連結此等裝置至下一級 内連結；通常稱其為第一級封裝。 多年來封裝區已表示對許多半導體晶片技術的改良系統 速度方面之主要約束。同時，裝置之封裝表示高比例之總 成本；最近成本模型化指示：就前沿裝置而言，封裝成本 可占總成本的80%之多。 給封裝技術帶來挑戰的複雜大尺度晶片之一實例為包括 多個具有不同功能的内連結晶片之晶片上系統（s〇c)。可使 用傳送及接合（T&J)方法論自分離的處理器或記憶體晶片 製造大SOC，其中經由與多個晶片結合之一薄膜進行晶片 至晶片之内連結。在圖1A中展示此方法之一實例。在一玻 璃晶圓或板上製造具有内連結佈線之薄膜結構。使用間柱， 通道連結來將塗布有分別具有伟線級（wiring level) 1 3及2a 之溥膜的晶片1及晶片2結合至内連結層20。在此實例中， 95200-98122l.d〇, ^^867
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内連結層上形成間柱丨5且使用焊接連結16將巧签馬诸f餐替組^ 至晶片。將間柱與形成於晶片上之層1〇(通常為聚醯亞胺） 内形成之通道11對準。晶片1及晶片2之背側受到平面化且 塗布有黏接層3，而一背概晶圓（backing wafer)4附著至該 毒接層。自内連結層2〇移除玻璃晶圓或板，而留下具有結 合晶片之内連結佈線。在晶片至晶片内連結層2〇上形成電 結合焊墊21，且電結合焊墊21具有在其上形成之以焊墊 22。在第6,444,560號美國專利中討論t&j方法之細節，其 揭示内容以引用的方式倂入本文中。 利用上述t&j方法論之晶片至晶片置放可近至25 μιη至 60 μηι，其置放精確度約為i μπι。值得注意的是，晶片】及 晶片2可具有不同功能且以不同方法製造。因此T&j方法允 許製造晶片上系統，其中不同裝置緊密地内連結（參看圖 1B)。
歸因於焊墊之間隔要求（典型的C4間距為至少1 5 〇 μηι，且 通常自0.5 mm至2.5 mm)，使用C4焊墊或導線結合焊墊來 SOC連結至主機板對封裝裝置之佈線密度及帶寬強加了實 際限制。此外’每一 C4連結表示約5〇 psec之訊號延遲。 為了（1)允許更有效的高密度裝置封裝及（2)製造成本降 低之裝置模組，因此需要將上述的丁&J方法論自晶片至晶片 内連結方案延伸至晶片至封裴整合技術。 【發明内容】 本發明提供一種包括一半導體裝置及連結該半導體裝置 至主機板之連結器結構的整合式結構，且提供一種製造 95200-981221.doc -6 · 此結:構之方法。 ，根據本毛明之第一態樣，該方法包括以下步驟：在可讓 /肖=輕射透過之板上形成_第_層a在半導體裝置上形成 一第二層。第一層具有安置於其中之第一組導體；第一組 導體連結至結合焊墊，該等結合焊餘據至主機板之連結 所需的間隔以第一間隔距離間隔。第二層具有安置在其中 且連結至半導體裝置之第二組導體。接著在第一層及第二 層之一者上形成間柱，且在第一層及第二層之另一者上形 成-第三層；言亥等間柱以小於第一間隔距離之第二間隔距 離間°纟第二層内形成通道，其同樣根據第二間隔距離 而間隔。接著使間柱與通道對準’且將半導體裝置附著至 第一層，以使得經由間柱連結第一組導體及第二組導體。 該方法亦包括下一步驟：使用藉由透射穿過板之消熔輻射 :肖炫第與板之間的介面，#&分離板接著將連結器附 著至，、.σ 5知塾。連結器結構形成插腳柵格陣列（PGA)、球狀 柵格陣列（BGA)、C4陣列及平臺柵格陣列（LGA)之一。 一支撐結構或加強件（stiffener)較佳附著至第一層，以使 得支撐結構環繞半導體裝置；可在半導體裝置附著至第一 層之前或之後附著該支撐結構。支撐結構具有對應於結合 焊墊佔據之面積的面積。支撐結構有利地具有與主機板之 熱膨脹係數（TCE)近似之熱膨脹係數。利用有機填充材料來 填充半導體裝置與支撐結構之間的間隙β值得注意的是， 第二組導體通常為複數個BEOL金屬層；此等金屬層之數目 小於扇出（fanout)至以第一間隔距離間隔之結合焊墊所需 95200-981221.doc 1328867 根據本發明之第二態樣，一種類似方法具備1^ 一層之間的連結器（C4連結器）。相應地’除了半導體裝置 與加強件之間的間隙之外，半導體裝置與環繞C4連結器的 第-層之間存在-間隙，其同樣填充有填充材料。 根據本發明之-額外態樣，提供—種包括—半導體裝置 及連結該半導體裝置至一主機板之連結器結構的整合式結 構。此外，此整合式結構包括具有安置在其中 體的第一層；第一組導體連結至安置在該層之下表面:的 結合焊塾。該等結合焊塾根據至主機板之連結之所需間隔 以第一間隔距離而相互間隔。在半導體裝置上安置面向第 一層之第二層且此第二層與半導體裝置接觸；第二層具有 安置在其中且連結至半導體裝置之第二組導體。複：個連 結器將第一組導體連結至第二組導體；此等導體為—組間 柱/通道連結器或一組C4連結器。此等連結器以小於第一間 隔距離之第二間隔距離相互間隔。支撐結構或加強件附^ 至第一層之上表面且環繞半導體裝置，且利用填充材料來 填充支撐結構與半導體裝置之間的_間隙。將連結器結構 連、至、，&焊墊，此等連結益結構可形成插腳柵格陣列 (PGA)、球狀柵格陣列（BGA)、C4陣列或平臺柵格陣列 (LGA)。 【實施方式】 根據本發明，使用T&J技術來減少個別晶片上所需的 BEOL金屬層之數目，同時提供自晶片至晶片及晶片與下— 95200-981221.doc 1328867 ^ΛΛΨ^Μ t封展乏間的有效且具成本效益之内連結。 第一實施例··使用間柱/通道連結將晶片接合至佈線層。 在透明基板23 (參看圖2 A)上的介電層26(通常為聚醯亞 胺或氧化物）内嵌入内連結佈線27(較佳為Cu)。基板23通常 由諸如硼浮玻璃（boro-float glass)之玻璃製成且直徑大小 為200 mm，其與製造中使用的晶圓大小相當。儘管包括導 體27之層26顯示為一單層，但是應瞭解為了便於製造其常 被設計及製造為多層結構。層26中佈線層之數目視與晶片 連結匹配所需之連結密度而定；通常需要3至5個金屬層。 Cu導體27連結至通常由Ni(但也可為Cu、Au、c〇或其組合） 形成的結合焊墊27p。結合焊墊2715具有根據至主機板之連 結所需的間隔之一間隔。舉例而言，若導體27使用以技術 (其中C4連結器要求之間隔至少為〇 5 mm)而連結 理之 較後階段）至一主機板，則焊墊27p之間隔同樣為〇·5 mm。 如圖2A所示，可提供一薄層介電材料來覆蓋焊墊，藉以 使該等焊墊與基板23分離。 參看圖2B，在佈線層26之頂部形成一對準結構^以形成 至晶片之實體或電連結。在此實施例中，該對準結構具有 在内連結佈線層上形成之間柱以與在晶片上之另一層上形 成之通道對準。形成之連結器焊塾29p連結至頂部&佈線。 焊墊29P具有形成於其上之間柱29;該等間柱可由Ni、cu、 鑛Ni之Cu、贾或其他一些金屬或金屬之組合而形成。佈線 層26之頂表面塗布有—層熱塑性聚合物黏接層μ ;間柱μ 自此層突出。層28充當用於隨後將晶片結合至佈線層％之 95200-981221.do« 1328867 [年9 j 12日兔正替換買 黏接劑。在每一間柱29之表面上形成一層低炫^ 30 ;此促成在晶片接合過程中形成電連結。此材料通常為 90/10 Pb/Sn焊料，其為2 Fm或更薄；替代合金材料包括 Au/Sn及Sn/Ag。如圖2B中所示，合金材料可經受熱軟熔處 理以使得層30獲得圓形狀；此促成了間柱與在晶片上形成 之通道結構對準。 根據此項技術中已知之方法製造晶片31。如此項技術中 之理解，在晶片之頂部表面31t處形成金屬佈線層33(嵌入介 電層32中且由此介電層所環繞）。此等佈線層通常被稱作線 後端或BEOL層。與此項技術的當前狀態對比’沒有必要構 建BEOL層，其扇出至區域密度降低的C4焊墊或線結合焊墊 以連結至晶片封裝；如下文更詳細的描述，在本實施例中 不使用C4或線結合焊墊而形成晶片與封裝間之連結。因 此，所需的BEOL金屬層33之數目通.常自6或7個（此扇出通 常所需要的數目）減少至3個或4個（參看圖3A)。其具有改良 晶片良率及降低晶片製造成本之效應。 最後的金屬層由一介電層35(觀察圖3B)覆蓋。層35通常 為在薄膜封裝處理中使用之聚醯亞胺材料。層35具有在其 中形成之通道36。如圖3B所示，該等通道可以一傾斜壁角 度形成以作為一用於將間柱29高精度、自我對準地置放於 通道36中之引導器。一連結至通道下的金屬層之導體位於 每通道36之底部。通道之壁角可設計為近似垂直或傾斜 通吊以南達此點之晶圓級製造晶片，且接著將晶片切 割為接合至封裝之個別晶片。 95200-98l221.doc •10· 年月日修正替換頁 胳m r 應注意：晶片.31(連同BEOL佈線33)及對準結構25(連通内 連結佈線層26)可加以並行處理。因為相對於習知晶片封裝 機制而言減少了 BEOL金屬佈線層之數目，所以此也具有改 良處理產量及降低成本之效應。 如圖4A所示，接著晶片31對準排列結構對準以使得間柱 29與通道36匹配。較佳地在適度提升之溫度下執行此對 準，以使知·黏接層28在與層35之表面接觸之前具有輕微的 黏性。此阻礙晶片3 1在隨後的結合操作過程中移動。 如圖4A所示，内連結面積之大小通常大於晶片面積。此 歸因於主機板上連結之較低的密度，其中連結器之典型間 距的範圍為自0.5 mm至2.5 mm。環繞晶片之區域4〇填充有 一加強件（或複數個加強件），其同樣利用黏接層28而附著至 薄膜内連結層之頂部。如圖4B中所示，加強件“在其中心 具有一稱微大於晶片31之孔。在加強件中可製作額外的開 口以允許其它裝置（例如，退耗電容器）附著在表面28a上並 鄰近晶片。加強件在其頂部表面上形成有一層熱塑性聚 醯亞胺或其它黏接劑42，且接著翻轉過來且附著至層Μ。 加強件可由陶究、金屬或有機材料製成；加強件材料 擇將視機械強度及可靠^ 你·… 加強件材料的熱膨脹 ’ 要與主機板之熱膨脹係數接近。如圖4B所 示，可選擇加強件41之厚戶 口衫所 应 使付加強件之背部表面41b ，、日日月之月部表面31b高声；ten -¥ 4¾. 厪相同。或者，可將加強 :厚：更好地容納表㈣上的熱冷卻焊料、熱傳導 或-些其它散熱片之置放。 導化口物 95200-981221.doc 1328867 ，. %eh2m^\ • 在置放於黏接層28上之後，在提升之溫度及壓力下使用 璧層處理將晶片3 1及加強件41結合至薄膜内連結結構（意 即’其上具有佈線層26及黏接層28之基板23)。視所使用之 特定材料而定，在15〇°C至400。(：之溫度及10至200 psi之壓 力執行結合。視疊層處理工具之設計而定，在實際尺寸的 玻璃基板（製造中使用的典型晶圓之尺寸，直徑為2〇〇 mm 至3 00 mm)上或以更小切割尺寸（例如，1 〇〇平方毫米平方至 300平方毫米）可執行結合操作。此結合操作會導致焊料30 流動並至少部分填充通道36且形成至Be〇l金屬層33之電 連結。因此自晶片3 1穿過金屬層33、間柱29及内連結佈線 27形成至結合焊墊27p之電連結。 接著利用有機材料（聚醯亞胺或未填滿材料）來填充晶片 與加強件之間的狹窄間隙43以確保晶片31 '加強件41及佈 線層2 6形成一剛性系統。 如圖4C不意展示，疊層結構接著經受雷射消熔處理。入 ^ 射至透明板23上之雷射輻射45穿透板且消熔了板與層26之 間的介面。其導致板自層26分層，以使得可移除板。接著 藉由灰化或雷射消熔任何聚醯亞胺殘餘物來曝光内連結層 結構中的烊墊27p。 s墊S：到曝光後，處理晶片/加強件/内連結結構以產生連 結至主機板之模組。此處之結構通常切割成個別模組且經 X適當的電測試。接下來如圖4D所示，在烊墊27p上形成連 結器冶金。連結器可為插腳栅格陣列（pGA)、插腳47、球狀 栅格陣列（BGA)、C4焊料球48或平臺栅格陣列（LGA)結構49 95200-981221.doc 12·
之形態。如上所述，可在鄰近晶片3 1之加強件開口中提供 間隔以退耦電容器或其類似物；相應地’内連結層之整個 底部表面26b可用於連結器結構47、48或49之置放。 應注意：如圖4D示意展示，.完整的結構相比習知的配置 而言具有改良的内連結密度及更高的可靠性。至晶片之連 結器（在此實施例中，間柱29)相比當前的封裝裝置之150 μιη 間距而言具有典型的1 〇 μΓη間距。此外，消除晶片與内連結 之間的C4焊接連結以使得避免具有C4疲乏可靠性之問 題。另外’若選擇的加強件材料具有其與主機板的TCE匹 配，則可避免對熱應力可靠性之關心。 應瞭解：藉由顛倒圖2Β及3Β中所示的間柱及通道之位 置，亦可實現晶片3 1與内連結佈線層26之間的間柱/通道連 結；意即’在晶片31之BEOL佈線層上可形成間柱而在内連 結佈線層26上形成具有通道之聚醯亞胺層。 亦應注意到透明板23可為任何習知尺寸及形狀以容納晶 片。舉例而言’若每一晶片31為25平方毫米且位於6〇平方 毫米加強件之中心，則可在200平方‘米的板上便利地處理 3x3陣列的晶片。 如圖5所示，若需要確保在晶片附著至内連結層之前内連 結層為剛性的，則在晶片接合處理之前加強件41可附著至 黏接層28(使用施加至加強件之黏接層42)。如上文所述參看 圖4Α至4C，晶片隨後附著並結合’且移除板23以產生圖々^ 所示之整合式結構。 第二實施例：晶片使用C4連結接合至佈線層 95200-981221.doc •13· 1328867
在此實施例中’使用習知的C4連結器實現晶片3丨與内連 結佈線27之間的連結。如圖6 A所示，晶片61具有嵌入介電 層62中之BEOL金屬佈線層，而最後的金屬層連結至其上形 成有C4焊料球64之焊墊63。内連結佈線67(較佳為Cu)嵌入 透明基板68上之介電層66(通常聚醯亞胺或氧化物）中。與第 一實施例（觀察圖6B ;比較圖2A)相似，内連結佈線亦連結 至結合焊墊67p。加強件41以其頂部之黏接層42製備，接著 翻轉過來且接合至層66以形成圖6C之結構。與第一實施例 相似’加強件在其中心具有一稍微大於晶片6丨之孔。 接著藉由習知的C4晶片接合方法將晶片接合至内連結佈 線層（圖6D)。接著利用有機材料71 (圖6E)來填充晶片與加強 件之間的整個間隙（包括晶片下及環繞C4連結器之任何空 間）。此步驟可視作間隙填充及C4未填滿處理。最後，與第 一實施例相似，藉由雷射消熔處理自層66移除透明基板 68 ’將結合焊墊67p曝露出來，且將適當的結構（Pga、 BGA、C4或LGA)附著至一焊墊以與主機板連結（圖6F)。 本發明之優勢 本發明提供一種建置整合式、高密度、高效能晶片内連 結系統之方法，其具有若干優勢：（1)相對現有的系統而言， 間柱/通道連結之使用減小了晶片内連結之間距；（2)以具有 可調整TCE之加強件環繞每—晶片；（3)整體晶片/封裝成本 估計降低50% ; (4)可並行製造晶片及内連結；（5)内連結之 底部表面除了連結器外無組件或結構，以使得整合式模組 之總面積減小。 95200-981221.doc •14· 1338867—η I Μ2.Ψ^μ\ 儘管已根據特定實施例說明了本發明，但是顯然鑒於上 文描述，熟悉此項技術者將易於瞭解各種替代物、修改及 變化。因此，本發明意欲包括屬於本發明及隨後的申請專 利範圍之範疇及精神的所有此等替代物、修改及變化。 【圖式簡單說明】 圖1Α為使用上述T&J方法論利用至第一級封裝之C4連結 之内連結晶片的示意橫截面圖。 圖1B為根據圖1A之T&J方法論製造的晶片上系統（S0C) 之示意圖。 圖2A為根據本發明之第一實施例在玻璃基板上形成之内 連結佈線層的示意橫截面圖。 圖2B為在圖2A之佈線層上形成以將佈線層連結至晶片 之間柱的示意橫截面圖。 圖3A為根據本發明具有在其上形成之線後端（be〇l)金 屬層之晶片的示意戴面圖。 圖3B為具有一額外層之圖3A之晶片的示意橫截面圖，該 額外層具有在其中形成從而與圖2A之佈線層上的間柱對準 之通道。 圖4A展示根據本發明第一實施例連結至内連結佈線層之 一晶片。 圖4B展示根據本發明第一實施例具有置於内連結佈線層 上之加強件之圖4A之配置。 圖4C為自内連結佈線層移除玻璃基板所用的消熔方法之 示意圖。 95200-981221.doc -15- 1328867 圖4D為根據本發明之一完全整合式裝置之立 '、思橫戴面 圖0 圖5為一基板之示意橫截面圖，該基板上 Λ乂百—佈線 層、多個加強件及連結間柱，其中在連結晶片之前附著加 強件。 圖6Α為根據本發明之第二實施例具有C4連結器之晶片 的示意橫戴面圖。
圖6Β至6F說明根據本發明之第二實施例形成整合式裴置 之步驟。 【主要元件符號說明】 1、2 晶片 la ' 2a 佈線級 3 黏接層 4 背襯晶圓 10 層 11 通道 15 間柱 16 焊接連結 20 内連結層 21 電結合焊塾 22 C4焊塾 23 透明基板 25 對準結構 26 介電層/佈線層
95200-981221.doc -16-
Lgg.lS· 9.11 修正替顧 26b 底部表面 27 導體 27p 結合焊墊 28 黏接層 28a 表面 29 間柱 29p 焊墊 30 低熔點合金材料層 31 晶片 31b 、 41b 背部表面 31t 頂部表面 32 介電層 33 金屬佈線層 35 介電層 36 通道 40 區域 41 加強件 42 黏接層 43 間隙 45 雷射韓射 47 、 48 、 49 連結器結構 61 晶片 62 介電層 63 焊墊
95200-981221.doc 17 1328867 64 66 67 67p 68 71 焊料球 介電層 内連結佈線 結合焊墊 透明基板 有機材料
日修正替換頁I 21
95200-981221 .doc 18-

Claims (1)

  1. T328867 年月f giE替換頁I 十、申請專利範圍： 導:i:及ί合式結構之方法’該整合式結構包括-半 "以連結該半導體裝置至一主機板之多個連 結器結構，該方法包含以下步驟： 個連 可讓消μ射透過之板上形成-卜介電層，該 弟"電層具有安置在其中之一第一組導體，該第—組 導體連結至多個沾入 機板之連結之料結合焊㈣根據至該主 在該半導體裝置1—第^隔距_隔開； :有安置在其中且連結至該半導體裝置之—第二 間等二層及該第二介電層其中之-上形成多個 距離間隔開；小於該第—間隔距離卜第二間隔 於該第-介電層及該第二介電層中沒 一層上形成一第三介電層； 八上之 第在ft:電層中形成多個通道’該等通道係根據該 弟一間隔距離間隔開； 使該等間柱對準該等通道； 將該半導體裝置附著至該第_介電層 組導體及該第二組導體㈣料㈣連結第 將一支撐結構附著至 構環繞該何㈣nf/電層錢传該支擇結 ^ ^ ^ k支撐結構具有一對應於該等結 4墊所佔據的—面積外之面積； 2.
    使用透射穿過該板之消熔輻射消熔該第 板之間的—介面’藉此分離該板；及 一介電層與該 將該等連結器結構附著至該等結合焊墊。 =求項1之方法’其中該等連結器結構形成—插聊拇格 歹Upga)、一球狀柵格陣列（BG 一 c4 一 柵格陣列(LGA)的其中之_。 千臺 3.
    如凊求項1之方法 著該半導體裝置 行0 ，其中附著該支撐結構之該步驟係在附 之該步驟之前及在該消熔步驟之前執 4·如請求項1之方法 著該半導體裝置 行0 其中附著該支撐結構之該步驟係在附 之忒步驟之後及在該消熔步驟之前執 5+ 6. 如請求項1之方法，苴 产墙夕士〜 進纟包含填充該半導體褒置與該 L堯之支揮結構之間之-間隙之步驟。 7. 如請求項1之方法，其 之料挪 進#包含在附著該等連結器結構 之該步驟之前曝露出該等結合焊墊之步驟。 8. 如求項1之方法，其中今耸門如# μ 4間柱係形成於該第一介電層 上，且垓第一介電層具有一用 黏接層。 有用以結合至該第三介電層之 9. 如請求項1之一種方法，其中該第 個金屬層内，該等金屬層之數目 二級導體係排列在複數 係小於扇出至以該第一 95200-981221.doc 閭隔距離間隔開之該等結合焊墊所需的層之數目。 10· -種製造-整合式結構之方法，該整合式結構包 導，裝置及用以連結該半導體裝置至4機板之多 結器結構’該方法包含以下步驟： 在一可讓消溶輻射透過之板上形成一第一介電層，該 第-介電層具有安置在其中之—第一組導體，該；一： 導體連結至多個結合焊塾，該等結合焊㈣根據至該主 機板之連結之-所需間隔以一第一間隔距離間隔開； 在該半導體裝置上形成一第二介電層，該第二介電層 具有安置在其中且連結至該半導體裝置之一第二 體； 、'等 在該第一介電層上形成複數個C4連結器，該等以連結 器係以小於該第-間隔距離之-第二間隔距離間隔開^ 使該等C4連結器對準該第一介電層； 將該等CM連結器附菩$ #楚 * _ 益W f主邊弟一介電層，以使得該第 組導體及該第二組導體連結； 將支撐、纟°構附著至該第一介電層，以使得該支撐社 構環繞該半導體裝置，該支#結構具有—對應於該等= 5烊塾所佔據的—面積外之面積； 使用透射穿過該板之消炫輻射消溶該第-介電層與該 板之間的一介面，藉此分離該板；及 將該等連結器結構附著至該等結合焊墊。 月求項10之方法，其中該等連結器結構形成一插腳拇 格陣列（PGA) ' 一球狀柵格陣列（BGA)、- C4陣列及-平 95200-98l22l.d〇l 10 0 臺柵格陣列（LGA)的其中之一。 12 13 月求項10之方法，其中附著該支撐結構之該步驟係在附 著亥C4連結盗之該步驟之前及在該消熔步驟之前執行。 如-月求項1G之方法，其中該主機板之特徵在於_熱膨服 系數（TCE)，且該支撐結構具備一與該主機板之近似 之 TCE。 4.如《•月求項1G之方法，其進_步包含以下步驟填充該半 導體裝置與該環繞之支撐結構間之一間隙及該半導體裝 置與環繞該等C4連結器之該第一介電層間之一間隙。 15. 如吻求項10之方法，其進一步包含在附著該等連結器結 構之該步驟之前曝露出該等結合焊墊之步驟。 16. 如哨求項10之方法，其中該第二組導體係排列在複數個 金屬層内，該等金屬層之數目係小於扇出至以該第一間 隔距離間隔開之該等結合焊墊所需的層之數目。 17. 一種包括一半導體裝置及用以連結該半導體裝置至一主機 板之夕個連結器結構的整合式結構，該整合式結構包含： 其中女置有一互連線路之一第一介電層，該第一介電 層具有一上表面及一下表面，該互連線路連結至安置在 該下表面上之多個結合焊墊，該等結合焊墊係根據至該 主機板之連結所需的間隔而相對於彼此以一第一間隔距 離間隔開； 該半導體裝置； 安置在該半導體裝置上且與之接觸之一第二介電層， 該第二介電層具有安置在其中且連結至該半導體裝置之 95200-98I22I.doc 曰修i替換頁 一組導體，該第二介電層面對該第一介電層； 連結該互連線路至該組導體之複數個連結器該等連 結器為-組C4連結器’該等連結器相料彼此以小於該 第—間隔距離之一第二間隔距離間隔開； 附著至該第一介電層之該上表面且環繞該半導體裝置 之—支撐結構，該支撐結構與該半導體裝置之間的一間 隙填充有一填充材料；及 連結至該等結合焊墊之多個連結器結構，其中該連結 器結構形成一平臺柵格陣列（LGA)以將該半導體裝置連 接至該主機板。 18. 如請求項17之整合式結構，其中該主機板之特徵在於一 熱膨脹係、數（TCE)，且該支撐結構具備—與該主機板之 TCE近似之Tce。 19. 如請求項17之整合式結構，其中該支樓結構具有一對應 於β玄等結合焊墊所佔據的一面積外之面積。 20. 如請求項17之整合式結構，其中該等複數個連結器為一 組C4連結器’且該填充材料填充了該半導體裝置與環繞 該等C4連結器之該第一介電層之間的一間隙。 21. 如請求項17之整合式結構，其中該結合焊塾包括彼此以 該第一間隔距離平均隔開之一結合焊墊陣列。 95200-9B1221.doc
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Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6642136B1 (en) * 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US8021976B2 (en) * 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US6815324B2 (en) * 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
US8158508B2 (en) * 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
TWI313507B (en) 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US7099293B2 (en) 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
TWI245402B (en) * 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US7394161B2 (en) * 2003-12-08 2008-07-01 Megica Corporation Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto
TWI236122B (en) * 2004-02-27 2005-07-11 Via Tech Inc A low thermal expansion build-up layer packaging and a method to package a die using the same
TWI237883B (en) * 2004-05-11 2005-08-11 Via Tech Inc Chip embedded package structure and process thereof
JP4865197B2 (ja) * 2004-06-30 2012-02-01 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8067837B2 (en) * 2004-09-20 2011-11-29 Megica Corporation Metallization structure over passivation layer for IC chip
JP4528062B2 (ja) * 2004-08-25 2010-08-18 富士通株式会社 半導体装置およびその製造方法
US20060145356A1 (en) * 2005-01-06 2006-07-06 International Business Machines Corporation On-chip cooling
TWI255518B (en) * 2005-01-19 2006-05-21 Via Tech Inc Chip package
US8294279B2 (en) * 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
JP3914239B2 (ja) * 2005-03-15 2007-05-16 新光電気工業株式会社 配線基板および配線基板の製造方法
JP4790297B2 (ja) * 2005-04-06 2011-10-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2007123524A (ja) * 2005-10-27 2007-05-17 Shinko Electric Ind Co Ltd 電子部品内蔵基板
TWI281737B (en) * 2005-12-13 2007-05-21 Via Tech Inc Chip package and coreless package substrate thereof
JP2007242888A (ja) * 2006-03-08 2007-09-20 Sony Corp 半導体パッケージ製造方法
JP3942190B1 (ja) * 2006-04-25 2007-07-11 国立大学法人九州工業大学 両面電極構造の半導体装置及びその製造方法
US8164773B2 (en) 2006-05-26 2012-04-24 Marvell World Trade Ltd. Wireless system-in-package and image processing control apparatus
KR100856326B1 (ko) * 2006-07-19 2008-09-03 삼성전기주식회사 레이저 리프트 오프를 이용한 유전체 박막을 갖는 박막 커패시터 내장된 인쇄회로기판 제조방법, 및 이로부터 제조된 박막 커패시터 내장된 인쇄회로기판
US7985621B2 (en) * 2006-08-31 2011-07-26 Ati Technologies Ulc Method and apparatus for making semiconductor packages
US8373266B2 (en) * 2007-03-29 2013-02-12 Continental Automotive Systems, Inc. Heat sink mounted on a vehicle-transmission case
US7893527B2 (en) * 2007-07-24 2011-02-22 Samsung Electro-Mechanics Co., Ltd. Semiconductor plastic package and fabricating method thereof
WO2009031262A1 (ja) * 2007-09-03 2009-03-12 Panasonic Corporation 配線基板
JP5245485B2 (ja) * 2008-03-25 2013-07-24 富士電機株式会社 半導体装置の製造方法
US8259454B2 (en) * 2008-04-14 2012-09-04 General Electric Company Interconnect structure including hybrid frame panel
KR100956688B1 (ko) * 2008-05-13 2010-05-10 삼성전기주식회사 인쇄회로기판 및 그 제조방법
US8637953B2 (en) * 2008-07-14 2014-01-28 International Business Machines Corporation Wafer scale membrane for three-dimensional integrated circuit device fabrication
US7989950B2 (en) * 2008-08-14 2011-08-02 Stats Chippac Ltd. Integrated circuit packaging system having a cavity
US8823160B2 (en) * 2008-08-22 2014-09-02 Stats Chippac Ltd. Integrated circuit package system having cavity
US9006028B2 (en) * 2008-09-12 2015-04-14 Ananda H. Kumar Methods for forming ceramic substrates with via studs
WO2010030962A2 (en) * 2008-09-12 2010-03-18 Kumar Ananda H Structures and methods for wafer packages, and probes
US7855455B2 (en) * 2008-09-26 2010-12-21 International Business Machines Corporation Lock and key through-via method for wafer level 3 D integration and structures produced
US8093099B2 (en) * 2008-09-26 2012-01-10 International Business Machines Corporation Lock and key through-via method for wafer level 3D integration and structures produced
US9064717B2 (en) * 2008-09-26 2015-06-23 International Business Machines Corporation Lock and key through-via method for wafer level 3D integration and structures produced thereby
US8143097B2 (en) * 2009-09-23 2012-03-27 Stats Chippac, Ltd. Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
US9875911B2 (en) 2009-09-23 2018-01-23 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interposer with opening to contain semiconductor die
US8901724B2 (en) 2009-12-29 2014-12-02 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
US8247895B2 (en) 2010-01-08 2012-08-21 International Business Machines Corporation 4D device process and structure
US8330262B2 (en) 2010-02-02 2012-12-11 International Business Machines Corporation Processes for enhanced 3D integration and structures generated using the same
JP2011176112A (ja) * 2010-02-24 2011-09-08 Renesas Electronics Corp 半導体集積回路及びその製造方法
US8710639B2 (en) * 2010-04-08 2014-04-29 Nec Corporation Semiconductor element-embedded wiring substrate
US8618652B2 (en) * 2010-04-16 2013-12-31 Intel Corporation Forming functionalized carrier structures with coreless packages
US8415792B2 (en) 2010-08-04 2013-04-09 International Business Machines Corporation Electrical contact alignment posts
JP2012049421A (ja) * 2010-08-30 2012-03-08 Keihin Corp 電子部品の実装構造
US8623763B2 (en) * 2011-06-01 2014-01-07 Texas Instruments Incorporated Protective layer for protecting TSV tips during thermo-compressive bonding
US20150325527A1 (en) * 2013-01-28 2015-11-12 Hewlett-Packard Development Company, Lp. Radiused alignment post for substrate material
US20140295623A1 (en) * 2013-03-29 2014-10-02 Kinsus Interconnect Technology Corp. Method of packaging a chip and a substrate
US9994741B2 (en) 2015-12-13 2018-06-12 International Business Machines Corporation Enhanced adhesive materials and processes for 3D applications
US9953934B2 (en) * 2015-12-16 2018-04-24 Intel Corporation Warpage controlled package and method for same
US20180053665A1 (en) * 2016-08-19 2018-02-22 Mediatek Inc. Pre-bumped redistribution layer structure and semiconductor package incorporating such pre-bumped redistribution layer structure
US20180130768A1 (en) * 2016-11-09 2018-05-10 Unisem (M) Berhad Substrate Based Fan-Out Wafer Level Packaging
US20180130720A1 (en) * 2016-11-09 2018-05-10 Unisem (M) Berhad Substrate Based Fan-Out Wafer Level Packaging
US20190259731A1 (en) * 2016-11-09 2019-08-22 Unisem (M) Berhad Substrate based fan-out wafer level packaging
US11062773B2 (en) * 2019-05-13 2021-07-13 Ememory Technology Inc. Near-memory computation system for analog computing

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160645A (ja) * 1984-02-01 1985-08-22 Hitachi Ltd 積層半導体集積回路装置
US4670770A (en) * 1984-02-21 1987-06-02 American Telephone And Telegraph Company Integrated circuit chip-and-substrate assembly
US4783695A (en) * 1986-09-26 1988-11-08 General Electric Company Multichip integrated circuit packaging configuration and method
US4884122A (en) * 1988-08-05 1989-11-28 General Electric Company Method and configuration for testing electronic circuits and integrated circuit chips using a removable overlay layer
US4933042A (en) * 1986-09-26 1990-06-12 General Electric Company Method for packaging integrated circuit chips employing a polymer film overlay layer
US4949148A (en) * 1989-01-11 1990-08-14 Bartelink Dirk J Self-aligning integrated circuit assembly
US5019535A (en) * 1989-03-28 1991-05-28 General Electric Company Die attachment method using nonconductive adhesive for use in high density interconnected assemblies
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5373627A (en) * 1993-11-23 1994-12-20 Grebe; Kurt R. Method of forming multi-chip module with high density interconnections
JPH08330360A (ja) * 1995-05-31 1996-12-13 Nec Corp 半導体装置及びその製造方法
US5791911A (en) * 1996-10-25 1998-08-11 International Business Machines Corporation Coaxial interconnect devices and methods of making the same
US5835355A (en) * 1997-09-22 1998-11-10 Lsi Logic Corporation Tape ball grid array package with perforated metal stiffener
EP0926729A3 (en) * 1997-12-10 1999-12-08 Mitsubishi Gas Chemical Company, Inc. Semiconductor plastic package and process for the production thereof
US5998868A (en) * 1998-02-04 1999-12-07 International Business Machines Corporation Very dense chip package
US6087199A (en) * 1998-02-04 2000-07-11 International Business Machines Corporation Method for fabricating a very dense chip package
US6025638A (en) * 1998-06-01 2000-02-15 International Business Machines Corporation Structure for precision multichip assembly
US6316786B1 (en) * 1998-08-29 2001-11-13 International Business Machines Corporation Organic opto-electronic devices
US6066513A (en) * 1998-10-02 2000-05-23 International Business Machines Corporation Process for precise multichip integration and product thereof
US6281452B1 (en) * 1998-12-03 2001-08-28 International Business Machines Corporation Multi-level thin-film electronic packaging structure and related method
US6110806A (en) * 1999-03-26 2000-08-29 International Business Machines Corporation Process for precision alignment of chips for mounting on a substrate
JP2001035960A (ja) * 1999-07-21 2001-02-09 Mitsubishi Electric Corp 半導体装置および製造方法
JP2001267474A (ja) * 2000-03-21 2001-09-28 Rohm Co Ltd 半導体装置
US6444560B1 (en) * 2000-09-26 2002-09-03 International Business Machines Corporation Process for making fine pitch connections between devices and structure made by the process
TW503531B (en) * 2000-09-28 2002-09-21 Toshiba Corp Multi-layered semiconductor apparatus
US6600224B1 (en) * 2000-10-31 2003-07-29 International Business Machines Corporation Thin film attachment to laminate using a dendritic interconnection
US6607942B1 (en) * 2001-07-26 2003-08-19 Taiwan Semiconductor Manufacturing Company Method of fabricating as grooved heat spreader for stress reduction in an IC package
US6472762B1 (en) * 2001-08-31 2002-10-29 Lsi Logic Corporation Enhanced laminate flipchip package using a high CTE heatspreader
US6599778B2 (en) * 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
JP3879516B2 (ja) * 2002-01-16 2007-02-14 日立電線株式会社 配線基板の製造方法及び配線基板
JP3908157B2 (ja) * 2002-01-24 2007-04-25 Ｎｅｃエレクトロニクス株式会社 フリップチップ型半導体装置の製造方法

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