CN100405561C - 制造集成结构的方法 - Google Patents

制造集成结构的方法 Download PDF

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Publication number
CN100405561C
CN100405561C CNB2004800256474A CN200480025647A CN100405561C CN 100405561 C CN100405561 C CN 100405561C CN B2004800256474 A CNB2004800256474 A CN B2004800256474A CN 200480025647 A CN200480025647 A CN 200480025647A CN 100405561 C CN100405561 C CN 100405561C
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layer
ground floor
semiconductor device
chip
attached
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CNB2004800256474A
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CN1846302A (zh
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B·H·波格
C·普拉塞德
R·于
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Ultratech Corp
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International Business Machines Corp
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Abstract

说明了一种用于形成包括半导体器件和用于连接到母板的连接器的集成结构的方法。在对烧蚀辐射透明的板上形成第一层(26)，以及在半导体器件(31)上形成第二层(32)。第一层具有连接到接合焊盘(27p)的第一组导体(27)，根据与母板的连接所需的间隔，以第一间隔距离间隔接合焊盘。第二层具有连接到半导体器件的第二组导体(33)。利用间隔小于接合焊盘的间隔的栓塞/过孔连接器(29，36)连接第一层和第二层。从而将半导体器件附装到第一层，通过栓塞连接第一组和第二组导体。通过穿透板的烧蚀辐射(45)烧蚀第一层与板之间的界面，从而分离板。然后将连接器结构(47、48、49)附装到接合焊盘。该方法允许以降低的成本制造高密度封装器件。

Description

制造集成结构的方法
技术领域
本发明涉及电子器件模块的制造，所述电子器件模块包括高性能半导体器件(包括CMOS逻辑器件，DRAM存储器器件等)以及这些器件之间的互连。具体地说，本发明涉及具有提高的可靠性和降低的成本的高密度芯片互连的制造。
背景技术
随着每一代的发展，电子器件不断变得更复杂，而同时其各自的器件单元日益变小。这种朝向更大的器件密度和复杂性的趋势对器件封装技术提出了具体挑战。目前的半导体器件采用引线接合焊盘或C4焊盘制造，以将这些器件连接到下一级互连；这通常称为第一级封装。
多年来，对于多种半导体芯片技术，封装部分代表在提高系统速度方面的主要限制。同时，器件的封装代表总成本的大部分；最近的成本模拟表明，对于前沿器件，封装成本可占总成本的80％之多。
对封装技术提出挑战的复杂大规模芯片的一个实例是包括具有不同功能的多个互连芯片的片上系统(SOC)。可利用转移与连接(T&J)方法由分离的处理器或存储器芯片制造大的SOC，在该方法中，通过薄膜形成芯片至芯片的互连，其中多个芯片被接合到该薄膜上。在图1A中示出了该方法的一个实例。在玻璃晶片或板上制造具有互连布线的薄膜结构。利用栓塞/过孔连接将分别用具有布线层1a和2a的薄膜覆盖的芯片1和2接合到互连层20。在该实例中，栓塞15在互连层上形成，并利用焊料连接16连接到芯片。该栓塞与在覆盖芯片的层10(通常为聚酰亚胺)中形成的过孔11对准。平面化并用粘合剂层3覆盖芯片1和2的背面，底层晶片4附装到该粘合剂层。从互连层20去除玻璃晶片或板，留下带有接合芯片的互连布线。在芯片至芯片互连层20上形成电接合焊盘21，并在其上形成C4焊盘22。在美国专利6,444,560中说明了T&J方法的细节，在此引入该公开作为参考。
利用上述T&J方法的芯片至芯片布置可以近达25μm至60μm，其布置精度约为1μm。值得注意的是，芯片1和2可具有不同功能，并通过不同方法制造。因此T&J方法允许制造其中不同器件紧密互连的片上系统(见图1B)。
由于焊盘的间隔要求(典型的C4间距为至少150μm，通常在0.5mm至2.5mm的范围内)，用于将SOC连接到母板的C4焊盘或引线接合焊盘的使用对布线密度和封装器件的带宽产生实际限制。此外，每个C4连接有约50皮秒的信号延迟。
因此，为了(1)允许高密度器件的更有效封装，以及(2)制造具有降低的成本的器件模块，希望将上述T&J方法从芯片至芯片互连模式扩展到芯片至封装的集成技术。
发明内容
本发明提供了一种集成结构，包括半导体器件和用于将所述半导体器件连接到母板的连接器结构，以及一种制造该结构的方法。
根据本发明的第一方面，所述方法包括以下步骤：在对烧蚀辐射透明的板上形成第一层，以及在所述半导体器件上形成第二层。所述第一层具有在其中设置的第一组导体；所述第一组导体连接到接合焊盘，根据与所述母板的连接所需的间隔，以第一间隔距离间隔所述接合焊盘。所述第二层具有在其中设置的第二组导体，所述第二组导体连接到所述半导体器件。然后在所述第一层和所述第二层中的一层上形成栓塞，并在所述第一层和所述第二层中的另一层上形成第三层；以小于所述第一间隔距离的第二间隔距离间隔所述栓塞。在所述第三层中形成过孔，同样地根据所述第二间隔距离间隔所述过孔。然后将所述栓塞对准所述过孔，并将所述半导体器件附装到所述第一层，从而通过所述栓塞连接所述第一组导体与所述第二组导体。所述方法还包括利用穿透所述板的烧蚀辐射烧蚀所述第一层与所述板之间的界面，从而分离所述板的步骤。然后将所述连接器结构附装到所述接合焊盘。所述连接器结构形成针栅阵列(PGA)、球栅阵列(BGA)、C4阵列和岸面栅格阵列(LGA)中的一种。
优选将支撑结构或加强构件附装到所述第一层，以使所述支撑结构环绕所述半导体器件；可在将所述半导体器件附装到所述第一层之前或之后附装所述支撑结构。所述支撑结构的面积对应于由所述接合焊盘占用的面积。所述支撑结构的热膨胀系数(TCE)有利地约等于所述母板的热膨胀系数。用有机填充材料填充所述半导体器件与所述支撑结构之间的空隙。值得注意的是，所述第二组导体典型地为多个BEOL金属层；这些金属层的数量小于扇出(fanout)到以所述第一间隔距离间隔的所述接合焊盘所需的层数。
根据本发明的第二方面，提供了一种类似的方法，其中在所述第一层与所述第二层之间的连接器是C4连接器。因此，除了在所述半导体器件与所述加强构件之间的空隙外，在所述半导体器件与环绕所述C4连接器的所述第一层之间还存在空隙，所述空隙同样用填充材料填充。
根据本发明的另一方面，提供了一种集成结构，包括半导体器件和用于将所述半导体器件连接到母板的连接器结构。此外，所述集成结构包括在其中设置第一组导体的第一层；所述第一组导体连接到在所述层的下表面上设置的接合焊盘。根据与所述母板连接所需的间隔以第一间隔距离使所述接合焊盘相互间隔。在所述半导体器件上并与其接触地设置面对所述第一层的第二层；所述第二层具有连接到所述半导体器件的在其中设置的第二组导体。多个导体将所述第一组导体连接到所述第二组导体；所述导体为一组栓塞/过孔连接器或一组C4连接器。所述连接器以小于所述第一间隔距离的第二间隔距离相互间隔。将支撑结构或加强构件附装到所述第一层的上表面，并环绕所述半导体器件，并且用填充材料填充所述支撑结构与所述半导体器件之间的间隙。所述连接器结构连接到所述接合焊盘；所述连接器结构可形成针栅阵列(PGA)、球栅阵列(BGA)、C4阵列或岸面栅格阵列(LGA)。
附图说明
图1A是利用上述T&J方法的互连芯片的示意性截面图，其中C4连接到第一级封装；
图1B是根据图1A的T&J方法制造的片上系统(SOC)的示意图；
图2A是根据本发明的第一实施例在玻璃衬底上形成的互连布线层的示意性截面图；
图2B是为了将布线层连接到芯片，在图2A的布线层上形成的栓塞的的示意性截面图；
图3A是根据本发明，在其上形成有后段制程(BEOL)金属层的芯片的示意性截面图；
图3B是图3A的芯片的示意性截面图，具有在其中形成有过孔的附加层，用于与在图2A的布线层上的栓塞对准；
图4A示出了根据本发明的第一实施例连接到互连布线层的芯片；
图4B示出了根据本发明的第一实施例具有互连布线层上设置的加强构件的图4A的布置；
图4C是烧蚀处理的示意图，通过该处理从互连布线层去除玻璃衬底；
图4D是根据本发明完成的集成器件的示意性截面图；
图5是在其上形成有布线层、加强构件和连接栓塞的衬底的示意性截面图，其中在连接芯片前附装加强构件；
图6A是根据本发明的第二实施例具有C4连接器的芯片的示意性截面图；以及
图6B-6F示出了根据本发明的第二实施例形成集成器件的步骤。
具体实施方式
根据本发明，T&J技术用于降低在分立芯片上所需的BEOL金属层的数量，同时提供高效且成本有效的从芯片到芯片和在芯片与下一级封装之间的互连。
第一实施例：利用栓塞/过孔连接的芯片与布线层连接
在透明衬底23上将互连布线27(优选Cu)嵌入介质层26(典型地为聚酰亚胺或氧化物)(见图2A)。衬底23典型地由例如浮法(boro-float)玻璃的玻璃形成，其尺寸为直径200mm，与用于制造的晶片尺寸相当。虽然介质层26，包括互连布线27示出为单层，应理解，为便于制造，其经常被设计和制造成多层结构。介质层26中的布线层数取决于为与芯片连接匹配所需的连接密度；典型地需要3至5个金属层。Cu互连布线27连接到通常由Ni(但也可以是Cu、Au、Co或其组合)形成的接合焊盘27p。接合焊盘27p的间隔与连接到母板所需的间隔一致。例如，如果将要利用要求C4连接器至少间隔0.5mm的C4技术将互连布线27连接(在方法的稍后阶段)到母板，则焊盘27p的间隔也是0.5mm。如图2A所示，可提供薄介质材料层，以覆盖焊盘27p并从而分离焊盘与衬底23。
在介质层26的顶部上形成对准结构25，以形成与芯片的物理和电连接(见图2B)。在该实施例中，对准结构具有在互连布线层上形成的栓塞，以与在覆盖芯片的另一层上形成的过孔对准。形成连接器焊盘29p，以连接到Cu布线的顶层。焊盘29p具有在其上形成的栓塞29；该栓塞可由Ni、Cu、镀敷Ni的Cu、W或者其它金属或金属组合形成。用热塑聚合物粘合剂层的层28覆盖介质层26的上表面；栓塞29从该层突出。层28用作粘合剂，用于随后将芯片接合到介质层26。在各栓塞29的表面上形成低熔点合金材料的层30；这便于在芯片连接处理期间形成电连接。该材料典型地是90/10的Pb/Sn焊料，厚2μm或更小；可选的合金材料包括Au/Sn和Sn/Ag。可对合金材料进行热回流处理，以使层30得到圆形形状，如图2B所示；这便于栓塞与在芯片上形成的过孔结构对准。
根据本领域已知的方法制造芯片31。在本领域中熟知，在芯片的顶表面31t形成金属布线层33(嵌入并被介质层32环绕)。这些布线层通常称为“后段制程”或BEOL层。与本领域的当前状态相比，不必形成BEOL层，该BEOL层扇出到面密度降低的C4焊盘或引线接合焊盘，以连接到芯片封装；下面将更详细地说明，不利用C4或引线接合焊盘，形成在本实施例中芯片与封装之间的连接。因此，所需的BEOL金属布线层33的数量通常从6或7(典型地该扇出所需的数量)减少到3或4(见图3A)。这具有改善芯片成品率和降低芯片制造成本的效果。
用介质层35覆盖最后的金属层(见图3B)。层35典型地是用于薄膜封装处理的聚酰亚胺材料。层35具有在其中形成的过孔36。如图3B所示，可形成具有倾斜的壁面角度的过孔，该壁面角度用于指导在过孔36中高精度、自对准放置栓塞29。在各过孔36的底部是连接到下面的金属层的导体。可将过孔的壁面角度制造成接近垂直或倾斜。典型地在直至此时的晶片级制造芯片，然后将其切割成分立的芯片，用于连接到封装。
应注意，可同时处理芯片31(以及BEOL金属布线层33)和对准结构25(以及介质层26)。由于相对于常规芯片封装系统降低了BEOL金属布线层的数量，这也产生提高处理能力和降低成本的效果。
然后对准芯片31与对准结构，从而使栓塞29与过孔36匹配，如图4A所示。优选在适度提高的温度下进行该对准，以在与层35的表面接触之前，使粘合剂层28轻微“发粘”。这可防止在随后的接合操作中芯片31的移动。
如图4A所述，互连区域的尺寸通常大于芯片区域。这是由于在母板上连接的密度较低，其中连接器的典型间距在0.5mm至2.5mm的范围内。用加强构件(或多个加强构件)填充环绕芯片的区域40，所述加强构件利用粘合剂层28附装到薄膜互连层的顶部。如图4B所示，在加强构件41中心中的孔稍大于芯片31。在加强构件中可形成其它开口，以允许邻近芯片31在表面28a上附装其它器件(例如解耦电容器)。加强构件具有在其顶表面上形成的热塑聚酰亚胺层或其它粘合剂层42，然后翻转该加强构件，并将其附装到层28。加强构件可由陶瓷、金属或有机材料制成；加强构件材料的选择将取决于机械强度和可靠性要求。还希望加强构件材料的热膨胀系数(TCE)接近于母板的TCE。可选择加强构件41的厚度，以使加强构件的背面41b与芯片的背面31b在相同高度，如图4B所示。可选地，可使加强构件较厚，以更好地容纳在表面31b上热冷却焊料、导热化合物或其它热沉的放置。
置于粘合剂层28上后，在提高的温度和压力下利用层压方法将芯片31和加强构件41接合到薄膜互连结构(即在其上具有介质层26和粘合剂层28的衬底23)。根据所采用的特定材料，在10至200psi的压力，150至400℃的温度下进行接合。根据层压方法工具的设计，可在全尺寸(用于制造的典型晶片的尺寸，直径200mm至300mm)或较小的切割尺寸(例如边长100至300mm)的玻璃衬底上进行接合操作。接合操作使焊料30流动，并至少部分填充过孔36，形成与BEOL金属布线层33的电连接。从而从芯片31，穿过金属布线层33、栓塞29和互连布线27，直到接合焊盘27p，形成电连接。
然后用有机材料(聚酰亚胺或底填材料)填充芯片与加强构件之间的窄空隙43，以确保芯片31、加强构件41和介质层26形成刚性系统。
然后对层压结构进行激光烧蚀处理，如图4C示意性所示。入射在透明衬底23上的激光辐射45穿透板，并烧蚀板与介质层26之间的界面。这导致板从介质层26脱离，从而去除该板。然后通过灰化和激光烧蚀任何聚酰亚胺残留物，露出互连层结构中的焊盘27p。
露出焊盘后，处理芯片/加强构件/互连结构，以得到用于连接到母板的模块。此时通常将该结构切割成分立的模块，并对其进行适当的电测试。然后在焊盘27p上形成连接器冶金，如图4D所示。连接器可以是针栅阵列(PGA)插针47、球栅阵列(BGA)或C4焊料球48，或者岸面栅格(LGA)结构49。如上所述，可邻近芯片31在加强构件开口中提供空间，用于解耦电容器等；因此，互连层的整个底面26b可用于放置连接器结构47、48或49。
应注意，与常规设置相比，在图4D中示意性示出的完整结构具有提高的互连密度和更高的可靠性。与现有封装器件的150μm间距相比，与芯片的连接器(在该实施例中为栓塞29)的典型间距为10μm。此外，可消除芯片与互连之间的C4焊料连接，从而避免C4疲劳可靠性的问题。另外，如果选择加强构件，使其TCE与母板的TCE匹配，可避免热应力可靠性问题。
应理解，还可通过颠倒图2B和3B中所示的栓塞和过孔的位置，实现芯片31与介质层26之间的栓塞/过孔连接；也就是说，可以在芯片31的BEOL布线层上形成栓塞，而在介质层26上形成具有过孔的聚酰亚胺层。
还应注意，透明衬底23可以是任何方便的尺寸和形状以容纳芯片。例如，如果各芯片31边长25mm，并位于边长60mm的加强构件中心，则在边长200mm的板上可方便地加工3×3的芯片阵列。
如果希望在将芯片附装于其上之前确保互连层为刚性的，在芯片连接方法之前可将加强构件41附装到粘合剂层28(利用对该加强构件施加的粘合剂层42)，如图5所示。随后如以上参考图4A-4C所述，附装并接合芯片，并去除衬底23，以得到图4D所示的集成结构。
第二实施例：利用C4连接的芯片与布线层连接
在该实施例中，利用常规C4连接器实现芯片61与互连布线27之间的连接。如图6A所示，芯片61具有嵌入介质层62中的BEOL金属布线层，其中最后的金属层连接到焊盘63，在该焊盘63上形成C4焊料球64。将互连布线67(优选Cu)嵌入在透明衬底68上的介质层66(典型地为聚酰亚胺或氧化物)中。与第一实施例相同，互连布线也连接到接合焊盘67p(见图6B；比较图2A)。加强构件41具有在其顶部的粘合剂层42，然后将其翻转并连接到层66，以形成图6C的结构。与第一实施例相同，在该加强构件中心中的孔稍大于芯片61。
然后通过常规C4芯片连接方法将芯片连接到互连布线层(图6D)。然后用有机材料71填充芯片与加强构件之间的整个空隙，包括芯片下方和C4连接器周围的任何空间(图6E)。该步骤可视为“空隙填充”和“C4底填”处理。最后，与第一实施例相同，通过激光烧蚀方法从层66去除透明衬底68，露出接合焊盘67p，并将适合的结构(PGA、BGA、C4或LGA)附装到焊盘，以连接到母板(图6F)。
工业适用性
本发明可通用于包括高性能半导体器件的电子器件模块的制造，具体地说高密度互连的制造。本发明提供了一种用于形成集成、高密度、高性能芯片互连系统的方法，其具有多个优点：(1)与现有系统相比，栓塞/过孔连接的利用减小了芯片互连的间距；(2)由TCE可调的加强构件环绕各芯片；(3)总芯片/封装成本降低了预计50％；(4)可同时制造芯片和互连；(5)除了连接器，互连的底面没有组件或结构，从而减小了集成模块的总面积。
虽然根据具体实施例说明了本发明，通过上述说明明显的是，多种替换、修改和变型对于本领域的技术人员将是显而易见的。因此，本发明旨在包括落入本发明以及以下权利要求书的精神和范围内的所有这些替换、修改和变型。

Claims (9)

1.一种制造集成结构的方法，所述集成结构包括半导体器件(31)和用于将所述半导体器件连接到母板的连接器结构(47、48、49)，所述方法包括以下步骤：
在对烧蚀辐射透明的板(23)上形成第一层(26)，所述第一层具有在其中设置的第一组导体(27)，所述第一组导体连接到接合焊盘(27p)，根据与所述母板的连接所需的间隔，以第一间隔距离间隔所述接合焊盘；
在所述半导体器件(31)上形成第二层(32)，所述第二层具有在其中设置的第二组导体(33)，所述第二组导体连接到所述半导体器件；
在所述第一层和所述第二层中的一层上形成栓塞(29)，并在所述第一层和所述第二层中的另一层上形成第三层(35)，以小于所述第一间隔距离的第二间隔距离间隔所述栓塞；
在所述第三层中形成过孔(36)，根据所述第二间隔距离间隔所述过孔；
将所述栓塞(29)对准所述过孔(36)；
将所述半导体器件附装到所述第一层，从而通过所述栓塞连接所述第一组导体与所述第二组导体；
将支撑结构(41)附装到所述第一层，以使所述支撑结构环绕所述半导体器件，所述支撑结构的面积对应于由所述接合焊盘占用的面积；
利用穿透所述板的烧蚀辐射(45)烧蚀所述第一层与所述板之间的界面，从而分离所述板；以及
将所述连接器结构附装到所述接合焊盘。
2.根据权利要求1的方法，其中所述连接器结构形成针栅阵列PGA(47)、球栅阵列BGA、C4阵列(48)和岸面栅格阵列LGA(49)中的一种。
3.根据权利要求1的方法，其中在所述将所述半导体器件附装到所述第一层的步骤之前和在所述烧蚀步骤之前进行所述将所述支撑结构附装到所述第一层的步骤。
4.根据权利要求1的方法，其中在所述将所述半导体器件附装到所述第一层的步骤之后和在所述烧蚀步骤之前进行所述将所述支撑结构附装到所述第一层的步骤。
5.根据权利要求1的方法，其中所述母板特征在于热膨胀系数，以及所述支撑结构的热膨胀系数等于所述母板的热膨胀系数。
6.根据权利要求1的方法，还包括填充所述半导体器件与环绕的所述支撑结构之间的空隙的步骤。
7.根据权利要求1的方法，还包括在所述将所述连接器结构附装到所述接合焊盘的步骤之前，露出所述接合焊盘的步骤。
8.根据权利要求1的方法，其中在所述第一层上形成所述栓塞，并且所述第一层具有粘合剂层(28)，用于接合到所述第三层。
9.根据权利要求1的方法，其中所述第二组导体设置于多个金属层中，所述金属层的数量小于扇出到以所述第一间隔距离间隔的所述接合焊盘所需的层数。
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Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6642136B1 (en) * 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US8021976B2 (en) 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US6815324B2 (en) * 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US7902679B2 (en) * 2001-03-05 2011-03-08 Megica Corporation Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
TWI313507B (en) 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US7099293B2 (en) 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
TWI245402B (en) * 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US7394161B2 (en) * 2003-12-08 2008-07-01 Megica Corporation Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto
TWI236122B (en) * 2004-02-27 2005-07-11 Via Tech Inc A low thermal expansion build-up layer packaging and a method to package a die using the same
TWI237883B (en) * 2004-05-11 2005-08-11 Via Tech Inc Chip embedded package structure and process thereof
JP4865197B2 (ja) * 2004-06-30 2012-02-01 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8067837B2 (en) 2004-09-20 2011-11-29 Megica Corporation Metallization structure over passivation layer for IC chip
JP4528062B2 (ja) * 2004-08-25 2010-08-18 富士通株式会社 半導体装置およびその製造方法
US20060145356A1 (en) * 2005-01-06 2006-07-06 International Business Machines Corporation On-chip cooling
TWI255518B (en) * 2005-01-19 2006-05-21 Via Tech Inc Chip package
US8294279B2 (en) * 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
JP3914239B2 (ja) * 2005-03-15 2007-05-16 新光電気工業株式会社 配線基板および配線基板の製造方法
JP4790297B2 (ja) * 2005-04-06 2011-10-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2007123524A (ja) * 2005-10-27 2007-05-17 Shinko Electric Ind Co Ltd 電子部品内蔵基板
TWI281737B (en) * 2005-12-13 2007-05-21 Via Tech Inc Chip package and coreless package substrate thereof
JP2007242888A (ja) * 2006-03-08 2007-09-20 Sony Corp 半導体パッケージ製造方法
JP3942190B1 (ja) * 2006-04-25 2007-07-11 国立大学法人九州工業大学 両面電極構造の半導体装置及びその製造方法
US8164773B2 (en) 2006-05-26 2012-04-24 Marvell World Trade Ltd. Wireless system-in-package and image processing control apparatus
KR100856326B1 (ko) * 2006-07-19 2008-09-03 삼성전기주식회사 레이저 리프트 오프를 이용한 유전체 박막을 갖는 박막 커패시터 내장된 인쇄회로기판 제조방법, 및 이로부터 제조된 박막 커패시터 내장된 인쇄회로기판
US7985621B2 (en) 2006-08-31 2011-07-26 Ati Technologies Ulc Method and apparatus for making semiconductor packages
US8373266B2 (en) * 2007-03-29 2013-02-12 Continental Automotive Systems, Inc. Heat sink mounted on a vehicle-transmission case
US7893527B2 (en) * 2007-07-24 2011-02-22 Samsung Electro-Mechanics Co., Ltd. Semiconductor plastic package and fabricating method thereof
EP2056655B1 (en) * 2007-09-03 2012-06-20 Panasonic Corporation Wiring board
JP5245485B2 (ja) * 2008-03-25 2013-07-24 富士電機株式会社 半導体装置の製造方法
US8259454B2 (en) * 2008-04-14 2012-09-04 General Electric Company Interconnect structure including hybrid frame panel
KR100956688B1 (ko) * 2008-05-13 2010-05-10 삼성전기주식회사 인쇄회로기판 및 그 제조방법
US8637953B2 (en) 2008-07-14 2014-01-28 International Business Machines Corporation Wafer scale membrane for three-dimensional integrated circuit device fabrication
US7989950B2 (en) * 2008-08-14 2011-08-02 Stats Chippac Ltd. Integrated circuit packaging system having a cavity
US8823160B2 (en) * 2008-08-22 2014-09-02 Stats Chippac Ltd. Integrated circuit package system having cavity
WO2010030962A2 (en) * 2008-09-12 2010-03-18 Kumar Ananda H Structures and methods for wafer packages, and probes
US9006028B2 (en) * 2008-09-12 2015-04-14 Ananda H. Kumar Methods for forming ceramic substrates with via studs
US8093099B2 (en) * 2008-09-26 2012-01-10 International Business Machines Corporation Lock and key through-via method for wafer level 3D integration and structures produced
US9064717B2 (en) * 2008-09-26 2015-06-23 International Business Machines Corporation Lock and key through-via method for wafer level 3D integration and structures produced thereby
US7855455B2 (en) * 2008-09-26 2010-12-21 International Business Machines Corporation Lock and key through-via method for wafer level 3 D integration and structures produced
US8143097B2 (en) 2009-09-23 2012-03-27 Stats Chippac, Ltd. Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
US9875911B2 (en) 2009-09-23 2018-01-23 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interposer with opening to contain semiconductor die
US8901724B2 (en) 2009-12-29 2014-12-02 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
US8247895B2 (en) 2010-01-08 2012-08-21 International Business Machines Corporation 4D device process and structure
US8330262B2 (en) 2010-02-02 2012-12-11 International Business Machines Corporation Processes for enhanced 3D integration and structures generated using the same
JP2011176112A (ja) * 2010-02-24 2011-09-08 Renesas Electronics Corp 半導体集積回路及びその製造方法
US8710639B2 (en) * 2010-04-08 2014-04-29 Nec Corporation Semiconductor element-embedded wiring substrate
US8618652B2 (en) * 2010-04-16 2013-12-31 Intel Corporation Forming functionalized carrier structures with coreless packages
US8415792B2 (en) 2010-08-04 2013-04-09 International Business Machines Corporation Electrical contact alignment posts
JP2012049421A (ja) * 2010-08-30 2012-03-08 Keihin Corp 電子部品の実装構造
US8623763B2 (en) * 2011-06-01 2014-01-07 Texas Instruments Incorporated Protective layer for protecting TSV tips during thermo-compressive bonding
US20150325527A1 (en) * 2013-01-28 2015-11-12 Hewlett-Packard Development Company, Lp. Radiused alignment post for substrate material
US20140295623A1 (en) * 2013-03-29 2014-10-02 Kinsus Interconnect Technology Corp. Method of packaging a chip and a substrate
US9994741B2 (en) 2015-12-13 2018-06-12 International Business Machines Corporation Enhanced adhesive materials and processes for 3D applications
US9953934B2 (en) * 2015-12-16 2018-04-24 Intel Corporation Warpage controlled package and method for same
US20180053665A1 (en) * 2016-08-19 2018-02-22 Mediatek Inc. Pre-bumped redistribution layer structure and semiconductor package incorporating such pre-bumped redistribution layer structure
US20190259731A1 (en) * 2016-11-09 2019-08-22 Unisem (M) Berhad Substrate based fan-out wafer level packaging
US20180130720A1 (en) * 2016-11-09 2018-05-10 Unisem (M) Berhad Substrate Based Fan-Out Wafer Level Packaging
US20180130768A1 (en) * 2016-11-09 2018-05-10 Unisem (M) Berhad Substrate Based Fan-Out Wafer Level Packaging
US11062773B2 (en) * 2019-05-13 2021-07-13 Ememory Technology Inc. Near-memory computation system for analog computing

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1180932A (zh) * 1996-10-25 1998-05-06 国际商业机器公司 同轴互连器件及其制造方法
US6444560B1 (en) * 2000-09-26 2002-09-03 International Business Machines Corporation Process for making fine pitch connections between devices and structure made by the process

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160645A (ja) * 1984-02-01 1985-08-22 Hitachi Ltd 積層半導体集積回路装置
US4670770A (en) 1984-02-21 1987-06-02 American Telephone And Telegraph Company Integrated circuit chip-and-substrate assembly
US4884122A (en) 1988-08-05 1989-11-28 General Electric Company Method and configuration for testing electronic circuits and integrated circuit chips using a removable overlay layer
US4783695A (en) 1986-09-26 1988-11-08 General Electric Company Multichip integrated circuit packaging configuration and method
US4933042A (en) 1986-09-26 1990-06-12 General Electric Company Method for packaging integrated circuit chips employing a polymer film overlay layer
US4949148A (en) 1989-01-11 1990-08-14 Bartelink Dirk J Self-aligning integrated circuit assembly
US5019535A (en) 1989-03-28 1991-05-28 General Electric Company Die attachment method using nonconductive adhesive for use in high density interconnected assemblies
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5373627A (en) 1993-11-23 1994-12-20 Grebe; Kurt R. Method of forming multi-chip module with high density interconnections
JPH08330360A (ja) * 1995-05-31 1996-12-13 Nec Corp 半導体装置及びその製造方法
US5835355A (en) * 1997-09-22 1998-11-10 Lsi Logic Corporation Tape ball grid array package with perforated metal stiffener
EP0926729A3 (en) * 1997-12-10 1999-12-08 Mitsubishi Gas Chemical Company, Inc. Semiconductor plastic package and process for the production thereof
US5998868A (en) 1998-02-04 1999-12-07 International Business Machines Corporation Very dense chip package
US6087199A (en) 1998-02-04 2000-07-11 International Business Machines Corporation Method for fabricating a very dense chip package
US6025638A (en) 1998-06-01 2000-02-15 International Business Machines Corporation Structure for precision multichip assembly
US6316786B1 (en) 1998-08-29 2001-11-13 International Business Machines Corporation Organic opto-electronic devices
US6066513A (en) 1998-10-02 2000-05-23 International Business Machines Corporation Process for precise multichip integration and product thereof
US6281452B1 (en) * 1998-12-03 2001-08-28 International Business Machines Corporation Multi-level thin-film electronic packaging structure and related method
US6110806A (en) 1999-03-26 2000-08-29 International Business Machines Corporation Process for precision alignment of chips for mounting on a substrate
JP2001035960A (ja) * 1999-07-21 2001-02-09 Mitsubishi Electric Corp 半導体装置および製造方法
JP2001267474A (ja) * 2000-03-21 2001-09-28 Rohm Co Ltd 半導体装置
TW503531B (en) * 2000-09-28 2002-09-21 Toshiba Corp Multi-layered semiconductor apparatus
US6600224B1 (en) * 2000-10-31 2003-07-29 International Business Machines Corporation Thin film attachment to laminate using a dendritic interconnection
US6607942B1 (en) * 2001-07-26 2003-08-19 Taiwan Semiconductor Manufacturing Company Method of fabricating as grooved heat spreader for stress reduction in an IC package
US6472762B1 (en) * 2001-08-31 2002-10-29 Lsi Logic Corporation Enhanced laminate flipchip package using a high CTE heatspreader
US6599778B2 (en) * 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
JP3879516B2 (ja) * 2002-01-16 2007-02-14 日立電線株式会社 配線基板の製造方法及び配線基板
JP3908157B2 (ja) * 2002-01-24 2007-04-25 Ｎｅｃエレクトロニクス株式会社 フリップチップ型半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1180932A (zh) * 1996-10-25 1998-05-06 国际商业机器公司 同轴互连器件及其制造方法
US6444560B1 (en) * 2000-09-26 2002-09-03 International Business Machines Corporation Process for making fine pitch connections between devices and structure made by the process

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