TWI819506B - 一種嵌埋封裝結構及其製造方法 - Google Patents

一種嵌埋封裝結構及其製造方法 Download PDF

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TWI819506B
TWI819506B TW111107546A TW111107546A TWI819506B TW I819506 B TWI819506 B TW I819506B TW 111107546 A TW111107546 A TW 111107546A TW 111107546 A TW111107546 A TW 111107546A TW I819506 B TWI819506 B TW I819506B
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Taiwan
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layer
copper
dielectric
copper pillar
wiring
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TW111107546A
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TW202301625A (zh
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陳先明
馮磊
黃本霞
寶玥
王聞師
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大陸商南通越亞半導體有限公司
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Abstract

本申請公開了一種多層嵌埋封裝結構，包括第一介電層和在所述第一介電層上的第二介電層，所述第一介電層包括第一佈線層，所述第二介電層包括沿高度方向貫穿所述第二介電層的第一銅柱層和器件放置口框以及在所述第一銅柱層上的第二佈線層，在所述第二佈線層上設置有第二銅柱層，所述第一佈線層和所述第二佈線層通過所述第一銅柱層導通連接，其中在所述器件放置口框的底部貼裝有第一器件，使得所述第一器件的端子與所述第一佈線層導通連接，在所述第二介電層上貼裝有第二器件，使得所述第二器件的端子與所述第二佈線層導通連接，在所述第二銅柱層的端部貼裝有第三器件，使得所述第三器件的端子與所述第二銅柱層導通連接。還公開了一種多層嵌埋封裝結構的製造方法。

Description

一種嵌埋封裝結構及其製造方法
本發明涉及電子器件封裝結構，具體涉及嵌埋封裝結構及其製造方法。
隨著電子技術發展日新月異，電子產品層出不窮，相關電子產品在智能化，集成化的道路上越行越遠，相關電子產品小型化和集成化成為市場的主流。小型化智能化意味著組成電子產品的核心部分各電子部件提出更高的要求，如何製造更低成本，更快的速度，更可靠性能，更小的尺寸是積體電路封裝追求的目標。
半導體前端晶圓製造從原有的幾十納米到十幾納米到幾納米，技術不斷拓展挑戰各種不可能。引領未來積體電路封裝通過不斷減少的最小特徵尺寸來提高各電子器件的集成密度。
目前先進的封裝方法包括：晶圓級晶片規模封裝(Wafer Level Chip Scale Packaging，WLCSP)，扇出型晶圓級封裝(Fan-Out Wafer Level Package，FOWLP)，倒裝晶片(FlipChip)，疊層封裝(Package on Package，POP)，扇出型面板級封裝(Fan-out Panel level Package,FOPLP)。扇出型封裝相對常規的晶圓級封裝具有獨特的優點：①I/O間距靈活，不依賴於晶片尺寸；②只使用有效裸片(die)，產品良率提高；③具有靈活的3D封裝路徑，即可以在頂部形成任意陣列的圖形；④具有較好的電性能及熱性能；⑤高頻應用； ⑥容易在重新佈線層(RDL)中實現高密度佈線。扇出型封裝方法一般為：提供承載襯底，在襯底表面形成粘合層；在粘合層上光刻、電鍍出重新佈線層(Redistribution Layers，RDL)；採用晶片鍵合工藝將半導體晶片安裝到重新佈線層上；採用注塑工藝將半導體晶片塑封於塑封材料層中；去除襯底和粘合層；在重新佈線層上光刻、電鍍形成凸塊下金屬層(UBM)；在UBM上進行植球回流，形成焊料凸塊。
而扇出型封裝中的面板級封裝較晶圓級封裝因基板尺寸更大故而容納的零部件是晶圓級的數倍，在制程能力滿足同等競爭中更具造價優勢。
扇出型封裝結構存在輸入/輸出端口不夠多及封裝結構尺寸較大等缺陷。如何解決在面板級扇出封裝中輸入/出端口數量不夠多以及如何縮小產品尺寸成為關鍵點。
現有技術CN111106013A公開了一種TMV(Through Molding Via)結構的製備方法以及大面板扇出型異構集成封裝結構，如圖1所述，該封裝結構利用面板級技術製作晶片塑封板10，採用鐳射電鍍的方式製作TMV結構12，提供天線13和表貼元件11並製作連接線路15相連，在塑封板另一側製作再佈線層16以及焊球17。
但是，現有技術鐳射或鑽孔加工技術加工效率較低，生產成本高；TMV製作無論鐳射或機加工鑽孔相關加工精度較差、結構形狀尺寸單一、對大尺寸多形狀TMV結構無法很好應對；鐳射填孔電鍍，銅柱與介電層結合力較差(銅柱外表面無法處理)，影響產品可靠性；並且鐳射填孔電鍍的銅柱上下成錐形，銅柱縱向尺寸差異不利於散熱及信號的傳輸與穩 定。
本發明的實施方案涉及提供一種嵌埋封裝結構及其製造方法，以解決上述技術問題。本發明通過將器件線上路佈置後植入，可以根據基板的良率進行選擇性植入減少器件的損耗，並且器件通過POP背靠背堆疊的方式，增加了I/O數，減少了將器件水準排布時的面積占比；線路和銅柱圖形可以根據實際需要任意設定，僅通過圖形影像電鍍即可實現，線路和銅柱上下尺寸均勻，對封裝體散熱以及信號傳輸穩定更有優勢，銅柱電鍍後對銅柱表面做棕化處理，增加了銅柱和介電層的結合力。
本發明第一方面涉及一種多層嵌埋封裝結構，包括第一介電層和在所述第一介電層上的第二介電層，所述第一介電層包括第一佈線層，所述第二介電層包括沿高度方向貫穿所述第二介電層的第一銅柱層和器件放置口框以及在所述第一銅柱層上的第二佈線層，在所述第二佈線層上設置有第二銅柱層，所述第一佈線層和所述第二佈線層通過所述第一銅柱層導通連接，其中在所述器件放置口框的底部貼裝有第一器件，使得所述第一器件的端子與所述第一佈線層導通連接，在所述第二介電層上貼裝有第二器件，使得所述第二器件的端子與所述第二佈線層導通連接，在所述第二銅柱層的端部貼裝有第三器件，使得所述第三器件的端子與所述第二銅柱層導通連接。
在一些實施方案中，在所述第一器件和第二器件與所述封裝結構的空隙中填充有介電材料，形成塑封層。
在一些實施方案中，所述第一介電層和所述第二介電層包括 有機介電材料、無機介電材料或它們的組合。優選地，所述第一介電層和所述第二介電層包括聚醯亞胺、環氧樹脂，雙馬來醯亞胺三嗪樹脂、陶瓷填料、玻璃纖維或它們的組合。
在一些實施方案中，在所述第三器件上覆蓋有第三介電層。
在一些實施方案中，所述第一器件和所述第二器件包括具有雙面端子的器件，使得所述第二器件的端子與所述第一器件的端子導通連接，所述第二器件的端子與所述第三器件的端子導通連接。
優選地，所述第一、第二和第三器件分別包括至少一個器件。
在一些實施方案中，在所述第一介電層的底面上設置有阻焊層和阻焊開窗。
本發明的第二方面提供一種多層嵌埋封裝結構的製造方法，包括如下步驟：
(a)在臨時承載板上形成第一佈線層，在所述第一佈線層上層壓第一介電層，減薄所述第一介電層以暴露出上述第一佈線層；
(b)在所述第一介電層上形成第一銅柱層，所述第一銅柱層包括犧牲銅柱，在所述第一銅柱層上層壓第二介電層，減薄所述第二介電層以暴露出所述第一銅柱層；
(c)在所述第二介電層上形成第二佈線層，使得所述第一佈線層和所述第二佈線層通過所述第一銅柱層導通連接；
(d)在所述第二佈線層上形成第二銅柱層；
(e)蝕刻所述犧牲銅柱，形成暴露出所述第一佈線層的器件放置口框；
(f)移除所述臨時承載板。
在一些實施方案中，所述製造方法還包括：
(g)在所述器件放置口框的底部貼裝第一器件，使得第一器件的端子與第一佈線層導通連接；
(h)在所述第二佈線層上貼裝第二器件，使得所述第二器件的端子與所述第二佈線層導通連接；
(i)在所述第二銅柱層的端部貼裝第三器件，使得所述第三器件的端子與所述第二銅柱層導通連接。
優選地，所述製造方法還包括：
(h')在步驟h之後和步驟i之前，填充介電材料形成覆蓋所述第一器件和所述第二器件的塑封層。
優選地，所述製造方法還包括：
(i')在步驟i之後，層壓介電材料形成覆蓋所述第三器件的塑封層。
在一些實施方案中，步驟(a)還包括：
(a1)在所述臨時承載板上施加第一光刻膠層，曝光顯影形成第一特徵圖案；
(a2)在所述第一特徵圖案中電鍍形成第一佈線層，並移除所述第一光刻膠層；
(a3)在所述第一佈線層上層壓第一介電層，並減薄所述第一介電層以暴露所述第一佈線層。
優選地，所述臨時承載板包括雙面覆銅板，其中所述雙面覆 銅板包括半固化片、在所述半固化片表面上的第一銅層和在所述第一銅層上的第二銅層，其中所述第一銅層和所述第二銅層通過物理壓合附著在一起。優選地，步驟(e)包括通過將所述第一銅層和所述第二銅層物理分離，並蝕刻所述第二銅層，以移除所述雙面覆銅板。
在一些實施方案中，步驟(b)還包括：
(b1)在所述第一介電層上形成金屬種子層；
(b2)在所述金屬種子層上施加第二光刻膠層，曝光顯影形成第二特徵圖案；
(b3)在所述第二特徵圖案中電鍍形成蝕刻防護層；
(b4)施加第三光刻膠層，曝光顯影形成第三特徵圖案；
(b5)在所述第三特徵圖案中電鍍形成第一銅柱層和在所述蝕刻防護層上的犧牲銅柱，並去除所述第二光刻膠層和所述第三光刻膠層；
(b6)在所述第一特徵層和所述犧牲銅柱上層壓第二介電層，並減薄所述第二介電層以暴露所述第一特徵層和所述犧牲銅柱。
在一些實施方案中，所述蝕刻防護層包括鎳、鈦或它們的組合。
在一些實施方案中，步驟(c)還包括：
(c1)在所述第二介電層上形成金屬種子層；
(c2)在所述金屬種子層上施加第四光刻膠層，曝光顯影形成第四特徵圖案；
(c3)在所述第四特徵圖案中電鍍銅形成第二佈線層，並移除所述第四光刻膠層。
在一些實施方案中，步驟(d)包括
(d1)在所述第二佈線層上施加第五光刻膠層，曝光顯影形成第五特徵圖案；
(d2)在所述第五特徵圖案中電鍍銅形成第二銅柱層；
(d3)移除所述第五光刻膠層，並蝕刻暴露的所述金屬種子層。
優選地，所述金屬種子層包括鈦、銅、鈦鎢合金或它們的組合。
在一些實施方案中，步驟(d)還包括：
(d1)在所述第二佈線層上施加第六光刻膠層，曝光顯影形成第六特徵圖案；
(d2)在所述第六特徵圖案中蝕刻所述犧牲銅柱及所述蝕刻防護層，形成器件放置口框。
在一些實施方案中，所述製造方法還包括在步驟f的移除所述臨時承載板之後，在所述第一介電層的底面上施加阻焊層，並對暴露的金屬進行表面處理形成阻焊開窗。
10:晶片塑封板
11:表貼元件
12:TMV結構
13:天線
15:連接線路
16:再佈線層
17:焊球
100、200、300、400:封裝結構
101:第一介電層
102:第二介電層
103:第三介電層
104:第四介電層
1011a:PP層
1011b:第一銅層
1011c:第二銅層
1011d:保護層
1012:第一光刻膠層
1013:第一佈線層
1020、1031:金屬種子層
1021:第二光刻膠層
1022:蝕刻防護層
1023:第三光刻膠層
1024:第一銅柱層
1025:犧牲銅柱
1026:器件放置口框
1032:第二佈線層
1033:第二銅柱層
1034:第四光刻膠層
1036:第六光刻膠層
1051:第一器件
1052:第二器件
1053:第三器件
106:阻焊層
1061:阻焊開窗
為了更好地理解本發明並示出本發明的實施方式，以下純粹以舉例的方式參照附圖。
具體參照附圖時，必須強調的是特定的圖示是示例性的並且目的僅在於說明性地討論本發明的優選實施方案，並且基於提供被認為是對於本發明的原理和概念方面的描述最有用和最易於理解的圖示的原因而 被呈現。就此而言，沒有試圖將本發明的結構細節以超出對本發明基本理解所必須的詳細程度來圖示；參照附圖的說明使本領域技術人員認識到本發明的幾種形式可如何實際體現出來。在附圖中：
圖1為現有技術中一種TMV結構的製備方法、大板扇出型異構集成封裝結構的截面示意圖；
圖2為根據本發明的一個實施方案的嵌埋封裝結構的截面示意圖；
圖3為根據本發明的另一個實施方案的嵌埋封裝結構的截面示意圖；
圖4為根據本發明的另一個實施方案的嵌埋封裝結構的截面示意圖；
圖5為根據本發明的另一個實施方案的嵌埋封裝結構的截面示意圖；
圖6(a)~6(p)示出本發明一個實施方案的封裝結構的製造方法的各步驟中間結構的截面示意圖。
參照圖2，示出嵌埋封裝結構100的截面示意圖。封裝結構100包括第一介電層101和位於第一介電層101的第一表面上的第二介電層102。第一介電層101和第二介電層102可以包括相同的材料，也可以包括不同的材料；可以包括有機介電材料、無機介電材料或它們的組合，優選，聚醯亞胺、環氧樹脂，雙馬來醯亞胺三嗪樹脂(BT)、陶瓷填料、玻璃纖維或它們的組合。
第一介電層101包括第一佈線層1013，第一佈線層1013在第一介電層101的第一表面上暴露，第二介電層102包括沿高度方向貫穿第二介電層102的第一銅柱層1024以及器件放置口框1026，第二介電層102上設置有第二佈線層1032，第二佈線層1032上設置有第二銅柱層1033，第一佈線層1013和第二佈線層1032通過第一銅柱層1024導通連接。第二介電層102包括第一銅柱層1024，第一銅柱層1024為銅銅柱層作為IO通道，其截面尺寸可以相同，也可以不同。第二銅柱層1033同樣作為IO通道。在植入器件之前佈置佈線層，可以根據基板的良率進行選擇性植入，減少器件損耗。
器件放置口框1026的底部貼裝有第一器件1051，第二佈線層1032上貼裝有第二器件1052，第二銅柱層1033的端部貼裝有第三器件1053，第一器件1051和第二器件1052與結構100之間的空隙可以填充介電材料以形成塑封層。第一器件1051、第二器件1052和第三器件1053採用背靠背堆疊設置，可以顯著增加單位面積I/O數，減少了將器件水準排布時的面積占比。
如圖2所示，封裝結構100還包括在第一介電層101的第二表面上形成的阻焊層106，阻焊層106內設置有阻焊開窗1061。
參照圖3，示出嵌埋封裝結構200的截面示意圖。封裝結構200與封裝結構100之間的區別在於，第一器件1051、第二器件1052均具有雙面端子，其中第一器件1051的端子和第二器件1052的端子導通連接，第二器件1052的端子與第三器件1053的端子導通連接。
參照圖4，示出嵌埋封裝結構300的截面示意圖。封裝結構300與封裝結構100之間的區別在於，在第二介電層102上設置有第三介電層103，第三介電層103包覆第二佈線層1032和第二銅柱層1033；第三介電層103 上設置有第四介電層104，第四介電層104包覆第三器件1053。第三介電層103和第一介電層101可以包括相同的材料，也可以包括不同的材料；第四介電層104和第一介電層101可以包括相同的材料，也可以包括不同的材料，優選，第四介電層104選自有機介電材料或感光介電材料，例如，有機介電材料可以為ABF或PP，感光介電材料可以為PID。
參照圖5，示出嵌埋封裝結構400的截面示意圖。封裝結構400與封裝結構300之間的區別在於，第一器件1051、第二器件1052均具有雙面端子，第一器件1051的端子和第二器件1052的端子導通連接，第二器件1052的端子與第三器件1053的端子導通連接。
參照圖6(a)~6(p)，示出本發明一個實施方案的多層嵌埋封裝結構的製造方法的各個步驟的中間結構的截面示意圖。
所述製造方法包括如下步驟：準備臨時承載板，例如雙面覆銅板DTF10，並在DTF10的至少一側上施加第一光刻膠層1012，曝光顯影形成第一特徵圖案-步驟(a)，如圖6(a)所示。DTF10包括PP(半固化片)層1011a，PP層1011a往外依次是位於PP層1011a表面的第一銅層1011b、位於第一銅層1011b表面的第二銅層1011c以及位於第二銅層1011c表面的保護層1011d；第一銅層1011b和第二銅層1011c為銅箔物理壓合而成，第一銅層1011b和第二銅層1011c可以物理分離，便於後續工序移除DTF10；保護層1011d可以包括銅、鈦、鎳、鎢或它們的組合；第一銅層1011b、第二銅層1011c和保護層1011d的厚度可以根據實際需要調節，優選地，第一銅層1011b的厚度為18μm、第二銅層1011c的厚度為3μm、保護層1011d的厚度為3~10μm。通常，可以在DTF10的兩側同時施加第一光刻膠層1012並曝光顯影形成第一特 徵圖案，本實施方案中後續僅對DTF10單側的單個單元進行演示，但是並不限定僅能在DTF10的一側進行後續操作。
接著，在圖案中電鍍銅形成第一佈線層1013，去除第一光刻膠層1012，層壓介電材料，並減薄介電材料以暴露第一佈線層1013的表面，形成第一介電層101-步驟(b)，如圖6(b)所示。通常，為了保證填充效果，基於填充量計算介電材料的用量，優選地，介電材料高於第一佈線層1013的表面5~20μm；介電材料可以包括有機介電材料、無機介電材料或它們的組合，優選，介電材料包括聚醯亞胺、環氧樹脂、雙馬來醯亞胺三嗪樹脂、陶瓷填料、玻璃纖維或它們的組合。按照功能性要求進行劃分，介電材料可以選自感光型材料和非感光型材料，優選地，介電材料採用感光型介電材料。可以通過磨板或等離子蝕刻的方式整體減薄介電材料，還可以通過鐳射或鑽孔的方式局部減薄介電材料；當介電材料採用感光型材料時，還可以通過曝光顯影的方式局部減薄介電材料。
然後，在第一介電層101的第一表面上形成金屬種子層1020，在金屬種子層1020上施加第二光刻膠層1021，曝光顯影形成第二特徵圖案，在圖案中電鍍形成蝕刻防護層1022-步驟(c)，如圖6(c)所示。通常，蝕刻防護層1022可以包括鎳、鈦或它們的組合，例如，8-15μm的鎳層。通常，可以通過化學鍍或者濺射的方式在第一介電層101上形成金屬種子層1020，金屬種子層1020可以包括鈦、銅、鈦鎢合金或它們的組合，金屬種子層1020的厚度範圍為0.8-5μm；優選地，濺射0.1μm鈦和1μm銅製作金屬種子層1020。
接著，施加第三光刻膠層1023，曝光顯影形成第三特徵圖 案，圖案中電鍍銅形成第一銅柱層1024及犧牲銅柱1025一步驟(d)，如圖6(d)所示。通常，第一銅柱層1024形成後可以對第一銅柱層1024表面進行棕化處理，增加第一銅柱層1024與其外包覆的介電層的結合力；第一銅柱層1024的形狀可以根據實際需要設定，例如，可以為方形、圓形等，具體不做限定。犧牲銅柱1025的厚度可以根據器件的厚度進行調整。第一銅柱層1024上下尺寸均勻，對於嵌埋封裝結構的散熱以及信號傳輸穩定更具優勢。犧牲銅柱1025位於蝕刻防護層1022的表面上，便於後續對犧牲銅柱1025進行蝕刻時，蝕刻防護層1022能夠保護第一佈線層1013免於蝕刻。
然後，去除第二光刻膠層1021和第三光刻膠層1023，層壓介電材料，並減薄介電材料以暴露第一銅柱層1024和犧牲銅柱1025，形成第二介電層102-步驟(e)，如圖6(e)所示。
接著，在第二介電層102上形成第二佈線層1032-步驟(f)，如圖6(f)所示。通常，包括以下步驟：
在第二介電層102上形成金屬種子層1031；
在金屬種子層1031上施加第四光刻膠層1034，曝光顯影形成第四特徵圖案；
在圖案中電鍍銅形成第二佈線層1032。
通常，可以通過化學鍍或者濺射的方式在第二介電層102上形成金屬種子層1031，金屬種子層1031可以包括鈦、銅、鈦鎢合金或它們的組合，金屬種子層1031的厚度範圍為0.8-5μm；優選地，濺射0.1μm鈦和1μm銅製作金屬種子層1031。
然後，在第二佈線層1032上形成第二銅柱層1033-步驟 (g)，如圖6(g)所示。通常，包括以下步驟：
施加第五光刻膠層，曝光顯影形成第五特徵圖案；
在圖案中電鍍銅形成第二銅柱層1033；
去除第四光刻膠層1034及第五光刻膠層，並蝕刻暴露的金屬種子層1031。
通常，第二銅柱層1033的形狀可以根據實際需要設定，例如，可以為方形、圓形等，具體不做限定；第二銅柱層1033上下尺寸均勻，對於嵌埋封裝結構的散熱以及信號傳輸穩定更具優勢。電鍍形成第二銅柱層1033後還可以對第二銅柱層1033表面進行棕化處理，增加第二銅柱層1033與其外包覆的介電層的結合力。
接著，施加第六光刻膠層1036，曝光顯影形成第六特徵圖案，蝕刻犧牲銅柱1025及蝕刻防護層1022，形成器件放置口框1026-步驟(h)，如圖6(h)所示。通常，可以在第二銅柱層1033和第二佈線層1032上施加第六光刻膠層1036，以保護第二銅柱層1033和第二佈線層1032在後續蝕刻犧牲銅柱1025時不被蝕刻；將第六光刻膠層1036曝光顯影後露出犧牲銅柱1025，蝕刻犧牲銅柱1025及蝕刻防護層1022。
然後，整板施加第七光刻膠層並曝光固化，分離第一銅層1011b和第二銅層1011c，並蝕刻第二銅層1011c和保護層1011d，移除第六光刻膠層1036和第七光刻膠層，形成基板-步驟(i)，如圖6(i)所示。施加第七光刻膠層是為了在移除DTF10過程中保護基板。本發明可以僅提供設置有佈線層和銅柱層的基板，後續由封裝廠商進一步貼裝器件，然後封裝即可，為後續封裝廠商省去圖形電鍍等制程設備投入。
接著，承接步驟(i)，在器件放置口框1026的底部貼裝第一器件1051，在第二佈線層1032的表面貼裝第二器件1052，在第二銅柱層1033的端部貼裝第三器件1053-步驟(j)，如圖6(j)所示。通常，各器件具有相對應的兩個端子面，或者具有單側端子面以及與該單側端子面相對應的非端子面，器件可以通過焊料實現端子與基板電信號相連。以具有單側端子面的器件為例進行後續工序說明，貼裝器件時，一種情況下可以通過在器件放置口框1026的底部、第二佈線層1032的表面以及第二銅柱層1033的端部以印刷或點錫的方式施加焊料，然後貼裝器件後經回流焊接；一種情況下，可以在第一器件1051、第二器件1052以及第三器件1053的端子表面沾貼焊料後，分別貼裝至器件放置口框1026的底部、第二佈線層1032的表面以及第二銅柱層1033的端部，經回流焊接。焊料可以包括錫膏和銀漿。線上路佈置後植入器件，可以根據基板的良率進行選擇性植入，減少器件的損耗；並且器件通過背靠背堆疊的方式植入，增加I/O數，減少將器件水準排布時的面積占比。
然後，填充介電材料以填充第一器件1051與器件放置口框1026之間的間隙-步驟(k)，如圖6(k)所示。通常，可以從貼裝器件的方向向下填充介電材料，優選地，介電材料選自有機介電材料或感光介電材料，例如，有機介電材料可以為ABF或PP，感光介電材料可以為PID。
接著，在第一介電層101的第二表面上施加阻焊層106，並對暴露的金屬進行金屬表面處理形成阻焊開窗1061-步驟(l)，如圖6(l)所示。通常，可以通過化學鎳鈀金或OPS等進行金屬表面處理。如果第一器件1051和第二器件1052具有雙側端子，則嵌埋封裝結構如圖3所示，第一器件 1051的部分端子和第二器件1052的部分端子焊接，第二器件1052的部分端子與第三器件1053的部分端子焊接。
然後，承接步驟(i)，在器件放置口框1026的底部貼裝第一器件1051，在第二佈線層1032的表面貼裝第二器件1052-步驟(m)，如圖6(m)所示。
接著，層壓介電材料覆蓋第二佈線層1032、第二銅柱層1033及第二器件1052，減薄介電材料暴露第二銅柱層1033的端部，形成第三介電層103-步驟(n)，如圖6(n)所示。通常，可以從貼裝器件的方向向下層壓介電材料，為保證填充效果，介電材料一般至少高於第二銅柱層1033的端部5μm；優選，介電材料選自有機介電材料或感光介電材料，例如，有機介電材料可以為ABF或PP，感光介電材料可以為PID。
然後，在第二銅柱層1033的端部貼裝第三器件1053，採用介電材料塑封第三器件1053，形成第四介電層104-步驟(o)，如圖6(o)所示。
最後，在第一介電層101的第二表面上施加阻焊層106，並對暴露的金屬進行金屬表面處理形成阻焊開窗1061-步驟(p)，如圖6(p)所示。如果第一器件1051和第二器件1052具有雙側端子，則嵌埋封裝結構如圖5所示，第一器件1051的部分端子和第二器件1052的部分端子焊接，第二器件1052的部分端子與第三器件1053的部分端子焊接。
本領域具通常知識者將會認識到，本發明不限於上下文中具體圖示和描述的內容。而且，本發明的範圍由所附申請專利範圍限定，包括上文所述的各個技術特徵的組合和子組合以及其變化和改進，本領域具 通常知識者在閱讀前述說明後將會預見到這樣的組合、變化和改進。
在申請專利範圍中，術語“包括”及其變體例如“包含”、“含有”等是指所列舉的組件被包括在內，但一般不排除其他組件。
100:封裝結構
101:第一介電層
102:第二介電層
1013:第一佈線層
1024:第一銅柱層
1026:器件放置口框
1032:第二佈線層
1033:第二銅柱層
1051:第一器件
1052:第二器件
1053:第三器件
106:阻焊層
1061:阻焊開窗

Claims (14)

  1. 一種多層嵌埋封裝結構的製造方法，包括如下步驟：(a)在臨時承載板上形成第一佈線層，在所述第一佈線層上層壓第一介電層，減薄所述第一介電層以暴露出上述第一佈線層；(b)在所述第一介電層上形成第一銅柱層，所述第一銅柱層包括犧牲銅柱，在所述第一銅柱層上層壓第二介電層，減薄所述第二介電層以暴露出所述第一銅柱層；(c)在所述第二介電層上形成第二佈線層，使得所述第一佈線層和所述第二佈線層通過所述第一銅柱層導通連接；(d)在所述第二佈線層上形成第二銅柱層；(e)蝕刻所述犧牲銅柱，形成暴露出所述第一佈線層的器件放置口框；(f)移除所述臨時承載板。
  2. 如請求項1所述的製造方法，還包括：(g)在所述器件放置口框的底部貼裝第一器件，使得第一器件的端子與第一佈線層導通連接；(h)在所述第二佈線層上貼裝第二器件，使得所述第二器件的端子與所述第二佈線層導通連接；(i)在所述第二銅柱層的端部貼裝第三器件，使得所述第三器件的端子與所述第二銅柱層導通連接。
  3. 如請求項2所述的製造方法，還包括：(h')在步驟h之後和步驟i之前，填充介電材料覆蓋所述第一器件和所述第二器件。
  4. 如請求項2所述的製造方法，還包括：(i')在步驟i之後，層壓介電材料形成覆蓋所述第三器件的塑封層。
  5. 如請求項1所述的製造方法，其中步驟(a)包括：(a1)在所述臨時承載板上施加第一光刻膠層，曝光顯影形成第一特徵圖案；(a2)在所述第一特徵圖案中電鍍形成第一佈線層，並移除所述第一光刻膠層；(a3)在所述第一佈線層上層壓第一介電層，並減薄所述第一介電層以暴露所述第一佈線層。
  6. 如請求項1所述的製造方法，其中所述臨時承載板包括雙面覆銅板，其中所述雙面覆銅板包括半固化片、在所述半固化片表面上的第一銅層和在所述第一銅層上的第二銅層，其中所述第一銅層和所述第二銅層通過物理壓合附著在一起。
  7. 如請求項1所述的製造方法，其中步驟(b)包括：(b1)在所述第一介電層上形成金屬種子層；(b2)在所述第一介電層的金屬種子層上施加第二光刻膠層，曝光顯影形成第二特徵圖案；(b3)在所述第二特徵圖案中電鍍形成蝕刻防護層；(b4)施加第三光刻膠層，曝光顯影形成第三特徵圖案；(b5)在所述第三特徵圖案中電鍍形成第一銅柱層和在所述蝕刻防護層上的犧牲銅柱，並去除所述第二光刻膠層和所述第三光刻膠層；(b6)在所述第一特徵層和所述犧牲銅柱上層壓第二介電層，並減薄所述第二介電層以暴露所述第一特徵層和所述犧牲銅柱。
  8. 如請求項7所述的製造方法，其中所述蝕刻防護層包括鎳、鈦或它們的組合。
  9. 如請求項1所述的製造方法，其中步驟(c)包括：(c1)在所述第二介電層上形成金屬種子層；(c2)在所述第二介電層的金屬種子層上施加第四光刻膠層，曝光顯影形成第四特徵圖案；(c3)在所述第四特徵圖案中電鍍銅形成第二佈線層，並移除所述第四光刻膠層。
  10. 根據請求項1所述的製造方法，其中步驟(d)包括(d1)在所述第二佈線層上施加第五光刻膠層，曝光顯影形成第五特徵圖案；(d2)在所述第五特徵圖案中電鍍銅形成第二銅柱層；(d3)移除所述第五光刻膠層，並蝕刻暴露的所述金屬種子層。
  11. 如請求項7或9所述的製造方法，其中所述金屬種子層包括鈦、銅、鈦鎢合金或它們的組合。
  12. 如請求項1所述的製造方法，其中步驟(d)包括(d1)在所述第二佈線層上施加第六光刻膠層，曝光顯影形成第六特徵圖案；(d2)在所述第六特徵圖案中蝕刻所述犧牲銅柱及所述蝕刻防護層，形成器件放置口框。
  13. 如請求項6所述的製造方法，其中步驟(e)包括通過將所述第一銅層和所述第二銅層物理分離，並蝕刻所述第二銅層，以移除所述雙面覆銅板。
  14. 如請求項1所述的製造方法，還包括在步驟f移除所述臨時承載板之後，在所述第一介電層的底面上施加阻焊層，並對暴露的金屬進行表面處理形成阻焊開窗。
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