TW201842644A - 半導體元件及其製造方法 - Google Patents

半導體元件及其製造方法 Download PDF

Info

Publication number
TW201842644A
TW201842644A TW107102420A TW107102420A TW201842644A TW 201842644 A TW201842644 A TW 201842644A TW 107102420 A TW107102420 A TW 107102420A TW 107102420 A TW107102420 A TW 107102420A TW 201842644 A TW201842644 A TW 201842644A
Authority
TW
Taiwan
Prior art keywords
trench
insulating layer
top surface
semiconductor element
substrate
Prior art date
Application number
TW107102420A
Other languages
English (en)
Other versions
TWI746776B (zh
Inventor
李燦浩
鄭顯秀
柳翰成
李仁榮
Original Assignee
南韓商三星電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南韓商三星電子股份有限公司 filed Critical 南韓商三星電子股份有限公司
Publication of TW201842644A publication Critical patent/TW201842644A/zh
Application granted granted Critical
Publication of TWI746776B publication Critical patent/TWI746776B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/073—Apertured devices mounted on one or more rods passed through the apertures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02333—Structure of the redistribution layers being a bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03602—Mechanical treatment, e.g. polishing, grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03616—Chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03901—Methods of manufacturing bonding areas involving a specific sequence of method steps with repetition of the same manufacturing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/05576—Plural external layers being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一種半導體元件，所述半導體元件包括：基底；絕緣層，位於所述基底上且包括溝槽；至少一個通孔結構，穿透所述基底且突出在所述溝槽的底表面上方；以及導電結構，在所述溝槽中環繞所述至少一個通孔結構。

Description

半導體裝置與其製造方法
本美國非臨時專利申請基於35 U.S.C.§119主張在2017年4月28日在韓國智慧財產局提出申請的韓國專利申請第10-2017-0055493號的優先權，所述韓國專利申請的公開內容全文併入本申請供參考。
本發明概念的實施例涉及半導體元件及/或製造所述半導體元件的方法，且更具體來說，涉及包括通孔結構（via structure）及焊盤結構的半導體元件及/或製造所述半導體元件的方法。
已開發出對半導體元件進行堆疊的技術來改善半導體產品的積集密度及性能。舉例來說，在多晶片封裝技術中，可在一個半導體封裝中安裝多個晶片（或半導體元件）。另外，在系統級封裝（system-in package）技術中，可在一個半導體封裝中堆疊不同種類的晶片（或半導體元件），且所述不同種類的晶片（或半導體元件）作為一個系統運行。當對半導體元件進行堆疊時，可能需要一種用於提高堆疊半導體元件的驅動速度的方法。半導體元件可通過導電通孔電連接到另一個半導體元件或印刷電路板。導電通孔可提高電信號的傳送速率。隨著半導體元件已被高度積集，需要可靠的導電通孔。
本發明概念的一些示例性實施例可提供可靠性得到提高的半導體元件及/或製造所述半導體元件的方法。
本發明概念的一些示例性實施例還可提供能夠提高良率的製造半導體元件的方法。
根據本發明概念的示例性實施例，一種半導體元件包括：基底；絕緣層，位於所述基底上，所述絕緣層包括溝槽；至少一個通孔結構，穿透所述基底且突出在所述溝槽的底表面上方；以及導電結構，在所述溝槽中環繞所述至少一個通孔結構。
根據本發明概念的示例性實施例，一種半導體元件包括：基底；絕緣層，位於所述基底上，所述絕緣層界定溝槽，所述絕緣層具有位於所述溝槽之外的第一頂表面、位於所述溝槽的底部處的第二頂表面及連接所述第一頂表面與所述第二頂表面的第三頂表面，所述溝槽從所述絕緣層的所述第一頂表面延伸到在垂直方向上位於所述絕緣層的所述第一頂表面與所述絕緣層的底表面之間的點；至少一個導電通孔結構，穿透所述基底且突出在所述溝槽的所述底表面上方；以及至少一個導電結構，在所述溝槽中環繞所述至少一個導電通孔結構。
根據本發明概念的示例性實施例，一種半導體元件當在平面圖中觀察時包括：第一金屬結構，包含第一金屬材料；阻擋金屬圖案，環繞所述第一金屬結構；以及導電結構，環繞所述阻擋金屬圖案，所述導電結構包含第二金屬材料；以及絕緣層，環繞所述導電結構。
根據本發明概念的示例性實施例，一種製造半導體元件的方法包括：形成通孔結構，所述通孔結構朝基底的第二表面穿透過所述基底的第一表面，所述第二表面與所述第一表面相對；在所述基底的所述第二表面處薄化所述基底，使得所述通孔結構突出在所述基底的經調整的第二表面上方；在所述基底的經調整的所述第二表面上形成絕緣層；在所述絕緣層中形成溝槽，以環繞所述通孔結構的突出部分；在所述基底的經調整的所述第二表面上及所述溝槽之上提供導電層；將所述導電層、所述通孔結構及所述絕緣層平坦化，使得所述導電層的頂表面、所述通孔結構的頂表面及所述絕緣層的頂表面共面，且所述導電層環繞所述通孔結構以形成導電結構；以及提供利用所述導電結構的半導體元件。
在下文中將詳細闡述根據本發明概念一些示例性實施例的半導體元件。
圖1是示出根據本發明概念示例性實施例的半導體元件的剖視圖。
參照圖1，半導體元件10可包括基底100、通孔結構200及焊盤結構300。半導體元件10可為包括記憶體晶片、邏輯晶片或其組合的半導體晶片。基底100可為晶圓級基底或晶片級基底。舉例來說，基底100可包含半導體材料，例如矽、鍺或矽鍺（silicon-germanium）。基底100可具有彼此相對的第一表面100a與第二表面100b。基底100的第二表面100b可實質上平行於基底100的第一表面100a。基底100的第一表面100a可為背側表面。在基底100的第一表面100a上可設置有絕緣層120。焊盤結構300可設置在絕緣層120中。基底100的第二表面100b可為前側表面。在基底100的第二表面100b上可設置有電路層110。在電路層110的底表面上可設置有連接端子400。連接端子400可包括焊料球、凸塊、柱或其任意組合。連接端子400可包含導電材料。舉例來說，連接端子400可包含錫（Sn）、鉛（Pb）、銀（Ag）或其任意合金中的至少一種。
通孔結構200可穿過基底100、絕緣層120及焊盤結構300設置。通孔結構200可電連接到焊盤結構300。通孔結構200可電連接到連接端子400中的至少一者。在本公開中，應理解，當稱一元件「電連接到」另一個元件時，所述元件可直接連接到另一元件，或者可存在一個或多個中間元件。電信號可通過連接端子400及通孔結構200從外部系統傳送到半導體元件10及/或可通過通孔結構200及連接端子400從半導體元件10傳送到外部系統。在本公開中，應理解，當稱一元件、元件或系統電連接到半導體元件時，所述元件、元件或系統可電連接到半導體元件的電晶體中的至少一者。絕緣層120、通孔結構200及焊盤結構300可在半導體元件10的頂表面處被暴露出。
圖2A是示出根據本發明概念示例性實施例的半導體元件的平面圖。圖2B是沿圖2A所示線IIB'-IIB''截取的剖視圖。另外，圖2B對應於圖1所示區IIB的放大圖。圖2C是圖2B所示區IIC的放大圖。在下文中，為容易且方便地進行解釋，將省略或僅簡要提及對與以上示例性實施例中的元件相同的元件的說明。
參照圖1、圖2A、圖2B、及圖2C，半導體元件10可包括基底100、電路層110、絕緣層120、通孔結構200及焊盤結構300。在基底100的第二表面100b上可設置有電路層110。電路層110可包括絕緣圖案111及112、電晶體115及內連線結構116。電晶體115可形成在基底100的第二表面100b上。第一絕緣圖案111可設置在基底100的第二表面100b上且可覆蓋電晶體115。第二絕緣圖案112可設置在第一絕緣圖案111上。舉例來說，絕緣圖案111及112可包含氧化矽、氮化矽或氮氧化矽中的至少一種。內連線結構116可包括接觸塞117、內連線圖案118及內連線通孔119。內連線結構116可包含導電材料（例如，銅或鎢）。接觸塞117可穿透第一絕緣圖案111以連接到電晶體115。內連線圖案118可設置在絕緣圖案111與絕緣圖案112之間。內連線通孔119可穿透第二絕緣圖案112中的至少一者以連接到內連線圖案118。在電路層110的底表面上可設置有連接端子400。電晶體115中的至少一者可通過內連線結構116電連接到連接端子400中的至少一者。在電路層110的底表面上可設置有保護層113。保護層113可不覆蓋連接端子400。保護層113可包含絕緣材料（例如，聚合物）。
在基底100的第一表面100a上可設置有絕緣層120。絕緣層120可具有溝槽125。溝槽125可從絕緣層120的頂表面120a朝絕緣層120的底表面延伸。溝槽125可在溝槽125的頂表面處具有第一寬度且在溝槽125的底表面處具有第二寬度，使得第一寬度大於第二寬度。絕緣層120可包括有機絕緣層。舉例來說，絕緣層120可包含聚合物。聚合物可包括感光性聚合物。聚合物可包括熱固性聚合物（thermosetting polymer）。聚合物可包括感光性聚醯亞胺（photosensitive polyimide，PSPI）、聚苯並惡唑（polybenzoxazole，PBO）或苯並環丁烯（benzocyclobutene，BCB）系聚合物中的至少一者。絕緣層120可包含有機材料，且因此可相對柔軟。舉例來說，絕緣層120可比基底100、焊盤結構300或通孔結構200中的至少一者柔軟。絕緣層120可緩衝或減小對焊盤結構300及通孔結構200施加的應力。在製造半導體元件10的製程中，基底100可能發生翹曲（warpage）。絕緣層120的熱膨脹係數（thermal expansion coefficient）可不同於基底100的熱膨脹係數。舉例來說，絕緣層120的熱膨脹係數可大於基底100的熱膨脹係數。通過對絕緣層120的厚度進行調整，可減小或防止基底100的翹曲。在下文中，將詳細闡述通孔結構200及焊盤結構300。
通孔結構200可穿透基底100、絕緣層120及焊盤結構300。通孔結構200可從基底100的第一表面100a突出。通孔結構200的側壁200c的上部部分可被焊盤結構300環繞。通孔結構200的側壁200c的下部部分可設置在基底100中。通孔結構200還可穿透第一絕緣圖案111。通孔結構200可通過內連線結構116電連接到電晶體115中的至少一者。另外，通孔結構200還可通過內連線結構116電連接到連接端子400中的至少一者。
在通孔結構200與基底100之間以及在通孔結構200與絕緣層120之間可夾置有襯墊層205。襯墊層205可不在通孔結構200與焊盤結構300之間延伸。舉例來說，襯墊層205可包含絕緣材料。絕緣材料可包含基於矽的絕緣材料。
通孔結構200可包括阻擋圖案210、晶種圖案220及導電通孔230。阻擋圖案210可設置在襯墊層205上。阻擋圖案210可沿通孔結構200的側壁200c設置。舉例來說，阻擋圖案210可形成通孔結構200的側壁200c。阻擋圖案210可包含鈦（Ti）、氮化鈦（TiN）、鉭（Ta）或氮化鉭（TaN）中的至少一種。晶種圖案220可沿阻擋圖案210延伸。晶種圖案220可包含金屬。導電通孔230可設置在晶種圖案220上。舉例來說，導電通孔230可具有柱形狀，且晶種圖案220可設置在阻擋圖案210與導電通孔230的側壁之間。阻擋圖案210可設置在晶種圖案220與襯墊層205之間。導電通孔230可包含金屬（例如，銅（Cu）或鎢（W））。阻擋圖案210、晶種圖案220及導電通孔230可在絕緣層120的頂表面120a處暴露出。
焊盤結構300可設置在基底100的第一表面100a上。如圖2A所示，當在平面圖中觀察時，焊盤結構300可環繞通孔結構200。焊盤結構300的平面形狀可並非僅限於圖2A所示四邊形形狀，而是可作出各種修改。通孔結構200可穿透焊盤結構300。焊盤結構300可覆蓋通孔結構200的側壁200c的至少一部分。焊盤結構300可電連接到通孔結構200。焊盤結構300可暴露出通孔結構200。舉例來說，焊盤結構300可暴露出通孔結構200的頂表面200a。焊盤結構300的頂表面300a可與通孔結構200的頂表面200a實質上共面。舉例來說，焊盤結構300的頂表面300a可與通孔結構200的頂表面200a設置在相同的水平高度或實質上相似的水平高度處。在本公開中，用語「相同的水平高度」及「共面」可將在製程進行期間可能出現的容差範圍考慮在內。
焊盤結構300可設置在絕緣層120中。舉例來說，焊盤結構300可設置在絕緣層120的溝槽125中。舉例來說，焊盤結構300可嵌置在絕緣層120中。焊盤結構300的頂表面300a可與絕緣層120的頂表面120a實質上共面。舉例來說，焊盤結構300的頂表面300a可與絕緣層120的頂表面120a設置在相同的水平高度或實質上相似的水平高度處。焊盤結構300的底表面300b可設置在絕緣層120中。絕緣層120可接觸焊盤結構300的側壁300c以及焊盤結構300的底表面300b。因此，焊盤結構300與絕緣層120之間的接觸面積可增大，從而提高焊盤結構300與絕緣層120之間的黏合強度。因此，可減少或防止焊盤結構300從絕緣層120分離的現象，從而提高半導體元件10的可靠性。
焊盤結構300的底表面300b與側壁300c之間的角度θ1可為鈍角。因此，焊盤結構300與絕緣層120之間的接觸面積可進一步增大。如果焊盤結構300的底表面300b與側壁300c之間的角度θ1等於或小於90度，則應力可能集中在焊盤結構300的邊緣或隅角中。此處，焊盤結構300的邊緣或隅角是指焊盤結構300的底表面300b與焊盤結構300的側壁300c交會的區。應力可包括物理應力及/或由焊盤結構300的熱膨脹係數與絕緣層120的熱膨脹係數之差造成的應力。焊盤結構300或絕緣層120中的至少一者可能被應力損壞。舉例來說，在焊盤結構300或絕緣層120中的至少一者中可能出現裂紋。然而，根據本發明概念的一些示例性實施例，焊盤結構300的底表面300b與側壁300c之間的角度θ1可大於90度。因此，應力可不集中在焊盤結構300的邊緣或隅角中。因此，半導體元件10的可靠性可得到提高。如果焊盤結構300的底表面300b與側壁300c之間的角度θ1大於120度，則可能難以形成焊盤結構300。根據本發明概念的一些示例性實施例，焊盤結構300的底表面300b與側壁300c之間的角度θ1可等於或小於120度。舉例來說，焊盤結構300的底表面300b與側壁300c之間的角度θ1可大於90度且等於或小於120度。
焊盤結構300可包括晶種焊盤310及導電焊盤320。如圖2C所示，晶種焊盤310可沿溝槽125的底表面125b及側壁125c以及通孔結構200的側壁200c的上部部分延伸。晶種焊盤310可接觸通孔結構200（例如，阻擋圖案210）。導電焊盤320可設置在晶種焊盤310上。導電焊盤320可填充溝槽125。導電焊盤320可包含金屬（例如，銅或鋁）。晶種焊盤310的最頂部表面及導電焊盤320的頂表面可在絕緣層120的頂表面120a處暴露出。
圖2D是根據本發明概念另一個示例性實施例的沿圖2A所示線IIB'-IIB''截取的剖視圖。另外，圖2D是與圖1所示區IIB對應的放大圖。在下文中，為容易且方便地進行解釋，將省略或僅簡要提及對與以上示例性實施例中的元件相同的元件的說明。
參照圖1、圖2A、及圖2D，半導體元件10A可包括基底100、電路層110、絕緣層120、通孔結構200及焊盤結構300。圖2D所示基底100、電路層110、絕緣層120及焊盤結構300可與以上參照圖2B所闡述的基底100、電路層110、絕緣層120及焊盤結構300相同或實質上相似。圖2D所示通孔結構200可與參照圖2B闡述的通孔結構200相同或實質上相似。舉例來說，通孔結構200可穿透基底100、絕緣層120及焊盤結構300。然而，根據本示例性實施例的通孔結構200可不設置在電路層110的第一絕緣圖案111中，此不同於圖2B。
圖3A是示出根據本發明概念示例性實施例的半導體元件的平面圖。圖3B是沿圖3A所示線IIIB-IIIB'截取的剖視圖。另外，圖3B對應於圖1所示區IIIB的放大圖。在下文中，為容易且方便地進行解釋，將省略或僅簡要提及對與以上示例性實施例中的元件相同的元件的說明。
參照圖1、圖3A、及圖3B，半導體元件10B可包括基底100、電路層110、絕緣層120、通孔結構201及202以及焊盤結構300。圖3B所示基底100、電路層110、絕緣層120及焊盤結構300可與參照圖2B所闡述的基底100、電路層110、絕緣層120及焊盤結構300相同或實質上相似。通孔結構201及202可包括多個通孔結構201及202，且焊盤結構300可包括分別對應於通孔結構201及202的多個焊盤結構300。通孔結構201及202中的每一者可穿透基底100、絕緣層120、焊盤結構300中的每一者及電路層110的第一絕緣圖案111。在一些示例性實施例中，如同圖2D所示通孔結構200一樣，通孔結構201及202可不設置在電路層110的第一絕緣圖案111中。
通孔結構201及202可包括彼此間隔開的第一通孔結構201與第二通孔結構202。第一通孔結構201可與參照圖1至圖2A至圖2C闡述的通孔結構200相同或實質上相似。第一通孔結構201可用作連接通孔。舉例來說，第一通孔結構201可電連接到電晶體115中的至少一者及/或連接端子400中的至少一者。第一通孔結構201可包括第一阻擋圖案211、第一晶種圖案221及第一導電通孔231。第二通孔結構202可包括第二阻擋圖案212、第二晶種圖案222及第二導電通孔232。第一阻擋圖案211及第二阻擋圖案212可與圖1及圖2A至圖2C所示阻擋圖案210相同或實質上相似，第一晶種圖案221及第二晶種圖案222可與圖1及圖2A至圖2C所示晶種圖案220相同或實質上相似，且第一導電通孔231及第二導電通孔232可與圖1及圖2A至圖2C所示導電通孔230相同或實質上相似。然而，第二通孔結構202的形狀可不同於第一通孔結構201的形狀。舉例來說，如圖3A所示，第二通孔結構202的平面形狀可不同於第一通孔結構201的平面形狀。第二通孔結構202可用作對準鍵（alignment key）。因此，可不在基底100的第一表面100a上或者絕緣層120的頂表面120a上形成額外對準鍵。如圖3B所示，第二通孔結構202可與電晶體115絕緣。在一些示例性實施例中，第二通孔結構202可通過內連線結構116電連接到電晶體115中的至少一者。在這種情形中，第二通孔結構202可用作對準鍵與電連接通孔二者。
焊盤結構300中的每一者可設置在形成於絕緣層120中的溝槽125中的每一者中。溝槽125可在溝槽125的頂表面處具有第一寬度且在溝槽125的底表面處具有第二寬度，使得第一寬度大於第二寬度。焊盤結構300中的每一者可包括晶種焊盤310及導電焊盤320。焊盤結構300中的一個焊盤結構300可覆蓋第一通孔結構201的側壁且可電連接到第一通孔結構201。焊盤結構300中的另一個焊盤結構300可覆蓋第二通孔結構202的側壁且可電連接到第二通孔結構202。焊盤結構300可不覆蓋第一通孔結構201的頂表面201a及第二通孔結構202的頂表面202a。
在下文中將闡述根據本發明概念一些實施例的製造半導體元件的方法。
圖4A至圖4G是示出根據本發明概念示例性實施例的製造半導體元件的方法的剖視圖。在下文中，為容易且方便地進行解釋，將省略或僅簡要提及對與以上示例性實施例中的技術特徵相同的技術特徵的說明。另外，為容易且方便地進行解釋，將闡述單個焊盤結構及單個連接端子。
參照圖4A，可在基底100的第二表面100b上形成電路層110，且可在基底100中形成通孔結構200。在一些實施例中，可在基底100的第二表面100b上形成電晶體115。可在基底100的第二表面100b上形成第一絕緣圖案111以覆蓋電晶體115。
可在基底100及第一絕緣圖案111中形成通孔孔洞250。通孔孔洞250可通過使用蝕刻製程的圖案化製程形成。可在通孔孔洞250的側壁及底表面上共形地形成襯墊層205。舉例來說，襯墊層205可包含氧化矽、氮化矽、或氮氧化矽中的至少一種。可在通孔孔洞250中形成通孔結構200。通孔結構200可包括阻擋圖案210、晶種圖案220及導電通孔230。通孔結構200可通過中段通孔製程（via-middle process）形成。舉例來說，可在形成電晶體115之後形成通孔孔洞250及通孔結構200，如圖4A所示。在一些示例性實施例中，通孔結構200可通過先通孔製程（via-first process）形成。舉例來說，通孔孔洞250及通孔結構200可在形成電晶體115及第一絕緣圖案111之前形成。在這種情形中，如同圖2D所示通孔結構200一樣，通孔結構200可不穿透第一絕緣圖案111。
可在襯墊層205上形成阻擋圖案210。形成通孔結構200可包括在阻擋圖案210上形成晶種圖案220以及使用晶種圖案220作為電極來執行電鍍製程。在電鍍製程期間，可通過使用導電材料填充通孔孔洞250來形成導電通孔230。在形成導電通孔230的製程中，可能難以使用導電材料完全填充通孔孔洞250。因此，在導電通孔230的端部部分290中可能形成缺陷295（例如，空隙）。此處，導電通孔230的端部部分290可朝向基底100的第一表面100a。舉例來說，導電通孔230的端部部分290可鄰近於通孔孔洞250的底表面。例如空氣等氣體可能佔據缺陷295。在一些示例性實施例中，在製造製程中使用的化學材料的殘留物可能餘留在缺陷295中。
可在第一絕緣圖案111上形成第二絕緣圖案112，且可在第一絕緣圖案111及第二絕緣圖案112中形成內連線結構116。由此，可形成電路層110。可在電路層110的底表面上形成連接端子400及保護層113。
參照圖4B，可對基底100的第一表面100a執行薄化製程。薄化製程可通過使用蝕刻劑或漿料（slurry）的回蝕製程（etch-back process）來執行。薄化製程可對基底100選擇性地執行。在薄化製程中可不移除襯墊層205及通孔結構200。通孔結構200的端部部分290可從經薄化的基底100的第一表面100a突出。
參照圖4C，可在經薄化的基底100的第一表面100a上形成絕緣層120。絕緣層120可通過使用例如感光性聚合物塗佈經薄化的基底100的第一表面100a來形成。絕緣層120可包含參照圖2A至圖2C闡述的材料。
參照圖4D，可將絕緣層120圖案化以形成初步溝槽126。初步溝槽126可通過使用罩幕圖案（圖中未示出）的光微影製程形成。可通過初步溝槽126暴露出通孔結構200。通孔結構200的端部部分290可從初步溝槽126突出。初步溝槽126的底表面126b與側壁126c之間的角度θ2可為約90度。
參照圖4E，可將絕緣層120硬化。在將絕緣層120硬化的製程中，可在絕緣層120中形成溝槽125，且使得溝槽125的頂表面處的第一寬度大於溝槽125的底表面處的第二寬度。溝槽125可從絕緣層120的頂表面120a朝絕緣層120的底表面延伸。絕緣層120可通過熱硬化製程被硬化。熱硬化製程可在高於室溫（例如，攝氏25度）的溫度下執行。溝槽125可通過初步溝槽126的熱流動（thermal flow）來形成。舉例來說，絕緣層120的一部分可因硬化製程中的熱而向下流動，且由此可形成溝槽125。溝槽125的底表面125b與側壁125c之間的角度θ1'可不同於初步溝槽126的底表面126b與側壁126c之間的角度θ2。在一些示例性實施例中，溝槽125的底表面125b與側壁125c之間的角度θ1'可大於圖4D所示初步溝槽126的底表面126b與側壁126c之間的角度θ2。溝槽125的底表面125b與側壁125c之間的角度θ1'可大於90度且等於或小於120度。溝槽125的底表面125b與側壁125c之間的角度θ1'可實質上等於圖2C所示焊盤結構300的底表面300b與側壁300c之間的角度θ1。通孔結構200可從溝槽125的底表面125b突出。通孔結構200的頂表面200a可設置在比溝槽125的底表面125b的水平高度高的水平高度處。
參照圖4F，可移除襯墊層205的一部分以暴露出通孔結構200的側壁200c的上部部分及通孔結構200的頂表面200a。舉例來說，可暴露出通孔結構200的端部部分290。襯墊層205的所述一部分可通過回蝕製程移除。通孔結構200及絕緣層120可相對於襯墊層205具有蝕刻選擇性。可移除設置在溝槽125中的襯墊層205。在移除襯墊層205的所述一部分之後，可在通孔結構200與設置在溝槽125下方的絕緣層120之間以及在通孔結構200與基底100之間餘留襯墊層205。
參照圖4G，可在基底100的第一表面100a上依序形成晶種層311及導電層312。晶種層311可通過沉積製程形成。晶種層311可沿絕緣層120的頂表面120a、溝槽125的底表面125b及側壁125c、通孔結構200的側壁200c的上部部分及通孔結構200的頂表面200a延伸。晶種層311可接觸阻擋圖案210。可在晶種層311上形成導電層312。導電層312可通過使用晶種層311作為電極進行電鍍製程來形成。導電層312可填充溝槽125。
再次參照圖4G，可將晶種層311及導電層312平坦化以形成晶種焊盤310及導電焊盤320。晶種焊盤310及導電焊盤320可形成在溝槽125中。因此，可提供包括晶種焊盤310及導電焊盤320的焊盤結構300。所述平坦化製程可使用化學機械研磨（chemical mechanical polishing，CMP）製程執行。可通過平坦化製程移除設置在絕緣層120的頂表面120a上的晶種層311及導電層312。可將絕緣層120與晶種層311及導電層312一同平坦化。絕緣層120的頂表面120a可被暴露出。焊盤結構300可被局限在溝槽125中。焊盤結構300的頂表面300a可與絕緣層120的頂表面120a實質上共面。
可將通孔結構200與晶種層311及導電層312一同平坦化，且因此可移除通孔結構200的一部分。舉例來說，可移除通孔結構200的端部部分290。此時，可將缺陷295與通孔結構200的端部部分290一同移除。因此，通孔結構200的電特性及可靠性可得到提高。在平坦化製程之後，通孔結構200可被焊盤結構300暴露出。平坦化的通孔結構200的頂表面200a可與焊盤結構300的頂表面300a及絕緣層120的頂表面120a實質上共面。由此，可製造出圖2B所示半導體元件10。
圖4H是沿圖2A所示線IIB-IIB’截取的用於解釋根據本發明概念示例性實施例的附加平坦化製程的剖視圖。在下文中，為容易且方便地進行解釋，將省略或僅簡要提及對與以上實施例中的元件相同的元件的說明。
參照圖4G及圖4H，可製備包括電路層110、通孔結構200、絕緣層120、晶種層311及導電層312的基底100。可形成晶種層311及導電層312，如圖4G所示。可將導電層312、晶種層311及絕緣層120平坦化以形成焊盤結構300，如圖4H所示。可通過平坦化製程移除通孔結構200的一部分。在平坦化製程之後，可餘留有通孔結構200的端部部分290的缺陷295而形成殘留缺陷296，如圖4H所示。殘留缺陷296可為平坦化的通孔結構200的頂表面200a的凹陷部分。可對殘留缺陷296進行檢驗。舉例來說，對殘留缺陷的檢驗可通過測量通孔結構200的頂表面200a的平坦度來執行。由於通孔結構200的頂表面200a被暴露出，因此可容易地檢驗殘留缺陷296。當檢測到殘留缺陷296時，可執行附加平坦化製程。
參照圖4H及圖2B，可通過附加平坦化製程將殘留缺陷296從通孔結構200的頂表面200a移除。可重複進行對殘留缺陷296的檢驗及附加平坦化製程。附加平坦化製程可被執行到不再檢測到殘留缺陷296為止，且因此，通孔結構200的頂表面200a實質上為平坦的。因此，通孔結構200的電特性及可靠性可得到提高。此處，用語「實質上平坦的頂表面」可將可在平坦化製程中出現的容差範圍考慮在內。
圖5A是示出根據本發明概念示例性實施例的半導體封裝的剖視圖。圖5B是圖5A所示區B的放大圖。在下文中，為容易且方便地進行解釋，將省略或僅簡要提及對與以上實施例中的元件相同的元件的說明。
參照圖5A及圖5B，半導體封裝1可包括封裝基底1000、第一半導體元件11、第二半導體元件12、第三半導體元件13、第四半導體元件14以及模塑層5000。封裝基底1000可包括印刷電路板（PCB）或再分佈層。在封裝基底1000的底表面上可設置有外部端子1001。第一半導體元件、第二半導體元件12及第三半導體元件13中的每一者可與圖2A至圖2C所示半導體元件10、圖2D所示半導體元件10A或圖3A及圖3B所示半導體元件10B相同。第一半導體元件11、第二半導體元件12及第三半導體元件13可分別包括：第一基底1100、第二基底2100及第三基底3100；第一電路層1110、第二電路層2110及第三電路層3110；第一絕緣層1120、第二絕緣層2120及第三絕緣層3120；第一通孔結構1200、第二通孔結構2200及第三通孔結構3200；以及第一焊盤結構1300、第二焊盤結構2300及第三焊盤結構3300。第四半導體元件14可為最上部半導體元件。第四半導體元件14可包括第四基底4100及第四電路層4110，但可不包括通孔結構及焊盤結構。然而，本發明概念的示例性實施例並非僅限於半導體封裝1中所包括的半導體元件11至半導體元件14的數目。
第一半導體元件11可安裝在封裝基底1000上。第一半導體元件11可通過第一連接端子1400電連接到封裝基底1000。第一半導體元件11可通過封裝基底1000電連接到外部端子1001。在第一半導體元件11與封裝基底1000之間可設置有第一黏合膜1500以密封或覆蓋第一連接端子1400。第一黏合膜1500可包含絕緣材料。第二半導體元件12可安裝在第一半導體元件11上。在第一半導體元件11與第二半導體元件12之間可設置有第二連接端子2400。
第二連接端子2400可為參照圖2A及圖2B、圖2D、圖3A及圖3B或圖4B闡述的連接端子400。舉例來說，第二連接端子2400可設置在第二電路層2110的底表面上。第二連接端子2400可包含錫、鉛、銀或其任意合金中的至少一種。第二半導體元件12可以第二連接端子2400面對第一半導體元件11的方式設置在第一半導體元件11上。在一些示例性實施例中，第一通孔結構1200可包括第一通孔結構1201及第二通孔結構1202。第一通孔結構1201及第二通孔結構1202可分別與參照圖3A及圖3B闡述的第一通孔結構201及第二通孔結構202相同。舉例來說，第二通孔結構1202可用作對準鍵。第二半導體元件12可使用第二通孔結構1202來與第一半導體元件11對準。在這種情形中，可不在第一基底1100上形成額外對準鍵。在一些示例性實施例中，可在第一絕緣層1120或第一基底1100上獨立設置對準鍵（圖中未示出）。在這種情形中，第二半導體元件12可使用對準鍵（圖中未示出）來與第一半導體元件11對準。在這種情形中，可省略第二通孔結構1202。在下文中，將參照圖5B更詳細地闡述第一半導體元件11與第二半導體元件12之間的電連接。
第二連接端子2400可通過第二電路層2110的第二內連線結構2116電連接到第二半導體元件12的第二電晶體2115或第二通孔結構2200中的至少一者。第一焊盤結構1300及第一通孔結構1200可在第一半導體元件11的頂表面處暴露出。第二連接端子2400可通過回焊製程直接接觸第一通孔結構1200及第一焊盤結構1300。第二連接端子2400可通過第一通孔結構1200、第一焊盤結構1300及第一電路層1110的第一內連線結構1116電連接到第一半導體元件11的第一電晶體1115中的至少一者。第二連接端子2400可通過第一通孔結構1200電連接到封裝基底1000。因此，第二半導體元件12可電連接到第一半導體元件11及封裝基底1000。
在第一半導體元件11與第二半導體元件12之間可設置有第二黏合膜2500。第二黏合膜2500可環繞第二連接端子2400。第二黏合膜2500可包含絕緣材料。舉例來說，第二黏合膜2500可包含環氧系聚合物、聚醯亞胺、聚酯、丙烯酸聚合物或聚碸中的至少一種。第二黏合膜2500可不包含導電粒子。如果第一半導體元件11的頂表面不是實質上平坦的，則可能難以通過第二黏合膜2500來密封第二連接端子2400。舉例來說，在第一半導體元件11與第二半導體元件12之間可能形成有空腔（圖中未示出）。在半導體封裝1中可能因空腔而出現缺陷。然而，根據本發明概念的一些示例性實施例，第一半導體元件11的頂表面可為實質上平坦的。舉例來說，第一通孔結構1200的頂表面1200a可設置在與第一焊盤結構1300的頂表面1300a及第一絕緣層1120的頂表面1120a相同的水平高度處或實質上相似的水平高度處。因此，第二黏合膜2500可對第二連接端子2400進行良好的密封。因此，可抑制或防止在第一半導體元件11與第二半導體元件12之間形成空腔。因此，半導體封裝1的良率可得到提高。
第一通孔結構1200及第二通孔結構2200可分別包括第一阻擋圖案1210及第二阻擋圖案2210、第一晶種圖案1220及第二晶種圖案2220以及第一導電通孔1230及第二導電通孔2230。第一焊盤結構1300及第二焊盤結構2300可分別包括第一晶種焊盤1310及第二晶種焊盤2310以及第一導電焊盤1320及第二導電焊盤2320。
如圖5A所示，第二通孔結構2200的頂表面可與第二焊盤結構2300的頂表面以及第二絕緣層2120的頂表面實質上共面。第三連接端子3400可直接接觸第二通孔結構2200及第二焊盤結構2300。在第二絕緣層2120的頂表面上可設置有第三黏合膜3500以密封第三連接端子3400。第三通孔結構3200的頂表面可與第三焊盤結構3300的頂表面以及第三絕緣層3120的頂表面實質上共面。第四連接端子4400可直接接觸第三通孔結構3200及第三焊盤結構3300。在第三絕緣層3120的頂表面上可設置有第四黏合膜4500以密封第四連接端子4400。第三黏合膜3500及第四黏合膜4500中的每一者可包含作為第二黏合膜2500的實例闡述的材料中的至少一種。模塑層5000可設置在封裝基底1000上以覆蓋第一半導體元件11、第二半導體元件12、第三半導體元件13及第四半導體元件14。
根據本發明概念的一些示例性實施例，通孔結構的頂表面及焊盤結構的頂表面可在半導體元件的頂表面處暴露出。連接端子可接觸通孔結構及焊盤結構。通孔結構的頂表面可與焊盤結構的頂表面及絕緣層的頂表面實質上共面。因此，可在絕緣層的頂表面上設置有黏合膜以密封連接端子。
絕緣層可緩衝或減小對焊盤結構施加的應力。焊盤結構可嵌置在絕緣層中以提高焊盤結構與絕緣層之間的黏合強度。可對焊盤結構的底表面與側壁之間的角度進行調整，且因此，應力可不集中在焊盤結構的邊緣或隅角中。因此，半導體元件的可靠性可得到提高。
儘管已參照示例性實施例闡述了本發明概念，然而對所屬領域中的技術人員來說將顯而易見的是，在不背離所公開的示例性實施例的精神及範圍的條件下，可作出各種改變及潤飾。因此，應理解，以上示例性實施例並非限制性的，而是說明性的。因此，本發明概念的範圍應由申請專利範圍及其等效範圍所許可的最廣範圍的解釋來確定，而不應受上述說明約束或限制。
1‧‧‧半導體封裝
10、10A、10B、11、12、13、14‧‧‧半導體元件
100‧‧‧基底
100a‧‧‧第一表面
100b‧‧‧第二表面
110‧‧‧電路層
111、112‧‧‧絕緣圖案
113‧‧‧保護層
115‧‧‧電晶體
116‧‧‧內連線結構
117‧‧‧接觸塞
118‧‧‧內連線圖案
119‧‧‧內連線通孔
120‧‧‧絕緣層
120a、200a、201a、202a、300a、1120a、1200a、1300a‧‧‧頂表面
125‧‧‧溝槽
125b、126b、300b‧‧‧底表面
125c、126c、200c、300c‧‧‧側壁
126‧‧‧初步溝槽
200、201、202‧‧‧通孔結構
205‧‧‧襯墊層
210‧‧‧阻擋圖案
211、1210‧‧‧第一阻擋圖案
212、2210‧‧‧第二阻擋圖案
220‧‧‧晶種圖案
221、1220‧‧‧第一晶種圖案
222、2220‧‧‧第二晶種圖案
230‧‧‧導電通孔
231、1230‧‧‧第一導電通孔
232、2230‧‧‧第二導電通孔
250‧‧‧通孔孔洞
290‧‧‧端部部分
295‧‧‧缺陷
296‧‧‧殘留缺陷
300‧‧‧焊盤結構
310‧‧‧晶種焊盤
311‧‧‧晶種層
312‧‧‧導電層
320‧‧‧導電焊盤
400‧‧‧連接端子
1000‧‧‧封裝基底
1001‧‧‧外部端子
1100‧‧‧第一基底
1110‧‧‧第一電路層
1115‧‧‧第一電晶體
1116‧‧‧第一內連線結構
1120‧‧‧第一絕緣層
1200、1201‧‧‧第一通孔結構
1202、2200‧‧‧第二通孔結構
1300‧‧‧第一焊盤結構
1310‧‧‧第一晶種焊盤
1320‧‧‧第一導電焊盤
1400‧‧‧第一連接端子
1500‧‧‧第一黏合膜
2100‧‧‧第二基底
2110‧‧‧第二電路層
2115‧‧‧第二電晶體
2116‧‧‧第二內連線結構
2120‧‧‧第二絕緣層
2300‧‧‧第二焊盤結構
2400‧‧‧第二連接端子
2500‧‧‧第二黏合膜
3100‧‧‧第三基底
3110‧‧‧第三電路層
3120‧‧‧第三絕緣層
3200‧‧‧第三通孔結構
3300‧‧‧第三焊盤結構
3400‧‧‧第三連接端子
3500‧‧‧第三黏合膜
4100‧‧‧第四基底
4110‧‧‧第四電路層
4400‧‧‧第四連接端子
4500‧‧‧第四黏合膜
5000‧‧‧模塑層
IIB、IIC、IIIB、V‧‧‧區
IIB'-IIB''、IIIB-IIIB'‧‧‧線
θ1、θ1'、θ2‧‧‧角度
根據附圖及隨附詳細說明，本發明概念將變得更顯而易見。 圖1是示出根據本發明概念示例性實施例的半導體元件的剖視圖。 圖2A是示出根據本發明概念示例性實施例的半導體元件的平面圖。 圖2B是根據本發明概念示例性實施例的沿圖2A所示線IIB'-IIB''截取的剖視圖。 圖2C是圖2B所示區IIC的放大圖。 圖2D是根據本發明概念另一個示例性實施例的沿線IIB'-IIB''截取的剖視圖。 圖3A是示出根據本發明概念示例性實施例的半導體元件的平面圖。 圖3B是沿圖3A所示線IIIB-IIIB'截取的剖視圖。 圖4A至圖4G是示出根據本發明概念示例性實施例的製造半導體元件的方法的剖視圖。 圖4H是沿圖2A所示線IIB-IIB’截取的用於解釋根據本發明概念示例性實施例的附加平坦化製程的剖視圖。 圖5A是示出根據本發明概念示例性實施例的半導體封裝的剖視圖。 圖5B是圖5A所示區B的放大圖。

Claims (25)

  1. 一種半導體元件，包括： 基底； 絕緣層，位於所述基底上，所述絕緣層包括溝槽； 至少一個通孔結構，穿透所述基底且突出在所述溝槽的底表面上方；以及 導電結構，在所述溝槽中環繞所述至少一個通孔結構。
  2. 如申請專利範圍第1項所述的半導體元件，其中所述絕緣層的頂表面、所述至少一個通孔結構的頂表面及所述導電結構的頂表面實質上共面。
  3. 如申請專利範圍第1項所述的半導體元件，其中所述絕緣層具有位於所述溝槽之外的第一頂表面、位於所述溝槽的底部處的第二頂表面及連接所述第一頂表面與所述第二頂表面的第三頂表面，所述第一頂表面界定所述溝槽的頂部，且所述第二頂表面位於所述第一頂表面與所述絕緣層的底表面之間。
  4. 如申請專利範圍第1項所述的半導體元件，其中所述溝槽在所述溝槽的頂部處具有第一寬度且在所述溝槽的底部處具有第二寬度，且所述第一寬度大於所述第二寬度。
  5. 如申請專利範圍第1項所述的半導體元件，其中所述至少一個通孔結構與所述導電結構包含同一種金屬材料。
  6. 如申請專利範圍第1項所述的半導體元件，還包括阻擋圖案，沿所述溝槽的第一側壁、所述溝槽的所述底部及所述溝槽的第二側壁，所述第一側壁是位於所述至少一個通孔結構與所述導電結構之間的側壁，且所述第二側壁是所述溝槽的位於所述導電結構與所述絕緣層之間的側壁。
  7. 如申請專利範圍第6項所述的半導體元件，其中所述至少一個通孔結構與所述導電結構包含彼此不同的金屬材料。
  8. 如申請專利範圍第1項所述的半導體元件，其中所述絕緣層具有比所述基底的熱膨脹係數大的熱膨脹係數。
  9. 如申請專利範圍第8項所述的半導體元件，其中所述絕緣層包括有機絕緣層或聚合物中的至少一種。
  10. 如申請專利範圍第1項所述的半導體元件，其中所述至少一個通孔結構包括連接通孔結構及對準通孔結構，所述對準通孔結構與所述連接通孔結構間隔開，且所述對準通孔結構用作對準鍵。
  11. 如申請專利範圍第1項所述的半導體元件，其中所述導電結構用作結合焊盤或再分佈層中的一者。
  12. 一種半導體元件，包括： 基底； 絕緣層，位於所述基底上，所述絕緣層界定溝槽，所述絕緣層具有位於所述溝槽之外的第一頂表面、位於所述溝槽的底部處的第二頂表面及連接所述第一頂表面與所述第二頂表面的第三頂表面，所述溝槽從所述絕緣層的所述第一頂表面延伸到在垂直方向上位於所述絕緣層的所述第一頂表面與所述絕緣層的底表面之間的點； 至少一個導電通孔結構，穿透所述基底且突出在所述溝槽的底部上方；以及 至少一個導電結構，在所述溝槽中環繞所述至少一個導電通孔結構。
  13. 如申請專利範圍第12項所述的半導體元件，其中所述絕緣層的所述第一頂表面、所述至少一個導電通孔結構的頂表面及所述至少一個導電結構的頂表面實質上共面。
  14. 如申請專利範圍第12項所述的半導體元件，其中所述溝槽在所述溝槽的頂部處具有第一寬度且在所述溝槽的底部處具有第二寬度，且所述第一寬度大於所述第二寬度。
  15. 如申請專利範圍第12項所述的半導體元件，其中所述至少一個通孔結構與所述至少一個導電結構包含同一種金屬材料中的至少一種。
  16. 如申請專利範圍第12項所述的半導體元件，其中還包括阻擋圖案，沿所述溝槽的第一側壁、所述溝槽的底部及所述溝槽的第二側壁，所述第一側壁是位於所述至少一個通孔結構與所述至少一個導電結構之間的側壁，且所述第二側壁是所述溝槽的位於所述至少一個導電結構與所述絕緣層之間的側壁。
  17. 如申請專利範圍第12項所述的半導體元件，其中所述絕緣層具有比所述基底的熱膨脹係數大的熱膨脹係數。
  18. 如申請專利範圍第17項所述的半導體元件，其中所述絕緣層包括有機絕緣層或聚合物中的至少一種。
  19. 一種半導體元件，當在平面圖中觀察時，所述半導體元件包括： 第一金屬結構，包含第一金屬材料； 阻擋金屬圖案，環繞所述第一金屬結構；以及 導電結構，環繞所述阻擋金屬圖案，所述導電結構包含第二金屬材料；以及絕緣層，環繞所述導電結構。
  20. 如申請專利範圍第19項所述的半導體元件，其中還包括用於所述第一金屬結構的晶種圖案，沿所述阻擋金屬圖案的內側壁。
  21. 一種製造半導體元件的方法，包括： 形成通孔結構，所述通孔結構朝基底的第二表面穿透過所述基底的第一表面，所述第二表面與所述第一表面相對； 在所述基底的所述第二表面處薄化所述基底，使得所述通孔結構突出在所述基底的經調整的所述第二表面上方； 在所述基底的經調整的所述第二表面上形成絕緣層； 在所述絕緣層中形成溝槽，以環繞所述通孔結構的突出部分； 在所述基底的經調整的所述第二表面上及所述溝槽之上提供導電層； 將所述導電層、所述通孔結構及所述絕緣層平坦化，使得所述導電層的頂表面、所述通孔結構的頂表面及所述絕緣層的頂表面共面，且所述導電層環繞所述通孔結構以形成導電結構；以及 提供利用所述導電結構的半導體元件。
  22. 如申請專利範圍第21項所述的半導體元件，其中形成所述溝槽包括： 在所述絕緣層中形成初步溝槽；以及 對所述絕緣層進行處理，以形成所述溝槽，使得所述溝槽在所述溝槽的頂部處具有第一寬度且在所述溝槽的底部處具有第二寬度，且所述第一寬度大於所述第二寬度。
  23. 如申請專利範圍第22項所述的半導體元件，其中所述處理包括執行熱硬化製程或熱流動製程中的至少一種。
  24. 如申請專利範圍第21項所述的半導體元件，還包括： 檢驗所述導電結構是否具有殘留缺陷；以及 回應於所述檢驗表明存在所述殘留缺陷來重複進行所述平坦化，直到所述檢驗不再表明存在所述殘留缺陷。
  25. 如申請專利範圍第21項所述的半導體元件，其中所述導電結構是結合焊盤或再分佈層中的一者。
TW107102420A 2017-04-28 2018-01-24 半導體元件及其製造方法 TWI746776B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
??10-2017-0055493 2017-04-28
KR1020170055493A KR102406573B1 (ko) 2017-04-28 2017-04-28 반도체 소자 및 그 제조 방법
KR10-2017-0055493 2017-04-28
US15/815,032 US10211070B2 (en) 2017-04-28 2017-11-16 Semiconductor device and method for manufacturing the same
US15/815,032 2017-11-16

Publications (2)

Publication Number Publication Date
TW201842644A true TW201842644A (zh) 2018-12-01
TWI746776B TWI746776B (zh) 2021-11-21

Family

ID=63917406

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107102420A TWI746776B (zh) 2017-04-28 2018-01-24 半導體元件及其製造方法

Country Status (4)

Country Link
US (4) US10211070B2 (zh)
KR (1) KR102406573B1 (zh)
CN (2) CN108807318A (zh)
TW (1) TWI746776B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI817034B (zh) * 2019-08-26 2023-10-01 英商思睿邏輯國際半導體有限公司 用於在積體電路封裝中極小化機械應力之金屬層圖案

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11625523B2 (en) 2016-12-14 2023-04-11 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips
CN108288616B (zh) 2016-12-14 2023-04-07 成真股份有限公司 芯片封装
US10290584B2 (en) 2017-05-31 2019-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive vias in semiconductor packages and methods of forming same
US10447274B2 (en) 2017-07-11 2019-10-15 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
US10957679B2 (en) 2017-08-08 2021-03-23 iCometrue Company Ltd. Logic drive based on standardized commodity programmable logic semiconductor IC chips
US10630296B2 (en) 2017-09-12 2020-04-21 iCometrue Company Ltd. Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
US10608642B2 (en) 2018-02-01 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells
US10623000B2 (en) 2018-02-14 2020-04-14 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
CN110223951B (zh) * 2018-03-02 2021-08-06 中芯国际集成电路制造(北京)有限公司 半导体结构及其形成方法
US10608638B2 (en) 2018-05-24 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US10892011B2 (en) 2018-09-11 2021-01-12 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US10937762B2 (en) 2018-10-04 2021-03-02 iCometrue Company Ltd. Logic drive based on multichip package using interconnection bridge
US11616046B2 (en) 2018-11-02 2023-03-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US11075145B2 (en) * 2019-05-16 2021-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including through die via and manufacturing method thereof
US10985154B2 (en) 2019-07-02 2021-04-20 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
EP3998524A4 (en) * 2019-07-08 2022-07-13 BOE Technology Group Co., Ltd. INDICATOR
US11887930B2 (en) 2019-08-05 2024-01-30 iCometrue Company Ltd. Vertical interconnect elevator based on through silicon vias
US11373981B2 (en) * 2019-08-28 2022-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Package and manufacturing method thereof
US11637056B2 (en) 2019-09-20 2023-04-25 iCometrue Company Ltd. 3D chip package based on through-silicon-via interconnection elevator
US20210125948A1 (en) * 2019-10-28 2021-04-29 Nanya Technology Corporation Semiconductor device and method for fabricating the same
US11205607B2 (en) * 2020-01-09 2021-12-21 Nanya Technology Corporation Semiconductor structure and method of manufacturing thereof
KR20210094329A (ko) * 2020-01-21 2021-07-29 삼성전자주식회사 반도체 패키지, 및 이를 가지는 패키지 온 패키지
US11600526B2 (en) 2020-01-22 2023-03-07 iCometrue Company Ltd. Chip package based on through-silicon-via connector and silicon interconnection bridge
JP7102481B2 (ja) * 2020-10-09 2022-07-19 Ｎｉｓｓｈａ株式会社 射出成形品及びその製造方法
KR20220129924A (ko) 2021-03-17 2022-09-26 삼성전자주식회사 인터포저, 이의 제조 방법, 및 이를 가지는 반도체 패키지
CN113078119B (zh) * 2021-03-26 2022-03-18 长鑫存储技术有限公司 半导体结构的制作方法及半导体结构
US11631631B2 (en) * 2021-05-28 2023-04-18 Advanced Semiconductor Engineering, Inc. Semiconductor device including via structure for vertical electrical connection
US11784111B2 (en) 2021-05-28 2023-10-10 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same
KR20230007006A (ko) * 2021-07-05 2023-01-12 삼성전자주식회사 비아 구조체를 포함하는 반도체 장치 및 이의 제조 방법

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6731007B1 (en) * 1997-08-29 2004-05-04 Hitachi, Ltd. Semiconductor integrated circuit device with vertically stacked conductor interconnections
JP3925780B2 (ja) * 1999-12-15 2007-06-06 エー・エス・エムジニテックコリア株式会社 触媒及び化学気相蒸着法を用いて銅配線及び薄膜を形成する方法
KR100587677B1 (ko) 2004-03-18 2006-06-08 삼성전자주식회사 전계효과 트랜지스터 구조 및 그의 제조방법
US7608549B2 (en) * 2005-03-15 2009-10-27 Asm America, Inc. Method of forming non-conformal layers
US7932179B2 (en) 2007-07-27 2011-04-26 Micron Technology, Inc. Method for fabricating semiconductor device having backside redistribution layers
US8791549B2 (en) * 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
WO2013062593A1 (en) 2011-10-28 2013-05-02 Intel Corporation 3d interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias
US8803316B2 (en) 2011-12-06 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV structures and methods for forming the same
KR101870155B1 (ko) * 2012-02-02 2018-06-25 삼성전자주식회사 비아 연결 구조체, 그것을 갖는 반도체 소자 및 그 제조 방법들
US20130320522A1 (en) * 2012-05-30 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Re-distribution Layer Via Structure and Method of Making Same
KR101931115B1 (ko) * 2012-07-05 2018-12-20 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR20140024674A (ko) 2012-08-20 2014-03-03 삼성전자주식회사 관통 비아 구조체 및 재배선 구조체를 갖는 반도체 소자
KR20150073473A (ko) * 2013-12-23 2015-07-01 에스케이하이닉스 주식회사 반도체 소자 및 제조 방법
US9252110B2 (en) * 2014-01-17 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of forming same
US9209128B2 (en) 2014-04-01 2015-12-08 International Business Machines Corporation Integrated circuit assembly with cushion polymer layer
KR102303983B1 (ko) * 2014-09-22 2021-09-23 삼성전자주식회사 반도체 장치 및 그 제조 방법, 및 상기 반도체 장치를 포함하는 반도체 패키지
US9397038B1 (en) 2015-02-27 2016-07-19 Invensas Corporation Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates
US9899342B2 (en) * 2016-03-15 2018-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package, redistribution circuit structure, and method of fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI817034B (zh) * 2019-08-26 2023-10-01 英商思睿邏輯國際半導體有限公司 用於在積體電路封裝中極小化機械應力之金屬層圖案

Also Published As

Publication number Publication date
US10699915B2 (en) 2020-06-30
CN108807318A (zh) 2018-11-13
US20200273723A1 (en) 2020-08-27
US11574819B2 (en) 2023-02-07
US20190139785A1 (en) 2019-05-09
US10937667B2 (en) 2021-03-02
US10211070B2 (en) 2019-02-19
US20180315620A1 (en) 2018-11-01
TWI746776B (zh) 2021-11-21
KR20180121737A (ko) 2018-11-08
CN116705737A (zh) 2023-09-05
US20210183663A1 (en) 2021-06-17
KR102406573B1 (ko) 2022-06-09

Similar Documents

Publication Publication Date Title
TWI746776B (zh) 半導體元件及其製造方法
US10079225B2 (en) Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package
KR101918608B1 (ko) 반도체 패키지
KR102379165B1 (ko) Tsv 구조를 구비한 집적회로 소자 및 그 제조 방법
TW201813018A (zh) 扇出晶圓級封裝型半導體封裝以及包含其的疊層封裝型半導體封裝
US20160351472A1 (en) Integrated circuit device and method of manufacturing the same
KR102422460B1 (ko) 반도체 소자
TW201818520A (zh) 半導體封裝及其製作方法
US10580726B2 (en) Semiconductor devices and semiconductor packages including the same, and methods of manufacturing the semiconductor devices
TWI551199B (zh) 具電性連接結構之基板及其製法
US11929318B2 (en) Package structure and method of forming the same
KR102010667B1 (ko) 상이한 평면들 상에서의 단자 연결들을 위한 융기된 비아
KR20170011366A (ko) 반도체 칩 및 이를 가지는 반도체 패키지
TW202114111A (zh) 封裝
KR102485701B1 (ko) 반도체 디바이스 및 방법
KR20200052536A (ko) 관통 실리콘 비아를 포함하는 반도체 소자 및 그 제조 방법
TWI775443B (zh) 半導體封裝及其形成方法
KR101889506B1 (ko) 반도체 장치 및 그의 제조방법
KR101013545B1 (ko) 스택 패키지 및 그의 제조방법
KR101624851B1 (ko) 내장형 재배선을 갖는 반도체 장치 및 이의 제조 방법
US20240030187A1 (en) Semiconductor package and method of manufacturing semiconductor package
KR101150464B1 (ko) 반도체 소자 및 그 형성 방법