TWI817034B - 用於在積體電路封裝中極小化機械應力之金屬層圖案 - Google Patents

用於在積體電路封裝中極小化機械應力之金屬層圖案 Download PDF

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TWI817034B
TWI817034B TW109128599A TW109128599A TWI817034B TW I817034 B TWI817034 B TW I817034B TW 109128599 A TW109128599 A TW 109128599A TW 109128599 A TW109128599 A TW 109128599A TW I817034 B TWI817034 B TW I817034B
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integrated circuit
circuit device
metal
external field
metal pattern
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TW109128599A
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TW202123347A (zh
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凱薩琳 蘿斯 荷蘭德
馬克 Ｌ 特拉比爾
龐耀宇
亞歷山大 巴爾
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英商思睿邏輯國際半導體有限公司
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Abstract

本發明揭示的一種方法可包含在一經製造積體電路裝置之一金屬層中及在該經製造積體電路裝置之一目標凸塊下方形成一金屬圖案，其中該金屬圖案具有一內部形狀及一外部場使得在該內部形狀與該外部場之間產生該金屬層中之一空隙空間並使該空隙空間在形成於該目標凸塊下方之一凸塊下金屬之一輪廓上大致居中，而在該輪廓之任一側上具有與該內部形狀及該外部場之一禁入距離使得該金屬極小化該經製造積體電路裝置內之底層結構上之機械應力之局部變動。

Description

用於在積體電路封裝中極小化機械應力之金屬層圖案
本發明大體上係關於一種半導體製造，且更特定言之係關於一頂層金屬層之圖案化以便極小化或消除在積體電路封裝(包含晶圓級晶片尺度封裝)中之機械應力。
半導體裝置製造係一種用於產生存在於許多電氣及電子裝置中之積體電路之程序。半導體裝置製造包含光微影、機械及化學處理步驟之多步驟序列，在此期間，在由半導電材料製成之晶圓上逐漸產生電子電路。例如，在半導體裝置製造期間，可在單個半導體晶粒上形成包含電晶體、電阻器、電容器、電感器及二極體之許多離散電路總成。
漸增地，形成在半導體上之積體電路通常封裝為晶圓級晶片尺度封裝(WLCSP)。一般而言，與將晶圓切割成個別電路(晶粒)且接著個別地封裝晶粒之更習知方法相反，WLCSP之製造涉及在一積體電路仍係一半導體晶圓之部分時封裝該積體電路。因此，所得封裝可實際上具有與晶粒相同之大小。由於此等裝置之大小約束，WLCSP之主要應用領域係智慧型電話及類似行動裝置。例如，智慧型電話中由WLCSP提供之功能可包含感測器、電力管理、無線通信、放大器等。
在形成WLCSP時，可在形成於半導體中之一底層上圖案化積體電路裝置，接著多個金屬佈線層(例如，銅)，然後頂層佈線金屬(例如，鋁)。在頂層佈線金屬上方，WLCSP可包含金屬重佈層(例如，銅或銅合金)，該金屬重佈層可與凸塊下金屬(例如，銅或銅合金)接觸，該凸塊下金屬繼而與焊料凸塊接觸。可藉由將積體電路晶粒之各種焊料凸塊熔融至一基板(例如，印刷電路板基板)上之對應金屬襯墊平台且接著允許該兩者冷卻來完成將該晶粒附接至該基板上。
由於WLCSP晶片(已包裝)及基板之機械及/或熱特性之失配，將晶片焊接至基板、在將晶粒附接至基板之後進行冷卻及/或溫度循環之程序可引起底層矽結構上之機械應力(例如，張力及/或壓縮)。此等機械應力可影響積體電路之電特性，從而可能導致具有與在WLCSP晶粒附接至基板之前測試及特性化之電特性明顯不同之電特性之一積體電路。
根據本發明之教示，可減少或消除與一積體電路中之被動電組件之製造相關聯之某些缺點及問題。
根據本發明之實施例，一種方法可包含在一經製造積體電路裝置之金屬層中及在該經製造積體電路裝置之一目標凸塊下方形成一金屬圖案，其中該金屬圖案具有一內部形狀及一外部場使得在該內部形狀與該外部場之間產生該金屬層中之一空隙空間，且使空隙空間在形成於目標凸塊下方之一凸塊下金屬之一輪廓上大致居中，而在輪廓之任一側上具有與該內部形狀及該外部場之一禁入距離(keepout distance)使得該金屬極小化該經製造積體電路裝置內之底層結構上之機械應力之局部變動。
根據本發明之此等及其他實施例，一種經製造積體電路裝 置可包含形成在該經製造積體電路裝置之一金屬層中及該經製造積體電路裝置之一目標凸塊下方之一金屬圖案，其中：該金屬圖案具有一內部形狀及一外部場，使得在該內部形狀與該外部場之間產生該金屬層中之一空隙空間；且該空隙空間在形成於目標凸塊下方之一凸塊下金屬之一輪廓上大致居中，而在輪廓之任一側上具有與該內部形狀及該外部場之一禁入距離使得該金屬極小化該經製造積體電路裝置內之底層結構上之機械應力之局部變動。
自包含於本文中之圖、描述及發明申請專利範圍，一般技術人員可容易明白本發明之技術優點。實施例之目的及優點將至少藉由發明申請專利範圍中具體指出之元件、特徵及組合來達成。
應理解，前述一般描述及下文詳細描述係說明性實例且不限製本發明中闡述之發明申請專利範圍。
100:半導體基板
102:積體電路
104:電絕緣層
106:頂部金屬化層
108:電絕緣層
110:凸塊下金屬
112:凸塊
201:距離
202:禁入距離
203:外部場
204:內部形狀
205:空隙空間
206:凸塊下金屬輪廓
207:目標凸塊平台
210:非目標凸塊
214:凸塊間距
301:線性橫向間隙
302:間隙距離
303:共心環
304:角度段
304A:內部形狀之部分
304B:內部形狀之部分
305A:外部場之部分
305B:外部場之部分
306:橋接段
藉由參考結合附圖進行之以下描述，可獲得對本發明實施例及其優點之更完整理解，其中相同元件符號指示相同特徵，且其中：圖1繪示根據本發明之實施例之在其中圖案化有一積體電路之一半導體基板之一部分之側視截面圖；圖2繪示根據本發明之實施例之一半導體基板之一部分之俯視平面圖，其描繪用於在包括半導體基板之一積體電路封裝中極小化機械應力之一金屬層之例示性圖案化；圖3A繪示根據本發明之實施例之一半導體基板之一部分之俯視平面圖，其描繪用於在包括半導體基板之一積體電路封裝中極小化機械應力之具有一間隙之一金屬層之例示性圖案化。
圖3B繪示根據本發明之實施例之一半導體基板之一部分之俯視平面圖，其描繪用於在包括半導體基板之一積體電路封裝中極小化機械應力之具有複數個共心環之一金屬層之例示性圖案化；圖3C繪示根據本發明之實施例之一半導體基板之一部分之俯視平面圖，其描繪用於在包括半導體基板之一積體電路封裝中極小化機械應力之具有角度段之一金屬層之例示性圖案化。
圖3D繪示根據本發明之實施例之一半導體基板之一部分之俯視平面圖，其描繪用於在包括半導體基板之一積體電路封裝中極小化機械應力之一金屬層之例示性圖案化，該圖案化包含一內部形狀與一外部場之間之一橋接段；及圖3E繪示根據本發明之實施例之一半導體基板之一部分之俯視平面圖，其描繪用於在包括半導體基板之一積體電路封裝中極小化機械應力之一金屬層之例示性圖案化，該圖案化包含一內部形狀與一外部場之間之複數個橋接段。
相關申請案
本發明主張2019年8月26日申請之美國臨時專利申請案第62/891,566號之優先權利，該案之全文以引用之方式併入本文中。
圖1繪示根據本發明之實施例之在其中圖案化有一積體電路102之一半導體基板100之一部分之側視截面圖。半導體基板100可由任何合適之材料形成，包含但不限於矽、碳化矽、鍺、磷化鎵、氮化鎵、砷化鎵、磷化銦、氮化銦、砷化銦等。儘管在圖1中未明確展示，但許多裝置(例如，電晶體，電阻器等)可形成在半導體基板100內以產生積體電路 102。積體電路102亦可包含多個金屬佈線層(例如，複數個銅層，未在圖1中明確展示)。可(例如，使用已知技術)在此積體電路102上形成一電絕緣層104，該電絕緣層104經圖案化有開口以允許頂部金屬化層106(例如，包括例如銅或銅合金之金屬重佈層)本身形成在電絕緣層104上且經圖案化以提供形成在半導體基板100上之凸塊112與形成在下方之積體電路102之間之所要電連接能力。可(例如，使用已知技術)在頂部金屬化層106上形成另一電絕緣層108，且其自身經圖案化有開口以允許頂部金屬化層106提供頂部金屬化層106與形成且介接在頂部金屬化層106與凸塊112之間之凸塊下金屬110(例如，銅或銅合金)之間之所要電連接能力。凸塊112可由焊料或亦具有允許凸塊112及圖1中所描繪之「堆疊」之附接藉由將凸塊112熔融至一基板(例如，印刷電路板基板)上之對應金屬襯墊平台且允許凸塊112冷卻並返回至固相來完成之所要熱特性(例如，熔點)之任何其他合適導電材料而形成。
圖2繪示根據本發明之實施例之半導體基板100之一部分之俯視平面圖，其描繪用於在包括半導體基板100之一積體電路封裝中極小化機械應力之頂部金屬化層106之例示性圖案化。如圖2中所示，圖案/形狀可靠近凸塊下金屬110形成在一目標凸塊平台207之頂部金屬化層106中(且因此，靠近凸塊112形成在頂部金屬化層106中)以便將機械應力侷限於圖2中所描繪之凸塊下金屬輪廓206之區域(例如，凸塊下金屬110之覆蓋區)，其可極小化或消除半導體基板100中之底層結構上之機械應力之局部變動。
頂部金屬化層106之此圖案化可包含一內部形狀204，其可包括圓形或n邊多邊形。在一些實施例中，內部形狀204可包含具有數個 邊(例如，八個或更多個)之多邊形，使得此多邊形近似一圓形。頂部金屬化層106之此圖案化亦可包含藉由形成在頂部金屬化層106中之一空隙空間205與內部形狀204分開之一外部場203。空隙空間205可大致居中於凸塊下金屬輪廓206上與內部形狀204之中心之一距離201處(例如，在製造公差及解析度內居中)，而凸塊下金屬輪廓206之任一側上有一禁入距離202。禁入距離202可為任何合適距離，使得其未侵犯具有與目標凸塊平台207之一凸塊間距214之非目標凸塊210。外部場203可具有任意外部邊緣，但可維持與凸塊下金屬輪廓206之禁入距離202。
儘管圖2描繪一特定圖案，但可根據本發明使用其他合適圖案化。
例如，圖3A繪示根據本發明之實施例之半導體基板100之一部分之俯視平面圖，其描繪具備具有一間隙距離302之一線性橫向間隙301之一金屬化層(例如，頂部金屬化層106)之例示性圖案化。在此一實施例中，一金屬圖案可維持相同整體輪廓，包含禁入距離202，如上文關於圖2所示及所述。圖3A中所示之圖案化在金屬圖案之不同特徵電耦合至不同電網路(例如，內部形狀204之部分304A可耦合至與內部形狀204之部分304B不同之一電網路，外部場203之部分305A可耦合至與外部場203之部分305B不同之一電網路)之情況下可係有用的。
作為另一實例，圖3B繪示根據本發明之實施例之半導體基板100之一部分之俯視平面圖，其描繪具有複數個較小共心環303之一金屬化層(例如，頂部金屬化層106)之例示性圖案化。各共心環303可包括圓形或n邊多邊形。在一些實施例中，各共心環303可包含具有數個邊(例如，八個或更多個)之多邊形，使得該多邊形近似一圓形。如圖3B中所描 繪，各共心環303可具有彼此近似(例如，在製造公差及解析度內)相同之中心，及/或可具有與內部形狀204近似(例如，在製造公差及解析度內)相同之中心。如圖3B中所示，使用較小共心環303可在金屬化中產生一梯度，此可進一步增強圖案化之機械應力極小化性質。
作為又一實例，圖3C繪示根據本發明之實施例之半導體基板100之一部分之俯視平面圖，其描繪具有一角度段304之一金屬化層(例如，頂部金屬化層106)之例示性圖案化。在此一實施例中，一金屬圖案可維持相同整體輪廓，包含如上文關於圖2所示及所述之禁入距離202，但僅具有一或多個部分，如由一或多個角度段304所界定，各角度段304存在於此輪廓中具有介於0度與360度之間之一角度。圖3C中所示之圖案化在金屬圖案之不同特徵電耦合至不同電網路之情況下可係有用的。
圖3D繪示根據本發明之實施例之一半導體基板100之一部分之俯視平面圖，其描繪一金屬化層(例如，頂部金屬化層106)之例示性圖案化，該圖案化包含內部形狀204與外部場203之間之一橋接段306。在此一實施例中，一金屬圖案可維持相同整體輪廓，包含禁入距離202，如上文關於圖2所示及所述。圖3D中所示之圖案化在金屬圖案之不同特徵電耦合至相同電網路(例如，橋接段306將內部形狀204及外部場203電耦合在一起，使得內部形狀204及外部場203具有相同電節點)之情況下可係有用的。
圖3E繪示根據本發明之實施例之一半導體基板100之一部分之俯視平面圖，其描繪一金屬化層(例如，頂部金屬化層106)之例示性圖案化，該圖案化包含內部形狀204與外部場203之間之複數個(例如兩個)橋接段306。在此一實施例中，一金屬圖案可維持相同整體輪廓，包含禁 入距離202，如上文關於圖2所示及所述。圖3E中所示之圖案化在金屬圖案之不同特徵電耦合至相同電網路(例如，橋接段306將內部形狀204及外部場203電耦合在一起，使得內部形狀204及外部場203具有相同電節點)之情況下可係有用的。
儘管圖2及圖3A至圖3E中所描繪之圖案畫被展示並論述為存在於頂部金屬化層106中，但應當理解，此圖案化可形成在任何其他合適金屬化層中。此外，包含在此圖案化內之金屬化(例如，在內部形狀204及外部場203中之任一者或兩者中)可傳導電能(例如，呈電壓或電流形式之信號資訊，或用於積體電路裝置之操作之供應電壓)或可為非電活化。此外，儘管圖2及圖3A至圖3E可僅描繪圖案化之一單一例項，但可在與半導體基板100相關聯之一或多個金屬化層上形成圖案化之多個例項。
如本文中所使用，當兩個或兩個以上元件被稱為「彼此」耦合時，此術語指示此兩個或更多個元件處於電子通信或機械通信(若適用)，無論間接或直接連接，具有或不具有中介元件。
本發明涵蓋一般技術者能理解之本文中之例示性實施例之所有改變、替代、變動、更改及修改。類似地，隨附發明申請專利範圍視情況涵蓋一般技術者能理解之本文中之例示性實施例之所有改變、替代、變動、更改及修改。此外，隨附發明申請專利範圍中所提及之一設備或系統或一設備或系統之一組件(其經調適、經配置、能夠、經組態以、經啟用以、可操作以或操作以執行一特定功能)涵蓋該設備、系統或組件，無論啟動、接通或解鎖其或該特定功能，只要該設備、系統或組件係經如此調適、配置、具備能力、組態、啟用、可操作或操作。因此，可在不背離本發明之範疇的情況下對本文中所描述之系統、設備及方法進行修改、新 增或省略。例如，可整合或分離系統及設備之組件。此外，本文中所揭示之系統及設備之操作可由更多、更少或其他組件執行且所描述之方法可包括更多、更少或其他步驟。另外，可依任何適合順序執行步驟。如本文件中所使用，「各」係指一組之各成員或一組之一子集之各成員。
儘管圖中繪示及下文中描述例示性實施例，但可使用任何數目個技術(無論當前已知或未知)來實施本發明之原理。本發明絕不受限於圖式中所繪示及上文所描述之例示性實施方案及技術。
除非另有明確說明，否則圖式中所描繪之物件未必按比例繪製。
本文中所列舉之所有實例及條件用語意欲用於教學目的以幫助讀者理解由發明者提出之揭示內容及概念以增進本技術，且應被解釋為不限於此等具體列舉之實例及條件。儘管已詳細描述本發明之實施例，但應瞭解，可在不背離本發明之精神及範疇的情況下對本發明進行各種改變、替代及更改。
儘管上文已列舉特定優點，但各種實施例可包含一些列舉優點、不包含任何列舉優點或包含所有列舉優點。另外，一般技術者可易於在複習以上圖及描述之後明白其他技術優點。
為幫助專利局及本申請案所發佈之任何專利之任何讀者理解本發明之隨附發明申請專利範圍，申請者希望指出，其不意欲隨附發明申請專利範圍或請求項元件之任何者援引35 U.S.C.§ 112(f)，除非特定請求項中明確使用字詞「用於…之構件」或「用於…之步驟」。
100:半導體基板
106:頂部金屬化層
201:距離
202:禁入距離
203:外部場
204:內部形狀
205:空隙空間
206:凸塊下金屬輪廓
207:目標凸塊平台
210:非目標凸塊
214:凸塊間距

Claims (36)

  1. 一種用以製造積體電路裝置之方法，其包括：在一經製造積體電路裝置之一金屬層中及在該經製造積體電路裝置之一凸塊下方形成一金屬圖案，其中該金屬圖案具有一內部形狀及一外部場，使得在該內部形狀與該外部場之間產生該金屬層中之一空隙空間；及使該空隙空間在形成於該凸塊下方之一凸塊下金屬之一輪廓上大致居中，以使得從該內部形狀到該輪廓之一第一距離係大約等於從該外部場到該輪廓之一第二距離，使得該金屬極小化該經製造積體電路裝置內之底層結構上之機械應力之局部變動。
  2. 如請求項1之方法，其中該金屬層係該經製造積體電路裝置之一頂層金屬。
  3. 如請求項1之方法，其中該金屬層包含銅、一銅合金及鋁之一者。
  4. 如請求項1之方法，其中該第一距離及該第二距離具有一足夠距離使得該金屬圖案未侵犯鄰近於該凸塊之其它凸塊。
  5. 如請求項1之方法，其中該外部場具有一外部邊緣使得該外部場維持與該凸塊下金屬輪廓之該第二距離。
  6. 如請求項1之方法，其進一步包括在該金屬層中形成該金屬圖案之多 個例項。
  7. 如請求項1之方法，其中該金屬圖案之至少一部分在該經製造積體電路裝置之一積體電路中係電活化。
  8. 如請求項7之方法，其中該金屬圖案之至少一部分攜載信號資訊。
  9. 如請求項1之方法，其中該金屬圖案之至少一部分在該經製造積體電路裝置之一積體電路中係非電活化。
  10. 如請求項1之方法，其中該金屬圖案包括透過該內部形狀及該外部場之至少一者之一線性間隙分離。
  11. 如請求項1之方法，其中該金屬圖案包括與該內部形狀共心之複數個較小環。
  12. 如請求項11之方法，其中該複數個較小環之各者之形狀係圓形。
  13. 如請求項11之方法，其中該複數個較小環之各者係多邊形。
  14. 如請求項1之方法，其中該金屬圖案具有包括該內部形狀及外部場之一部分之一角度段。
  15. 如請求項1之方法，其中該內部形狀之形狀係圓形。
  16. 如請求項1之方法，其中該內部形狀之形狀係多邊形。
  17. 如請求項1之方法，其中該經製造積體電路裝置係一晶圓級晶片尺度封裝。
  18. 如請求項1之方法，其中形成該金屬圖案包括圖案化該金屬層以便產生該內部形狀與該外部場之間該金屬層內之至少一個橋接段使得該內部形狀及該外部場彼此電耦合。
  19. 一種經製造積體電路裝置，其包括形成於該經製造積體電路裝置之一金屬層中及該經製造積體電路裝置之一凸塊下方之一金屬圖案，其中：該金屬圖案具有一內部形狀及一外部場使得在該內部形狀與該外部場之間產生該金屬層中之一空隙空間；及該空隙空間在形成於該凸塊下方之一凸塊下金屬之一輪廓上大致居中，以使得從該內部形狀到該輪廓之一第一距離係大約等於從該外部場到該輪廓之一第二距離，使得該金屬極小化該經製造積體電路裝置內之底層結構上之機械應力之局部變動。
  20. 如請求項19之經製造積體電路裝置，其中該金屬層係該經製造積體電路裝置之一頂層金屬。
  21. 如請求項19之經製造積體電路裝置，其中該金屬層包括銅、一銅合金及鋁之一者。
  22. 如請求項19之經製造積體電路裝置，其中該第一距離及該第二距離具有一足夠距離使得該金屬圖案未侵犯鄰近於該凸塊之其它凸塊。
  23. 如請求項19之經製造積體電路裝置，其中該外部場具有一外部邊緣使得該外部場維持與該凸塊下金屬輪廓之該第二距離。
  24. 如請求項19之經製造積體電路裝置，其中該經製造積體電路裝置包括形成於該金屬層中之該金屬圖案之多個例項。
  25. 如請求項19之經製造積體電路裝置，其中該金屬圖案之至少一部分在該經製造積體電路裝置之一積體電路中係電活化。
  26. 如請求項25之經製造積體電路裝置，其中該金屬圖案之該至少一部分攜載信號資訊。
  27. 如請求項19之經製造積體電路裝置，其中該金屬圖案之至少一部分在該經製造積體電路裝置之一積體電路中係非電活化。
  28. 如請求項19之經製造積體電路裝置，其中該金屬圖案包括透過該內部形狀及該外部場之至少一者之一線性間隙分離。
  29. 如請求項19之經製造積體電路裝置，其中該金屬圖案包括與該內部形狀共心之複數個較小環。
  30. 如請求項29之經製造積體電路裝置，其中該複數個較小環之各者之形狀係圓形。
  31. 如請求項29之經製造積體電路裝置，其中該複數個較小環之各者係多邊形。
  32. 如請求項19之經製造積體電路裝置，其中該金屬圖案具有包括該內部形狀及該外部場之一部分之一角度段。
  33. 如請求項19之經製造積體電路裝置，其中該內部形狀之形狀係圓形。
  34. 如請求項19之經製造積體電路裝置，其中該內部形狀之形狀係多邊形。
  35. 如請求項19之經製造積體電路裝置，其中該經製造積體電路裝置係一晶圓級晶片尺度封裝。
  36. 如請求項19之經製造積體電路裝置，其進一步包括形成於該內部形 狀與該外部場之間該金屬層內之至少一個橋接段使得該內部形狀及該外部場彼此電耦合。
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