CN116705737A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN116705737A
CN116705737A CN202310693840.XA CN202310693840A CN116705737A CN 116705737 A CN116705737 A CN 116705737A CN 202310693840 A CN202310693840 A CN 202310693840A CN 116705737 A CN116705737 A CN 116705737A
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CN
China
Prior art keywords
trench
semiconductor device
insulating layer
top surface
substrate
Prior art date
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Pending
Application number
CN202310693840.XA
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English (en)
Inventor
李灿浩
郑显秀
柳翰成
李仁荣
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN116705737A publication Critical patent/CN116705737A/zh
Pending legal-status Critical Current

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  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

可提供一种半导体封装，所述半导体封装包括：第一半导体器件；第二半导体器件，位于所述第一半导体器件上；以及焊料球，位于所述第一半导体器件与所述第二半导体器件之间。所述第一半导体器件，包括：衬底；绝缘层，位于所述衬底上且包括沟槽；至少一个通孔结构，穿透所述衬底且突出在所述沟槽的底表面上方；以及导电结构，在所述沟槽中环绕所述至少一个通孔结构，且其中所述通孔结构与所述焊料球直接物理接触。

Description

半导体封装
本发明是2018年04月26日所提出的申请号为201810387480.X、发明名称为《半导体器件及其制造方法》的发明专利申请的分案申请。
技术领域
本发明概念的实施例涉及半导体器件及/或制造所述半导体器件的方法，且更具体来说，涉及包括通孔结构(via structure)及焊盘结构的半导体器件及/或制造所述半导体器件的方法。
背景技术
已开发出对半导体器件进行堆叠的技术来改善半导体产品的集成密度及性能。举例来说，在多芯片封装技术中，可在一个半导体封装中安装多个芯片(或半导体器件)。另外，在系统级封装(system-in package)技术中，可在一个半导体封装中堆叠不同种类的芯片(或半导体器件)，且所述不同种类的芯片(或半导体器件)作为一个系统运行。当对半导体器件进行堆叠时，可能需要一种用于提高堆叠半导体器件的驱动速度的方法。半导体器件可通过导电通孔电连接到另一个半导体器件或印刷电路板。导电通孔可提高电信号的传输速度。随着半导体器件已被高度集成，需要可靠的导电通孔。
发明内容
本发明概念的一些示例性实施例可提供可靠性得到提高的半导体器件及/或制造所述半导体器件的方法。
本发明概念的一些示例性实施例还可提供能够提高良率的制造半导体器件的方法。
根据本发明概念的示例性实施例，一种半导体器件包括：衬底；绝缘层，位于所述衬底上，所述绝缘层包括沟槽；至少一个通孔结构，穿透所述衬底且突出在所述沟槽的底表面上方；以及导电结构，在所述沟槽中环绕所述至少一个通孔结构。
根据本发明概念的示例性实施例，一种半导体器件包括：衬底；绝缘层，位于所述衬底上，所述绝缘层界定沟槽，所述绝缘层具有位于所述沟槽之外的第一顶表面、位于所述沟槽的底部处的第二顶表面及连接所述第一顶表面与所述第二顶表面的第三顶表面，所述沟槽从所述绝缘层的所述第一顶表面延伸到在垂直方向上位于所述绝缘层的所述第一顶表面与所述绝缘层的底表面之间的点；至少一个导电通孔结构，穿透所述衬底且突出在所述沟槽的所述底表面上方；以及至少一个导电结构，在所述沟槽中环绕所述至少一个导电通孔结构。
根据本发明概念的示例性实施例，一种半导体器件当在平面图中观察时包括：第一金属结构，包含第一金属材料；阻挡金属图案，环绕所述第一金属结构；以及导电结构，环绕所述阻挡金属图案，所述导电结构包含第二金属材料；以及绝缘层，环绕所述导电结构。
根据本发明概念的示例性实施例，一种制造半导体器件的方法包括：形成通孔结构，所述通孔结构朝衬底的第二表面穿透过所述衬底的第一表面，所述第二表面与所述第一表面相对；在所述衬底的所述第二表面处薄化所述衬底，使得所述通孔结构突出在所述衬底的经调整的第二表面上方；在所述衬底的经调整的所述第二表面上形成绝缘层；在所述绝缘层中形成沟槽，以环绕所述通孔结构的突出部分；在所述衬底的经调整的所述第二表面上及所述沟槽之上提供导电层；将所述导电层、所述通孔结构及所述绝缘层平坦化，使得所述导电层的顶表面、所述通孔结构的顶表面及所述绝缘层的顶表面共面，且所述导电层环绕所述通孔结构以形成导电结构；以及提供利用所述导电结构的半导体器件。
附图说明
根据附图及随附详细说明，本发明概念将变得更显而易见。
图1是示出根据本发明概念示例性实施例的半导体器件的剖视图。
图2A是示出根据本发明概念示例性实施例的半导体器件的平面图。
图2B是根据本发明概念示例性实施例的沿图2A所示线IIB'-IIB”截取的剖视图。
图2C是图2B所示区IIC的放大图。
图2D是根据本发明概念另一个示例性实施例的沿线IIB'-IIB”截取的剖视图。
图3A是示出根据本发明概念示例性实施例的半导体器件的平面图。
图3B是沿图3A所示线IIIB-IIIB'截取的剖视图。
图4A至图4G是示出根据本发明概念示例性实施例的制造半导体器件的方法的剖视图。
图4H是沿图2A所示线IIB'-IIB”截取的用于解释根据本发明概念示例性实施例的附加平坦化工艺的剖视图。
图5A是示出根据本发明概念示例性实施例的半导体封装的剖视图。
图5B是图5A所示区V的放大图。
具体实施方式
在下文中将详细阐述根据本发明概念一些示例性实施例的半导体器件。
图1是示出根据本发明概念示例性实施例的半导体器件的剖视图。
参照图1，半导体器件10可包括衬底100、通孔结构200及焊盘结构300。半导体器件10可为包括存储器芯片、逻辑芯片或其组合的半导体芯片。衬底100可为晶片级衬底或芯片级衬底。举例来说，衬底100可包含半导体材料，例如硅、锗或硅锗(silicon-germanium)。衬底100可具有彼此相对的第一表面100a与第二表面100b。衬底100的第二表面100b可实质上平行于衬底100的第一表面100a。衬底100的第一表面100a可为背侧表面。在衬底100的第一表面100a上可设置有绝缘层120。焊盘结构300可设置在绝缘层120中。衬底100的第二表面100b可为前侧表面。在衬底100的第二表面100b上可设置有电路层110。在电路层110的底表面上可设置有连接端子400。连接端子400可包括焊料球、凸块、柱或其任意组合。连接端子400可包含导电材料。举例来说，连接端子400可包含锡(Sn)、铅(Pb)、银(Ag)或其任意合金中的至少一种。
通孔结构200可穿过衬底100、绝缘层120及焊盘结构300设置。通孔结构200可电连接到焊盘结构300。通孔结构200可电连接到连接端子400中的至少一者。在本公开中，应理解，当称一元件“电连接到”另一个元件时，所述元件可直接连接到另一元件，或者可存在一个或多个中间元件。电信号可通过连接端子400及通孔结构200从外部系统传送到半导体器件10及/或可通过通孔结构200及连接端子400从半导体器件10传送到外部系统。在本公开中，应理解，当称一元件、器件或系统电连接到半导体器件时，所述元件、器件或系统可电连接到半导体器件的晶体管中的至少一者。绝缘层120、通孔结构200及焊盘结构300可在半导体器件10的顶表面处被暴露出。
图2A是示出根据本发明概念示例性实施例的半导体器件的平面图。图2B是沿图2A所示线IIB'-IIB”截取的剖视图。另外，图2B对应于图1所示区IIB的放大图。图2C是图2B所示区IIC的放大图。在下文中，为容易且方便地进行解释，将省略或仅简要提及对与以上示例性实施例中的元件相同的元件的说明。
参照图1、图2A、图2B、及图2C，半导体器件10可包括衬底100、电路层110、绝缘层120、通孔结构200及焊盘结构300。在衬底100的第二表面100b上可设置有电路层110。电路层110可包括绝缘图案111及112、晶体管115及互连结构116。晶体管115可形成在衬底100的第二表面100b上。第一绝缘图案111可设置在衬底100的第二表面100b上且可覆盖晶体管115。第二绝缘图案112可设置在第一绝缘图案111上。举例来说，绝缘图案111及112可包含氧化硅、氮化硅或氮氧化硅中的至少一种。互连结构116可包括接触塞117、互连图案118及互连通孔119。互连结构116可包含导电材料(例如，铜或钨)。接触塞117可穿透第一绝缘图案111以连接到晶体管115。互连图案118可设置在绝缘图案111与绝缘图案112之间。互连通孔119可穿透第二绝缘图案112中的至少一者以连接到互连图案118。在电路层110的底表面上可设置有连接端子400。晶体管115中的至少一者可通过互连结构116电连接到连接端子400中的至少一者。在电路层110的底表面上可设置有保护层113。保护层113可不覆盖连接端子400。保护层113可包含绝缘材料(例如，聚合物)。
在衬底100的第一表面100a上可设置有绝缘层120。绝缘层120可具有沟槽125。沟槽125可从绝缘层120的顶表面120a朝绝缘层120的底表面延伸。沟槽125可在沟槽125的顶表面处具有第一宽度且在沟槽125的底表面处具有第二宽度，使得第一宽度大于第二宽度。绝缘层120可包括有机绝缘层。举例来说，绝缘层120可包含聚合物。聚合物可包括感光性聚合物。聚合物可包括热固性聚合物(thermosetting polymer)。聚合物可包括感光性聚酰亚胺(photosensitive polyimide，PSPI)、聚苯并恶唑(polybenzoxazole，PBO)或苯并环丁烯(benzocyclobutene，BCB)系聚合物中的至少一者。绝缘层120可包含有机材料，且因此可相对柔软。举例来说，绝缘层120可比衬底100、焊盘结构300及通孔结构200中的至少一者柔软。绝缘层120可缓冲或减小对焊盘结构300及通孔结构200施加的应力。在制造半导体器件10的工艺中，衬底100可能发生翘曲(warpage)。绝缘层120的热膨胀系数(thermalexpansion coefficient)可不同于衬底100的热膨胀系数。举例来说，绝缘层120的热膨胀系数可大于衬底100的热膨胀系数。通过对绝缘层120的厚度进行调整，可减小或防止衬底100的翘曲。在下文中，将详细阐述通孔结构200及焊盘结构300。
通孔结构200可穿透衬底100、绝缘层120及焊盘结构300。通孔结构200可从衬底100的第一表面100a突出。通孔结构200的侧壁200c的上部部分可被焊盘结构300环绕。通孔结构200的侧壁200c的下部部分可设置在衬底100中。通孔结构200还可穿透第一绝缘图案111。通孔结构200可通过互连结构116电连接到晶体管115中的至少一者。另外，通孔结构200还可通过互连结构116电连接到连接端子400中的至少一者。
在通孔结构200与衬底100之间以及在通孔结构200与绝缘层120之间可夹置有衬垫层205。衬垫层205可不在通孔结构200与焊盘结构300之间延伸。举例来说，衬垫层205可包含绝缘材料。绝缘材料可包含基于硅的绝缘材料。
通孔结构200可包括阻挡图案210、晶种图案220及导电通孔230。阻挡图案210可设置在衬垫层205上。阻挡图案210可沿通孔结构200的侧壁200c设置。举例来说，阻挡图案210可形成通孔结构200的侧壁200c。阻挡图案210可包含钛(Ti)、氮化钛(TiN)、钽(Ta)及氮化钽(TaN)中的至少一种。晶种图案220可沿阻挡图案210延伸。晶种图案220可包含金属。导电通孔230可设置在晶种图案220上。举例来说，导电通孔230可具有柱形状，且晶种图案220可设置在阻挡图案210与导电通孔230的侧壁之间。阻挡图案210可设置在晶种图案220与衬垫层205之间。导电通孔230可包含金属(例如，铜(Cu)或钨(W))。阻挡图案210、晶种图案220及导电通孔230可在绝缘层120的顶表面120a处暴露出。
焊盘结构300可设置在衬底100的第一表面100a上。如图2A所示，当在平面图中观察时，焊盘结构300可环绕通孔结构200。焊盘结构300的平面形状可并非仅限于图2A所示四边形形状，而是可作出各种修改。通孔结构200可穿透焊盘结构300。焊盘结构300可覆盖通孔结构200的侧壁200c的至少一部分。焊盘结构300可电连接到通孔结构200。焊盘结构300可暴露出通孔结构200。举例来说，焊盘结构300可暴露出通孔结构200的顶表面200a。焊盘结构300的顶表面300a可与通孔结构200的顶表面200a实质上共面。举例来说，焊盘结构300的顶表面300a可与通孔结构200的顶表面200a设置在相同的水平高度或实质上相似的水平高度处。在本公开中，用语“相同的水平高度”及“共面”可将在工艺进行期间可能出现的容差范围考虑在内。
焊盘结构300可设置在绝缘层120中。举例来说，焊盘结构300可设置在绝缘层120的沟槽125中。举例来说，焊盘结构300可嵌置在绝缘层120中。焊盘结构300的顶表面300a可与绝缘层120的顶表面120a实质上共面。举例来说，焊盘结构300的顶表面300a可与绝缘层120的顶表面120a设置在相同的水平高度或实质上相似的水平高度处。焊盘结构300的底表面300b可设置在绝缘层120中。绝缘层120可接触焊盘结构300的侧壁300c以及焊盘结构300的底表面300b。因此，焊盘结构300与绝缘层120之间的接触面积可增大，从而提高焊盘结构300与绝缘层120之间的粘合强度。因此，可减少或防止焊盘结构300从绝缘层120分离的现象，从而提高半导体器件10的可靠性。
焊盘结构300的底表面300b与侧壁300c之间的角度θ1可为钝角。因此，焊盘结构300与绝缘层120之间的接触面积可进一步增大。如果焊盘结构300的底表面300b与侧壁300c之间的角度θ1等于或小于90度，则应力可能集中在焊盘结构300的边缘或隅角中。此处，焊盘结构300的边缘或隅角是指焊盘结构300的底表面300b与焊盘结构300的侧壁300c交会的区。应力可包括物理应力及/或由焊盘结构300的热膨胀系数与绝缘层120的热膨胀系数之差造成的应力。焊盘结构300及绝缘层120中的至少一者可能被应力损坏。举例来说，在焊盘结构300及绝缘层120中的至少一者中可能出现裂纹。然而，根据本发明概念的一些示例性实施例，焊盘结构300的底表面300b与侧壁300c之间的角度θ1可大于90度。因此，应力可不集中在焊盘结构300的边缘或隅角中。因此，半导体器件10的可靠性可得到提高。如果焊盘结构300的底表面300b与侧壁300c之间的角度θ1大于120度，则可能难以形成焊盘结构300。根据本发明概念的一些示例性实施例，焊盘结构300的底表面300b与侧壁300c之间的角度θ1可等于或小于120度。举例来说，焊盘结构300的底表面300b与侧壁300c之间的角度θ1可大于90度且等于或小于120度。
焊盘结构300可包括晶种焊盘310及导电焊盘320。如图2C所示，晶种焊盘310可沿沟槽125的底表面125b及侧壁125c以及通孔结构200的侧壁200c的上部部分延伸。晶种焊盘310可接触通孔结构200(例如，阻挡图案210)。导电焊盘320可设置在晶种焊盘310上。导电焊盘320可填充沟槽125。导电焊盘320可包含金属(例如，铜或铝)。晶种焊盘310的最顶部表面及导电焊盘320的顶表面可在绝缘层120的顶表面120a处暴露出。
图2D是根据本发明概念另一个示例性实施例的沿图2A所示线IIB'-IIB”截取的剖视图。另外，图2D是与图1所示区IIB对应的放大图。在下文中，为容易且方便地进行解释，将省略或仅简要提及对与以上示例性实施例中的元件相同的元件的说明。
参照图1、图2A、及图2D，半导体器件10A可包括衬底100、电路层110、绝缘层120、通孔结构200及焊盘结构300。图2D所示衬底100、电路层110、绝缘层120及焊盘结构300可与以上参照图2B所阐述的衬底100、电路层110、绝缘层120及焊盘结构300相同或实质上相似。图2D所示通孔结构200可与参照图2B阐述的通孔结构200相同或实质上相似。举例来说，通孔结构200可穿透衬底100、绝缘层120及焊盘结构300。然而，根据本示例性实施例的通孔结构200可不设置在电路层110的第一绝缘图案111中，此不同于图2B。
图3A是示出根据本发明概念示例性实施例的半导体器件的平面图。图3B是沿图3A所示线IIIB-IIIB'截取的剖视图。另外，图3B对应于图1所示区IIIB的放大图。在下文中，为容易且方便地进行解释，将省略或仅简要提及对与以上示例性实施例中的元件相同的元件的说明。
参照图1、图3A、及图3B，半导体器件10B可包括衬底100、电路层110、绝缘层120、通孔结构201及202以及焊盘结构300。图3B所示衬底100、电路层110、绝缘层120及焊盘结构300可与参照图2B所阐述的衬底100、电路层110、绝缘层120及焊盘结构300相同或实质上相似。通孔结构201及202可包括多个通孔结构201及202，且焊盘结构300可包括分别对应于通孔结构201及202的多个焊盘结构300。通孔结构201及202中的每一者可穿透衬底100、绝缘层120、焊盘结构300中的每一者及电路层110的第一绝缘图案111。在一些示例性实施例中，如同图2D所示通孔结构200一样，通孔结构201及202可不设置在电路层110的第一绝缘图案111中。
通孔结构201及202可包括彼此间隔开的第一通孔结构201与第二通孔结构202。第一通孔结构201可与参照图1至图2A至图2C阐述的通孔结构200相同或实质上相似。第一通孔结构201可用作连接通孔。举例来说，第一通孔结构201可电连接到晶体管115中的至少一者及/或连接端子400中的至少一者。第一通孔结构201可包括第一阻挡图案211、第一晶种图案221及第一导电通孔231。第二通孔结构202可包括第二阻挡图案212、第二晶种图案222及第二导电通孔232。第一阻挡图案211及第二阻挡图案212可与图1及图2A至图2C所示阻挡图案210相同或实质上相似，第一晶种图案221及第二晶种图案222可与图1及图2A至图2C所示晶种图案220相同或实质上相似，且第一导电通孔231及第二导电通孔232可与图1及图2A至图2C所示导电通孔230相同或实质上相似。然而，第二通孔结构202的形状可不同于第一通孔结构201的形状。举例来说，如图3A所示，第二通孔结构202的平面形状可不同于第一通孔结构201的平面形状。第二通孔结构202可用作对准键(alignment key)。因此，可不在衬底100的第一表面100a上或者绝缘层120的顶表面120a上形成额外对准键。如图3B所示，第二通孔结构202可与晶体管115绝缘。在一些示例性实施例中，第二通孔结构202可通过互连结构116电连接到晶体管115中的至少一者。在这种情形中，第二通孔结构202可用作对准键与电连接通孔二者。
焊盘结构300中的每一者可设置在形成于绝缘层120中的沟槽125中的每一者中。沟槽125可在沟槽125的顶表面处具有第一宽度且在沟槽125的底表面处具有第二宽度，使得第一宽度大于第二宽度。焊盘结构300中的每一者可包括晶种焊盘310及导电焊盘320。焊盘结构300中的一个焊盘结构300可覆盖第一通孔结构201的侧壁且可电连接到第一通孔结构201。焊盘结构300中的另一个焊盘结构300可覆盖第二通孔结构202的侧壁且可电连接到第二通孔结构202。焊盘结构300可不覆盖第一通孔结构201的顶表面201a及第二通孔结构202的顶表面202a。
在下文中将阐述根据本发明概念一些实施例的制造半导体器件的方法。
图4A至图4G是示出根据本发明概念示例性实施例的制造半导体器件的方法的剖视图。在下文中，为容易且方便地进行解释，将省略或仅简要提及对与以上示例性实施例中的技术特征相同的技术特征的说明。另外，为容易且方便地进行解释，将阐述单个焊盘结构及单个连接端子。
参照图4A，可在衬底100的第二表面100b上形成电路层110，且可在衬底100中形成通孔结构200。在一些实施例中，可在衬底100的第二表面100b上形成晶体管115。可在衬底100的第二表面100b上形成第一绝缘图案111以覆盖晶体管115。
可在衬底100及第一绝缘图案111中形成通孔孔洞250。通孔孔洞250可通过使用蚀刻工艺的图案化工艺形成。可在通孔孔洞250的侧壁及底表面上共形地形成衬垫层205。举例来说，衬垫层205可包含氧化硅、氮化硅及氮氧化硅中的至少一种。可在通孔孔洞250中形成通孔结构200。通孔结构200可包括阻挡图案210、晶种图案220及导电通孔230。通孔结构200可通过中段通孔工艺(via-middle process)形成。举例来说，可在形成晶体管115之后形成通孔孔洞250及通孔结构200，如图4A所示。在一些示例性实施例中，通孔结构200可通过先通孔工艺(via-first process)形成。举例来说，通孔孔洞250及通孔结构200可在形成晶体管115及第一绝缘图案111之前形成。在这种情形中，如同图2D所示通孔结构200一样，通孔结构200可不穿透第一绝缘图案111。
可在衬垫层205上形成阻挡图案210。形成通孔结构200可包括在阻挡图案210上形成晶种图案220以及使用晶种图案220作为电极来执行电镀工艺。在电镀工艺期间，可通过使用导电材料填充通孔孔洞250来形成导电通孔230。在形成导电通孔230的工艺中，可能难以使用导电材料完全填充通孔孔洞250。因此，在导电通孔230的端部部分290中可能形成缺陷295(例如，空隙)。此处，导电通孔230的端部部分290可朝向衬底100的第一表面100a。举例来说，导电通孔230的端部部分290可邻近于通孔孔洞250的底表面。例如空气等气体可能占据缺陷295。在一些示例性实施例中，在制造工艺中使用的化学材料的残留物可能余留在缺陷295中。
可在第一绝缘图案111上形成第二绝缘图案112，且可在第一绝缘图案111及第二绝缘图案112中形成互连结构116。由此，可形成电路层110。可在电路层110的底表面上形成连接端子400及保护层113。
参照图4B，可对衬底100的第一表面100a执行薄化工艺。薄化工艺可通过使用蚀刻剂或浆料(slurry)的回蚀工艺(etch-back process)来执行。薄化工艺可对衬底100选择性地执行。在薄化工艺中可不移除衬垫层205及通孔结构200。通孔结构200的端部部分290可从经薄化的衬底100的第一表面100a突出。
参照图4C，可在经薄化的衬底100的第一表面100a上形成绝缘层120。绝缘层120可通过使用例如感光性聚合物涂布经薄化的衬底100的第一表面100a来形成。绝缘层120可包含参照图2A至图2C阐述的材料。
参照图4D，可将绝缘层120图案化以形成初步沟槽126。初步沟槽126可通过使用掩模图案(图中未示出)的光刻工艺形成。可通过初步沟槽126暴露出通孔结构200。通孔结构200的端部部分290可从初步沟槽126突出。初步沟槽126的底表面126b与侧壁126c之间的角度θ2可为约90度。
参照图4E，可将绝缘层120硬化。在将绝缘层120硬化的工艺中，可在绝缘层120中形成沟槽125，且使得沟槽125的顶表面处的第一宽度大于沟槽125的底表面处的第二宽度。沟槽125可从绝缘层120的顶表面120a朝绝缘层120的底表面延伸。绝缘层120可通过热硬化工艺被硬化。热硬化工艺可在高于室温(例如，25摄氏度)的温度下执行。沟槽125可通过初步沟槽126的热流动(thermal flow)来形成。举例来说，绝缘层120的一部分可因硬化工艺中的热而向下流动，且由此可形成沟槽125。沟槽125的底表面125b与侧壁125c之间的角度θ1'可不同于初步沟槽126的底表面126b与侧壁126c之间的角度θ2。在一些示例性实施例中，沟槽125的底表面125b与侧壁125c之间的角度θ1'可大于图4D所示初步沟槽126的底表面126b与侧壁126c之间的角度θ2。沟槽125的底表面125b与侧壁125c之间的角度θ1'可大于90度且等于或小于120度。沟槽125的底表面125b与侧壁125c之间的角度θ1'可实质上等于图2C所示焊盘结构300的底表面300b与侧壁300c之间的角度θ1。通孔结构200可从沟槽125的底表面125b突出。通孔结构200的顶表面200a可设置在比沟槽125的底表面125b的水平高度高的水平高度处。
参照图4F，可移除衬垫层205的一部分以暴露出通孔结构200的侧壁200c的上部部分及通孔结构200的顶表面200a。举例来说，可暴露出通孔结构200的端部部分290。衬垫层205的所述一部分可通过回蚀工艺移除。通孔结构200及绝缘层120可相对于衬垫层205具有蚀刻选择性。可移除设置在沟槽125中的衬垫层205。在移除衬垫层205的所述一部分之后，可在通孔结构200与设置在沟槽125下方的绝缘层120之间以及在通孔结构200与衬底100之间余留衬垫层205。
参照图4G，可在衬底100的第一表面100a上依序形成晶种层311及导电层312。晶种层311可通过沉积工艺形成。晶种层311可沿绝缘层120的顶表面120a、沟槽125的底表面125b及侧壁125c、通孔结构200的侧壁200c的上部部分及通孔结构200的顶表面200a延伸。晶种层311可接触阻挡图案210。可在晶种层311上形成导电层312。导电层312可通过使用晶种层311作为电极进行电镀工艺来形成。导电层312可填充沟槽125。
再次参照图4G，可将晶种层311及导电层312平坦化以形成晶种焊盘310及导电焊盘320。晶种焊盘310及导电焊盘320可形成在沟槽125中。因此，可提供包括晶种焊盘310及导电焊盘320的焊盘结构300。所述平坦化工艺可使用化学机械抛光(chemical mechanicalpolishing，CMP)工艺执行。可通过平坦化工艺移除设置在绝缘层120的顶表面120a上的晶种层311及导电层312。可将绝缘层120与晶种层311及导电层312一同平坦化。绝缘层120的顶表面120a可被暴露出。焊盘结构300可被局限在沟槽125中。焊盘结构300的顶表面300a可与绝缘层120的顶表面120a实质上共面。
可将通孔结构200与晶种层311及导电层312一同平坦化，且因此可移除通孔结构200的一部分。举例来说，可移除通孔结构200的端部部分290。此时，可将缺陷295与通孔结构200的端部部分290一同移除。因此，通孔结构200的电特性及可靠性可得到提高。在平坦化工艺之后，通孔结构200可被焊盘结构300暴露出。平坦化的通孔结构200的顶表面200a可与焊盘结构300的顶表面300a及绝缘层120的顶表面120a实质上共面。由此，可制造出图2B所示半导体器件10。
图4H是沿图2A所示线IIB'-IIB”截取的用于解释根据本发明概念示例性实施例的附加平坦化工艺的剖视图。在下文中，为容易且方便地进行解释，将省略或仅简要提及对与以上实施例中的元件相同的元件的说明。
参照图4G及图4H，可制备包括电路层110、通孔结构200、绝缘层120、晶种层311及导电层312的衬底100。可形成晶种层311及导电层312，如图4G所示。可将导电层312、晶种层311及绝缘层120平坦化以形成焊盘结构300，如图4H所示。可通过平坦化工艺移除通孔结构200的一部分。在平坦化工艺之后，可余留有通孔结构200的端部部分290的缺陷295而形成残留缺陷296，如图4H所示。残留缺陷296可为平坦化的通孔结构200的顶表面200a的凹陷部分。可对残留缺陷296进行检验。举例来说，对残留缺陷的检验可通过测量通孔结构200的顶表面200a的平坦度来执行。由于通孔结构200的顶表面200a被暴露出，因此可容易地检验残留缺陷296。当检测到残留缺陷296时，可执行附加平坦化工艺。
参照图4H及图2B，可通过附加平坦化工艺将残留缺陷296从通孔结构200的顶表面200a移除。可重复进行对残留缺陷296的检验及附加平坦化工艺。附加平坦化工艺可被执行到不再检测到残留缺陷296为止，且因此，通孔结构200的顶表面200a实质上为平坦的。因此，通孔结构200的电特性及可靠性可得到提高。此处，用语‘实质上平坦的顶表面’可将可在平坦化工艺中出现的容差范围考虑在内。
图5A是示出根据本发明概念示例性实施例的半导体封装的剖视图。图5B是图5A所示区V的放大图。在下文中，为容易且方便地进行解释，将省略或仅简要提及对与以上实施例中的元件相同的元件的说明。
参照图5A及图5B，半导体封装1可包括封装衬底1000、第一半导体器件11、第二半导体器件12、第三半导体器件13、第四半导体器件14以及模塑层5000。封装衬底1000可包括印刷电路板(PCB)或再分布层。在封装衬底1000的底表面上可设置有外部端子1001。第一半导体器件、第二半导体器件12及第三半导体器件13中的每一者可与图2A至图2C所示半导体器件10、图2D所示半导体器件10A或图3A及图3B所示半导体器件10B相同。第一半导体器件11、第二半导体器件12及第三半导体器件13可分别包括：第一衬底1100、第二衬底2100及第三衬底3100；第一电路层1110、第二电路层2110及第三电路层3110；第一绝缘层1120、第二绝缘层2120及第三绝缘层3120；第一通孔结构1200、第二通孔结构2200及第三通孔结构3200；以及第一焊盘结构1300、第二焊盘结构2300及第三焊盘结构3300。第四半导体器件14可为最上部半导体器件。第四半导体器件14可包括第四衬底4100及第四电路层4110，但可不包括通孔结构及焊盘结构。然而，本发明概念的示例性实施例并非仅限于半导体封装1中所包括的半导体器件11至半导体器件14的数目。
第一半导体器件11可安装在封装衬底1000上。第一半导体器件11可通过第一连接端子1400电连接到封装衬底1000。第一半导体器件11可通过封装衬底1000电连接到外部端子1001。在第一半导体器件11与封装衬底1000之间可设置有第一粘合膜1500以密封或覆盖第一连接端子1400。第一粘合膜1500可包含绝缘材料。第二半导体器件12可安装在第一半导体器件11上。在第一半导体器件11与第二半导体器件12之间可设置有第二连接端子2400。
第二连接端子2400可为参照图2A及图2B、图2D、图3A及图3B或图4B阐述的连接端子400。举例来说，第二连接端子2400可设置在第二电路层2110的底表面上。第二连接端子2400可包含锡、铅、银及其任意合金中的至少一种。第二半导体器件12可以第二连接端子2400面对第一半导体器件11的方式设置在第一半导体器件11上。在一些示例性实施例中，第一通孔结构1200可包括第一通孔结构1201及第二通孔结构1202。第一通孔结构1201及第二通孔结构1202可分别与参照图3A及图3B阐述的第一通孔结构201及第二通孔结构202相同。举例来说，第二通孔结构1202可用作对准键。第二半导体器件12可使用第二通孔结构1202来与第一半导体器件11对准。在这种情形中，可不在第一衬底1100上形成额外对准键。在一些示例性实施例中，可在第一绝缘层1120或第一衬底1100上独立设置对准键(图中未示出)。在这种情形中，第二半导体器件12可使用对准键(图中未示出)来与第一半导体器件11对准。在这种情形中，可省略第二通孔结构1202。在下文中，将参照图5B更详细地阐述第一半导体器件11与第二半导体器件12之间的电连接。
第二连接端子2400可通过第二电路层2110的第二互连结构2116电连接到第二半导体器件12的第二晶体管2115及第二通孔结构2200中的至少一者。第一焊盘结构1300及第一通孔结构1200可在第一半导体器件11的顶表面处暴露出。第二连接端子2400可通过回焊工艺直接接触第一通孔结构1200及第一焊盘结构1300。第二连接端子2400可通过第一通孔结构1200、第一焊盘结构1300及第一电路层1110的第一互连结构1116电连接到第一半导体器件11的第一晶体管1115中的至少一者。第二连接端子2400可通过第一通孔结构1200电连接到封装衬底1000。因此，第二半导体器件12可电连接到第一半导体器件11及封装衬底1000。
在第一半导体器件11与第二半导体器件12之间可设置有第二粘合膜2500。第二粘合膜2500可环绕第二连接端子2400。第二粘合膜2500可包含绝缘材料。举例来说，第二粘合膜2500可包含环氧系聚合物、聚酰亚胺、聚酯、丙烯酸聚合物及聚砜中的至少一种。第二粘合膜2500可不包含导电粒子。如果第一半导体器件11的顶表面不是实质上平坦的，则可能难以通过第二粘合膜2500来密封第二连接端子2400。举例来说，在第一半导体器件11与第二半导体器件12之间可能形成有空腔(图中未示出)。在半导体封装1中可能因空腔而出现缺陷。然而，根据本发明概念的一些示例性实施例，第一半导体器件11的顶表面可为实质上平坦的。举例来说，第一通孔结构1200的顶表面1200a可设置在与第一焊盘结构1300的顶表面1300a及第一绝缘层1120的顶表面1120a相同的水平高度处或实质上相似的水平高度处。因此，第二粘合膜2500可对第二连接端子2400进行良好的密封。因此，可抑制或防止在第一半导体器件11与第二半导体器件12之间形成空腔。因此，半导体封装1的良率可得到提高。
第一通孔结构1200及第二通孔结构2200可分别包括第一阻挡图案1210及第二阻挡图案2210、第一晶种图案1220及第二晶种图案2220以及第一导电通孔1230及第二导电通孔2230。第一焊盘结构1300及第二焊盘结构2300可分别包括第一晶种焊盘1310及第二晶种焊盘2310以及第一导电焊盘1320及第二导电焊盘2320。
如图5A所示，第二通孔结构2200的顶表面可与第二焊盘结构2300的顶表面以及第二绝缘层2120的顶表面实质上共面。第三连接端子3400可直接接触第二通孔结构2200及第二焊盘结构2300。在第二绝缘层2120的顶表面上可设置有第三粘合膜3500以密封第三连接端子3400。第三通孔结构3200的顶表面可与第三焊盘结构3300的顶表面以及第三绝缘层3120的顶表面实质上共面。第四连接端子4400可直接接触第三通孔结构3200及第三焊盘结构3300。在第三绝缘层3120的顶表面上可设置有第四粘合膜4500以密封第四连接端子4400。第三粘合膜3500及第四粘合膜4500中的每一者可包含作为第二粘合膜2500的实例阐述的材料中的至少一种。模塑层5000可设置在封装衬底1000上以覆盖第一半导体器件11、第二半导体器件12、第三半导体器件13及第四半导体器件14。
根据本发明概念的一些示例性实施例，通孔结构的顶表面及焊盘结构的顶表面可在半导体器件的顶表面处暴露出。连接端子可接触通孔结构及焊盘结构。通孔结构的顶表面可与焊盘结构的顶表面及绝缘层的顶表面实质上共面。因此，可在绝缘层的顶表面上设置有粘合膜以密封连接端子。
绝缘层可缓冲或减小对焊盘结构施加的应力。焊盘结构可嵌置在绝缘层中以提高焊盘结构与绝缘层之间的粘合强度。可对焊盘结构的底表面与侧壁之间的角度进行调整，且因此，应力可不集中在焊盘结构的边缘或隅角中。因此，半导体器件的可靠性可得到提高。
尽管已参照示例性实施例阐述了本发明概念，然而对所属领域中的技术人员来说将显而易见的是，在不背离所公开的示例性实施例的精神及范围的条件下，可作出各种改变及润饰。因此，应理解，以上示例性实施例并非限制性的，而是说明性的。因此，本发明概念的范围应由以上权利要求书及其等效范围所许可的最广范围的解释来确定，而不应受上述说明约束或限制。

Claims (20)

1.一种半导体封装，其特征在于，包括：
第一半导体器件；
第二半导体器件，位于所述第一半导体器件上；以及
焊料球，位于所述第一半导体器件与所述第二半导体器件之间，
其中所述第一半导体器件，包括：
衬底；
绝缘层，位于所述衬底上，所述绝缘层包括沟槽；
至少一个通孔结构，穿透所述衬底且突出在所述沟槽的底表面上方；以及
导电结构，在所述沟槽中环绕所述至少一个通孔结构，且
其中所述通孔结构与所述焊料球直接物理接触。
2.根据权利要求1所述的半导体封装，还包括：
粘合膜，设置于所述第一半导体器件与所述第二半导体器件之间，
其中所述粘合膜环绕所述焊料球且包括绝缘材料。
3.根据权利要求1所述的半导体封装，其中所述绝缘层具有位于所述沟槽之外的第一顶表面、位于所述沟槽的底部处的第二顶表面及连接所述第一顶表面与所述第二顶表面的第三顶表面，所述第一顶表面界定所述沟槽的顶部，且所述第二顶表面位于所述第一顶表面与所述绝缘层的底表面之间。
4.根据权利要求1所述的半导体封装，其中所述沟槽在所述沟槽的顶部处具有第一宽度且在所述沟槽的底部处具有第二宽度，且所述第一宽度大于所述第二宽度。
5.根据权利要求1所述的半导体封装，其中所述至少一个通孔结构与所述导电结构包含同一种金属材料。
6.根据权利要求1所述的半导体封装，还包括：
阻挡图案，沿所述沟槽的第一侧壁、所述沟槽的所述底部及所述沟槽的第二侧壁，所述第一侧壁是位于所述至少一个通孔结构与所述导电结构之间的侧壁，且所述第二侧壁是所述沟槽的位于所述导电结构与所述绝缘层之间的侧壁。
7.根据权利要求6所述的半导体封装，其中所述至少一个通孔结构与所述导电结构包含彼此不同的金属材料。
8.根据权利要求1所述的半导体封装，其中所述绝缘层具有比所述衬底的热膨胀系数大的热膨胀系数。
9.根据权利要求8所述的半导体封装，其中所述绝缘层包括有机绝缘层及聚合物中的至少一种。
10.根据权利要求1所述的半导体封装，其中所述至少一个通孔结构包括连接通孔结构及对准通孔结构，所述对准通孔结构与所述连接通孔结构间隔开，且所述对准通孔结构用作对准键。
11.根据权利要求1所述的半导体封装，其中所述绝缘层的顶表面、所述至少一个通孔结构的顶表面及所述导电结构的顶表面实质上共面。
12.一种半导体封装，其特征在于，包括：
封装衬底；
第一半导体器件，位于所述封装衬底上；
第二半导体器件，与所述封装衬底间隔开，所述第一半导体器件夹置于所述第二半导体器件与所述封装衬底之间；以及
焊料球，位于所述第一半导体器件与所述第二半导体器件之间，
其中所述第一半导体器件，包括：
衬底；
绝缘层，位于所述衬底上，所述绝缘层界定沟槽，所述绝缘层具有位于所述沟槽之外的第一顶表面、位于所述沟槽的底部处的第二顶表面及连接所述第一顶表面与所述第二顶表面的第三顶表面，所述沟槽从所述绝缘层的所述第一顶表面延伸到在垂直方向上位于所述绝缘层的所述第一顶表面与所述绝缘层的底表面之间的点；
至少一个导电通孔结构，穿透所述衬底且突出在所述沟槽的底部上方；以及
至少一个导电结构，在所述沟槽中环绕所述至少一个导电通孔结构，且
其中所述导电通孔结构与所述焊料球直接物理接触。
13.根据权利要求12所述的半导体封装，其中所述绝缘层的所述第一顶表面、所述至少一个导电通孔结构的顶表面及所述至少一个导电结构的顶表面实质上共面。
14.根据权利要求12所述的半导体封装，其中所述沟槽在所述沟槽的顶部处具有第一宽度且在所述沟槽的底部处具有第二宽度，且所述第一宽度大于所述第二宽度。
15.根据权利要求12所述的半导体封装，其中所述至少一个导电通孔结构与所述至少一个导电结构包含同一种金属材料。
16.根据权利要求12所述的半导体封装，还包括：
阻挡图案，沿所述沟槽的第一侧壁、所述沟槽的底部及所述沟槽的第二侧壁，所述第一侧壁是位于所述至少一个导电通孔结构与所述至少一个导电结构之间的侧壁，且所述第二侧壁是所述沟槽的位于所述至少一个导电结构与所述绝缘层之间的侧壁。
17.根据权利要求12所述的半导体封装，其中所述绝缘层具有比所述衬底的热膨胀系数大的热膨胀系数。
18.根据权利要求17所述的半导体封装，其中所述绝缘层包括有机绝缘层及聚合物中的至少一种。
19.一种半导体封装，其特征在于，包括：
封装衬底；
第一半导体器件，位于所述封装衬底上；
第二半导体器件，与所述封装衬底间隔开，所述第一半导体器件夹置于所述第二半导体器件与所述封装衬底之间；以及
焊料球，位于所述第一半导体器件与所述第二半导体器件之间，
其中当在平面图中观察时，所述第一半导体器件包括：
第一金属结构，包含第一金属材料；
阻挡金属图案，环绕所述第一金属结构；以及
导电结构，环绕所述阻挡金属图案，所述导电结构包含第二金属材料；以及
绝缘层，环绕所述导电结构，且
其中所述第一金属结构与所述焊料球直接物理接触。
20.根据权利要求19所述的半导体封装，还包括：
用于所述第一金属结构的晶种图案，沿所述阻挡金属图案的内侧壁。
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US20200273723A1 (en) 2020-08-27
KR20180121737A (ko) 2018-11-08
TW201842644A (zh) 2018-12-01
US10211070B2 (en) 2019-02-19
US11574819B2 (en) 2023-02-07
US20180315620A1 (en) 2018-11-01
US10937667B2 (en) 2021-03-02
KR102406573B1 (ko) 2022-06-09
US10699915B2 (en) 2020-06-30
TWI746776B (zh) 2021-11-21
US20190139785A1 (en) 2019-05-09
US20210183663A1 (en) 2021-06-17

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