CN101656197A - 硅通孔键合结构 - Google Patents

硅通孔键合结构 Download PDF

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CN101656197A
CN101656197A CN200910000421A CN200910000421A CN101656197A CN 101656197 A CN101656197 A CN 101656197A CN 200910000421 A CN200910000421 A CN 200910000421A CN 200910000421 A CN200910000421 A CN 200910000421A CN 101656197 A CN101656197 A CN 101656197A
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substrate
transition zone
protective layer
contact
silicon
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王宗鼎
陈承先
卿恺明
李柏毅
李建勋
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提出了键合半导体衬底的系统和方法。优选的实施例包括在半导体衬底的表面之上形成过渡层，同时为了防止可能形成的潜在的空隙，保留从过渡层突出的TSV。在将被键合到第一半导体衬底的另一个半导体衬底上形成保护层。两个衬底被对准并键合到一起，并且过渡层防止与初始半导体衬底的表面发生任何短路接触。

Description

硅通孔键合结构
技术领域
本发明一般涉及键合半导体结构的系统和方法，更具体地，涉及使用硅通孔将一个半导体结构键合到另一个半导体结构的系统和方法。
背景技术
图1示出了将第一半导体结构101键合到第二半导体结构103上的方法。第一半导体结构101包括硅通孔105，其从第一半导体结构101的一个表面延伸到第一半导体结构101的另一个表面。第二半导体结构103包括覆盖在凸点下金属化层(UBM)109上的接触凸点107，其提供第一半导体结构101上的硅通孔105与第二半导体结构103之间的电接触。
在键合过程中，不流动胶(NFU)111代表性地置于第一半导体结构101上。一旦NFU111处于适当的位置，第一半导体结构101和第二半导体结构103与对准相应的接触凸点107的硅通孔105发生接触以建立第一半导体结构101和第二半导体结构103之间的电接触。在上述结构已经对准和发生接触之后，代表性地进行回流以回流接触凸点107，形成与硅通孔105更好的接触。
然而，如果NFU111被使用，第一半导体结构101邻近硅通孔105的表面可能被暴露。当这种情况发生时，在回流过程中，接触凸点107的材料(例如，焊料)可能流动到开口内，并在接触凸点107和第一半导体结构101之间建立如标号113所指示的短路路径。这将导致第一半导体结构101和第二半导体结构103的缺陷，或者甚至整个器件故障。
因此，需要一种保护半导体结构的表面避免产生可能导致短路的空隙的方法。
发明内容
本发明的使两个半导体衬底彼此连接的优选的实施例，普遍解决或避开了上述以及其他的问题，并且普遍达到了技术效果。
根据本发明的一个优选的实施例，一种半导体结构包括第一衬底和第二衬底。第一衬底包括第一侧面和与第一侧面相对的第二侧面，位于衬底的第二侧面之上的过渡层，延伸穿过过渡层的硅通孔。第二衬底包括位于第二衬底和过渡层之间的保护层，以及延伸穿过保护层并与硅通孔接触的接触点。
根据本发明的另一个优选的实施例，一种半导体结构包括第一衬底和位于第一衬底之上的第二衬底。过渡层位于第一衬底和第二衬底之间，保护层位于过渡层和第二衬底之间。导体延伸穿过第一衬底并穿过过渡层，接触凸点位于第一衬底和第二衬底之间并与硅通孔接触。
根据本发明的又一个优选的实施例，一种半导体结构包括第一衬底，其具有在第一衬底的第一表面上的接触凸点。保护层位于第一衬底的第一表面之上，其中接触凸点基本被保护层暴露，过渡层位于保护层之上。第二衬底位于过渡层之上，第二衬底包括面对第一衬底的第二表面和背对第二衬底的第三表面，硅通孔从第三表面延伸到接触凸点。
本发明的实施例的一项有益效果为减少了接触凸点延伸穿过键合材料内的空隙的能力，以及衬底表面发生短路的能力。因此，整体结构将有较少的损坏，并且提高了可用器件的成品率。
附图说明
为了更加全面的理解示出的实施例及其有益效果，以下结合附图进行说明，其中：
图1为现有技术中键合两个半导体衬底的示意图；以及
图2-6为根据本发明的实施例使用硅通孔接合两个半导体衬底的示意图。
不同的附图中的相应的数字和标号除非另有说明外一般指示相应的部分。附图绘制仅为清楚地示出优选的实施例的相关方面，并不必需按照比例绘制。
具体实施方式
下面详细讨论本发明优选的实施例的制造和使用。应当理解的是，无论如何，示出的实施例提供了很多可在广泛多种场景中实施的适用的发明构思。所讨论的特定的实施例仅是制造和使用本发明的特定方式，并不是对本发明的范围的限制。
本发明在特定的环境中将参考示出的实施例进行描述，也就是使用硅通孔将一个半导体管芯键合到另一个半导体管芯上。然而，本发明也可以应用到其他键合工艺中。
参考图2，示出了第一半导体衬底201，其具有形成在其上的UBM203和接触凸点205。第一半导体衬底201优选地半导体管芯，其包括具有形成在其中和/或其上的电子器件的衬底，并且，优选但并不必需的，也包括电介质和导电层以提供电子器件之间的连接和布线(图2中全部通过衬里207表示)。位于第一半导体衬底201上可以具有任意数量的导电和电介质层的交互层，但是代表性的层的范围可以为三层到十二层交互的导电和电介质层。
可选择的，第一半导体衬底201可以包括半导体晶片以提供晶片-晶片或晶片-管芯键合。在本实施例中，半导体晶片优选地包括多个半导体管芯，每个管芯优选地包括：衬底，形成在衬底其中和/或其上的有源器件，以及多个电介质和导电层。在本实施例中，独立的半导体管芯优选地形成在单一的半导体晶片上，并且虑及同时处理所有独立管芯的优选的方法，独立的管芯没有从半导体晶片上分离。
在第一半导体衬底201的一个表面上设置UBM203。为了提供导电层和器件与形成在UBM203之上的接触凸点205(下面进一步描述)之间的电连接，UBM203优选地连接到相应的一个导电层和器件207。UBM203优选地由至少三层导电材料形成，如一层铬、一层铬铜合金、一层铜，可选择的在铜层的顶层之上具有金层。然而，本领域的普通技术人员可以得知材料和层具有很多适合的排列，如钛/钛钨/铜的排列或铜/镍/金的排列，适合UBM203的结构。可以用于UBM203的任何合适的材料或材料的层都包括在本申请的范围内。
UBM203优选地通过一致的在第一半导体衬底201的表面之上形成每个层而形成。每个层的形成优选地使用CVD工艺如PECVD来完成，然而其它形成工艺，如溅射或蒸发，可根据所需的材料选择使用。UBM203内的每个层优选地具有介于大约2μm到大约15μm之间的厚度。一旦所需的层被形成，该层的部分被去除，优选地通过适合的光刻掩膜和刻蚀工艺以去除不想要的材料并保留构图的UBM203。
接触凸点205优选地形成在UBM203之上，并优选地包括材料如锡或其它适当的金属，如银或铜。在一个实施例中，接触凸点205为锡焊料凸点，接触凸点205可以由通过常用方法如蒸发、电镀、印刷、焊料迁移、植球等等初始形成锡层，到大约100μm的优选厚度而形成。一旦在结构上已经形成锡层，优选地进行回流以使材料形成期望的凸点形状。
图3示出了在第一半导体衬底201的表面之上的保护层301的形成和构图。保护层301优选地由如聚酰亚胺(PI)、苯并环丁烯(BCB)、二氧化硅、氮化硅、环氧树脂或其组合物等材料而形成。保护层301优选地通过化学汽相淀积(CVD)工艺形成，然而其它适当的工艺，如等离子体增强化学汽相淀积(PECVD)，或低压化学汽相淀积(LPCVD)，可以根据所使用的特定材料选择使用。保护层301优选形成地从第一半导体衬底的表面具有大约3μm到大约20μm之间的厚度，优选地大约10μm的厚度。
优选地，一旦保护层301已经在第一半导体衬底201之上(也在接触凸点205之上)形成，保护层301就被构图以暴露接触凸点205。构图优选地通过合适的光刻工艺完成，从而形成光致抗蚀剂(未示出)、暴光并显影以暴露保护层301的某些部分同时保护其它部分。然后优选进行刻蚀工艺，如反应离子刻蚀(RIE)，以去除保护层301的暴露部分并基本上暴露接触凸点205。然而，尽管列举的方法为对保护层301构图的优选方法，但是可以选择使用其它适合的方法，如光刻形成硬掩膜，对保护层301构图的所有适合的方法都包括在本发明的范围中。
图4示出了第二半导体衬底401，其最终将被键合到第一半导体衬底201(以下参考图6进行描述)。第二半导体衬底401类似于第一半导体衬底201，它可以是半导体管芯或半导体晶片，也优选地具有形成在其中或其上的有源器件和用于布线和连接的交互的电介质和导电层(图4中全部用线路403表示)。有源器件和交互的电介质和导电层403优选地位于第二半导体衬底401的第一侧面402上，第二侧面404优选地不具有有源器件以及电介质和导电层。
优选地，第二半导体衬底401还包括一个或多个TSV405。TSV405可以通过刻蚀部分地穿过第二半导体衬底401和衬里407的通孔而形成，如阻挡层，优选地形成在如氧化物、氮化物等等的电介质的通孔中。导电材料优选地淀积到通孔内，之后，衬底的第二侧面404可以被减薄以暴露第二半导体衬底401的第二侧面404上的TSV405。优选的，在暴露导电材料之后，第二半导体衬底401和衬里407至少部分在第二半导体衬底401的第二侧面404上被刻蚀，不刻蚀导电材料，这样导电材料至少部分从第二半导体衬底401和衬里407突出。
在另一项技术中，TSV405可以通过刻蚀部分地穿过第二半导体衬底401的通孔和在通孔中淀积电介质层而形成。然后第二半导体衬底401的第二侧面404与通孔内的电介质层一起优选地被减薄。在第二侧面404被减薄之后，保留在通孔内的电介质被去除，具有或不具有衬里407的导电材料，在通孔内被再淀积。
TSV405可以使用导电材料如Al、Cu、其它金属、合金、掺杂多晶硅或其组合物等等填充。优选的，TSV405使用金属填充。TSV405优选地连接到至少一些有源器件和交互的电介质和导电层403，这样将有源器件和交互的电介质和导电层403电连接到TSV405和第二半导体衬底401的第二侧面404上。
图5示出了在第二半导体衬底401的第二侧面404之上的过渡层501的形成。过渡层501，与第一半导体衬底201上的保护层301类似，优选地由如PI、BCB、二氧化硅、氮化硅、环氧树脂或其组合物等等材料形成。过渡层501优选地通过如旋涂或分层工艺而形成，然而也可以选择使用其它适合的印刷方法。
优选的，过渡层501和保护层301包括相同的材料。具有相同的材料将增加过渡层501和保护层301的粘附，导致更强的键合。然而，过渡层501和保护层301可以选择性的由两种不同的材料制成，或甚至材料的组合，只要所述材料能够彼此键合。
一旦形成在第二半导体衬底401的第二侧面404之上，过渡层501优选被构图，这样TSV405从过渡层501突出，并不暴露半导体衬底的第二侧面404。过渡层501优选地通过适合的光刻掩膜层(未示出)来构图，然后被刻蚀以暴露TSV405，这样TSV405从过渡层501突出。优选的，TSV405从过渡层501突出的距离介于1μm到大约20μm之间，优选距离为大约10μm。
通过在第二半导体衬底401的第二侧面404之上形成过渡层501，第二半导体衬底401的表面优选地与进一步的接触隔离。该隔离防止了任何材料如接触凸点205中的材料接触第二半导体衬底401的第二侧面404，以及潜在地形成可以导致破坏的短路。
图6示出了将第一半导体衬底201键合到第二半导体衬底401上。为了将第一半导体衬底201键合到第二半导体衬底401上，衬底彼此对准，这样TSV405对准接触凸点205，这样保护层301和过渡层501互相面对。
一旦对准，第一半导体衬底201和第二半导体衬底401优选地使用如热压键合工艺互相键合，然而也可以选择使用其它工艺如倒装芯片键合或金属扩散键合。同时所使用的精确的参数将至少部分地基于在包括在小于大约100MPa的压力，优选使用30MPa的压力条件下，热压键合的工艺中，用于保护层301和过渡层501所选择的材料。另外，低压键合，优选使用介于大约180℃到大约400℃之间的温度，优选地大约250℃的温度，然而也可以选择使用其它合适的温度。
在第一半导体衬底201和第二半导体衬底401已经被键合到一起之后，为了增强与TSV405的接触，优选进行回流以回流接触凸点205。然而，具有介于接触凸点205的材料之间的过渡层501，暴露第二半导体衬底401的第二侧面404的空隙如果没有一起去除，数目大大减少了。因此，由于接触凸点之间的无意的短路接触而造成的损害大大减少了。
在热压键合之后，保护层301和过渡层501为了增加它们的硬度和对损害的抵抗力，优选地在恒温器中被固化。固化优选地在介于大约150℃到大约350℃之间的温度进行，优选地大约250℃的温度。另外，固化优选地进行大约30分钟到大约4小时的时间，优选地固化大约1小时的时间。
在本发明的另一个实施例中，在将第一半导体衬底201键合到第二半导体衬底401之前，保护层301和/或过渡层501可以通过一个或多个固化工艺被部分固化。通过部分固化这些层中的一个或两个，用于保护层301和过渡层501的材料的粘度下降了，使得材料更好流动，并且使键合工艺更有效。优选的，材料被固化到全部固化的大约70％到大约90％，优选部分固化大约80％。如果在键合之前使用部分固化，优选地在键合到全部固化材料之前进行一次或多次固化。
尽管详细描述了示出的实施例及其有益效果，但是应当理解的是，在不偏离限定在附加的权利要求中的本发明的精神和范围的情况下，可以做出各种变化、替代和改造。例如，第一半导体衬底和第二半导体衬底也可以是半导体管芯或其它半导体晶片。
此外，本申请的保护范围不限于本说明书中描述的工艺、设备、制造、物质的组成、装置、方法和步骤的具体实施例。由于本领域的普通技术人员将很容易从本发明所公开的内容得到启示，因此根据本发明的内容，目前存在的或之后开发出的、与这里所描述的相关实施例发挥基本相同的作用或达到基本相同的效果的工艺、机器、制造、物质的成分、装置、方法或步骤可能被利用。因此，所附的权利要求目的在于把工艺、机器、制造、物质的成分、装置、方法或步骤包括在其范围之内。

Claims (15)

1、一种连接两个半导体晶片的方法，所述方法包括：
提供第一衬底，包括：
第一侧面以及与所述第一侧面相对的第二侧面；
穿过所述第一衬底并从所述第一衬底的第二侧面突出的硅通孔；
位于所述第一衬底的第二侧面之上的过渡层；
提供具有第三侧面的第二衬底，所述第二衬底包括：
位于所述第二衬底的第三侧面上的接触点；
位于所述第二衬底的第三侧面之上的保护层；
使所述过渡层接触所述保护层，这样所述硅通孔以及所述接触点彼此对准；以及
将所述第一衬底键合到所述第二衬底上。
2、根据权利要求1所述方法，其中所述过渡层和所述保护层包括不同的材料。
3、根据权利要求1所述方法，还包括：
在使所述过渡层接触所述保护层之前，部分固化所述过渡层和所述保护层；以及
在将所述第一衬底键合到第二衬底上之后，完全固化所述过渡层和所述保护层。
4、根据权利要求1所述方法，还包括在使所述过渡层接触所述保护层之后，回流所述接触点。
5、一种接合两个半导体衬底的方法，所述方法包括：
提供第一衬底，其具有第一表面和与所述第一表面相对的第二表面；
形成穿过所述第一衬底在所述第一表面之间延伸到所述第二表面的开口；
在所述开口内形成导体，并从所述第一衬底的第二表面突出；
在所述第一衬底的第二表面之上形成过渡层，所述导体从所述过渡层突出；
提供具有第三表面的第二衬底；
在所述第三表面上形成接触凸点；
在所述第三表面之上形成保护层，这样所述接触凸点基本上被暴露；
对准所述接触凸点和所述导体，这样所述过渡层与所述保护层相接触，并且所述接触凸点与所述导体相接触；以及
将所述保护层键合到所述过渡层。
6、根据权利要求5所述方法，还包括在形成导体之前，在所述开口内形成衬里。
7、根据权利要求5所述方法，还包括在对准所述接触凸点和所述导体之后，回流所述接触凸点。
8、根据权利要求5所述方法，还包括在将所述保护层键合到所述过渡层之前，部分固化所述过渡层。
9、根据权利要求3或8所述方法，其中所述过渡层被部分固化到全部固化的大约70％到90％。
10、根据权利要求5所述方法，其中所述过渡层包括苯并环丁烯或聚酰亚胺。
11、一种使两个半导体衬底附着的方法，所述方法包括：
提供第一衬底和第二衬底，所述第一衬底包括从第一侧面延伸并从与第一侧面相对的第二侧面突出的硅通孔，所述第二衬底包括第三侧面上的接触点；
在所述第二衬底的第三侧面之上形成保护层；
在所述第一衬底的第二侧面之上形成过渡层，所述硅通孔从所述过渡层突出；
使所述过渡层接触所述保护层，所述硅通孔接触所述接触点；
将所述过渡层键合到所述保护层；以及
在所述硅通孔之上回流所述接触点。
12、根据权利要求11所述方法，还包括在使所述过渡层接触所述保护层之前，部分固化所述保护层。
13、根据权利要求12所述方法，其中部分固化所述保护层继续进行直到所述保护层至少70％被固化。
14、根据权利要求1、5或11任一项所述方法，其中所述键合至少部分通过热压键合完成。
15、根据权利要求14所述方法，其中所述热压键合至少部分在介于大约150℃到大约400℃之间的温度进行。
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