TWI702658B - 具有ｒｄｌ中介層的三維ｉｃ封裝與相關方法 - Google Patents

具有ｒｄｌ中介層的三維ｉｃ封裝與相關方法 Download PDF

Info

Publication number
TWI702658B
TWI702658B TW107147434A TW107147434A TWI702658B TW I702658 B TWI702658 B TW I702658B TW 107147434 A TW107147434 A TW 107147434A TW 107147434 A TW107147434 A TW 107147434A TW I702658 B TWI702658 B TW I702658B
Authority
TW
Taiwan
Prior art keywords
bottom die
rdl
interconnect
die
interposer
Prior art date
Application number
TW107147434A
Other languages
English (en)
Other versions
TW201941313A (zh
Inventor
路克Ｇ 英格蘭
Original Assignee
美商格芯（美國）集成電路科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商格芯（美國）集成電路科技有限公司 filed Critical 美商格芯（美國）集成電路科技有限公司
Publication of TW201941313A publication Critical patent/TW201941313A/zh
Application granted granted Critical
Publication of TWI702658B publication Critical patent/TWI702658B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/89—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/03002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0341—Manufacturing methods by blanket deposition of the material of the bonding area in liquid form
    • H01L2224/03416—Spin coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/03452—Chemical vapour deposition [CVD], e.g. laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/035—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0383—Reworking, e.g. shaping
    • H01L2224/03845—Chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/05576—Plural external layers being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80003—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/80006—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
    • H01L2224/80013—Plasma cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/802—Applying energy for connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80905—Combinations of bonding methods provided for in at least two different groups from H01L2224/808 - H01L2224/80904
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80909—Post-treatment of the bonding area
    • H01L2224/80948—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/381—Pitch distance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

3D IC封裝包含具有與一前裝置側相對的一後互連側的一底部晶粒，後互連側具有向其延伸的複數個底部晶粒互連。頂部晶粒具有與一後側相對的一前裝置側，前裝置側具有複數個頂部晶粒互連。中介層包含在底部晶粒及頂部晶粒之間的再分佈層(RDL)，RDL包含從其後側RDL互連延伸至其前側RDL互連的複數個佈線層。凸塊下金屬化(UBM)在第一位置處將後側RDL互連耦合至複數個頂部晶粒互連，前側RDL互連在第二位置處耦合至複數個底部晶粒互連。第一位置與第二位置不部分重疊。

Description

具有RDL中介層的三維IC封裝與相關方法
本發明關於積體電路(IC)封裝，更特別地，本發明關於具有中介層的三維(3D)IC封裝，該中介層包含頂部和底部IC晶粒之間的再分佈層，以及關於用以形成該IC封裝的相關方法。
積體電路(IC)在半導體工廠中的前段製程(FEOL)期間形成於半導體晶圓中，即直到IC裝置上的第一金屬化層。後段製程(BEOL)處理為在第一次金屬化後的裝置製造過程中在半導體晶圓上執行的任何處理，例如，擴大用於與其他裝置互連的佈線。
3D IC封裝通常藉由以某些在其間的互連將IC頂部晶粒的前側電耦合至到IC底部晶粒的後側而形成。底部晶粒/晶圓的後側上的佈線層(其通過該底部晶粒而連接至半導體通孔(TSV)連接)限於具有約8至10微米的線-空間尺寸的佈線。此限制係基於微影處理能力，而薄底部晶圓面朝下安裝在臨時處理晶圓上，作為三維半導體通孔(3D/TSV)互連處理的一部分。臨時處理晶圓上的薄晶圓的翹曲阻礙了高解析度微影成像。另外，經由底部晶粒/晶圓到後側佈線的TSV連接的間距受到此佈線層的最小線-空間尺寸的限制。在許多情況下，底部晶粒的TSV互連必須耦合的頂部晶粒的前側上的微柱互連的間距要求(例如約30至40微米)驅動底部晶粒的TSV放置間距。較大間距的TSV放置消耗了無法用於其他電路的較大量面積，由於 先進節點邏輯晶圓的高成本，這是不希望的。針對底部晶粒的後側佈線層的當前8微米至10微米的線-空間限制僅允許TSV覆蓋區的部分收縮。為了完全降低TSV覆蓋區的影響，需要1微米或更小的線-空間。
在後側佈線處理期間為底部晶粒產生較小佈線尺寸的一方法為將其上具有載體晶圓的晶圓重新引入製造IC的晶圓廠中，然後形成另外的、較小的佈線層。然而，此方法在後勤上具有挑戰性，因為當前的IC製造工具沒有組態以處理臨時載體晶圓，且那些工具通常位於具有更高等級的粒子和其他污染限制的清潔區域中。配合IC晶粒的另一挑戰是希望在晶粒之間產生更多數量的互連。有可能在小區域內產生更多數量的TSV連接到底部晶粒的後側以增加連接數量，但目前無法擴大(扇出)TSV以與頂部晶粒上的當前微柱間距配合。當前3D IC封裝的另一個挑戰是兩個晶粒的互連必須以對齊或部分重疊(overlap)的方式配合。
本發明的第一態樣關於用以形成三維(3D)積體電路(IC)封裝的方法，方法包含：提供包含複數個IC底部晶粒於其中的一IC底部晶粒晶圓，每一IC底部晶粒具有與一前裝置側相對的一後互連側，後互連側具有由一後側介電層圍繞的複數個暴露的底部晶粒互連；將第一載體耦合至IC底部晶粒晶圓的前裝置側；針對在IC底部晶粒晶圓中的每一IC底部晶粒產生包含再分佈層(RDL)的中介層，中介層具有前側、後側及耦合至其後側的第二載體，RDL包含複數個佈線層，佈線層從中介層的後側上的後側RDL互連延伸至中介層的前側上的前側RDL互連；將中介層的前側混合接合至IC底部晶粒晶圓的後側，其中針對每一相應的IC底部晶粒，前側RDL互連的至少一部分在相應的IC底部晶粒的一第一位置處操作地耦合至相應的IC底部晶粒的複數個暴露的底部晶粒互連；從中介層移除第二載體，在第二位置處暴露後側RDL互連；在第二位置處的暴露的後側RDL互連上形成一 凸塊下金屬化(UBM)；移除第一載體並將IC底部晶粒晶圓與中介層切割成複數個IC底部晶粒，每一IC底部晶粒包含中介層的一相應RDL和一相應UBM；提供包含複數個頂部晶粒互連的一IC頂部晶粒；以及藉由將IC頂部晶粒的複數個頂部晶粒互連耦合至在一選定IC底部晶粒上的UBM來形成3D IC封裝。
本發明的第二態樣關於三維(3D)積體電路(IC)封裝，包含：具有與前裝置側相對的後互連側的IC底部晶粒，後互連側具有向其延伸的複數個底部晶粒互連；具有與後側相對的前裝置側的IC頂部晶粒，前裝置側具有複數個頂部晶粒互連；在IC底部晶粒及IC頂部晶粒之間包含再分佈層(RDL)的中介層，RDL包含從其後側RDL互連延伸至其前側RDL互連的複數個佈線層；一凸塊下金屬化(UBM)，其在第一位置處將後側RDL互連耦合至複數個頂部晶粒互連，以及其中前側RDL互連在第二位置處耦合至複數個底部晶粒互連。
本發明的第三態樣關於三維(3D)積體電路(IC)封裝，包含：具有與前裝置側相對的後互連側的IC底部晶粒，後互連側具有暴露於其中的複數個半導體通孔(TSV)；具有前裝置側的IC頂部晶粒，前裝置側具有暴露於其中的複數個微柱；在IC底部晶粒及IC頂部晶粒之間包含一再分佈層(RDL)的一中介層，RDL包含從其後側RDL互連延伸至其前側RDL互連的複數個佈線層；以及一凸塊下金屬化(UBM)，其在第一位置處將後側RDL互連耦合至複數個頂部晶粒互連，其中前側RDL互連在第二位置處耦合至複數個底部晶粒互連，以及其中後側RDL互連具有比前側RDL互連更大的間距。
由以下對本發明具體實施例的更具體描述將更清楚本發明的前述和其他特徵。
100:3D IC封裝
102:IC底部晶粒晶圓
104:IC底部晶粒
106:基板層
110:後互連側
112:前裝置側
120:底部晶粒互連
120’:底部晶粒互連
122:後側介電層
124:底部晶粒互連
126:BEOL互連部分
128:後側半導體層
130:底部晶粒互連
131:半導體通孔
140:第一載體
142:黏著劑
144:焊墊層
146:焊墊
150:中介層
152:再分佈層
154:前側
156:後側
158:第二載體
160:後側RDL互連
162:前側RDL互連
164:介電層
170:第一位置
172:銅-氧化物層
176:電漿激活
178:退火
180:第二位置
184:凸塊下金屬化
190:頂部晶粒
192:頂部晶粒互連
198:受控塌陷晶片連接層
200:球柵陣列層疊板
202:焊球
210:前裝置側
212:後側
將參考以下附圖詳細描述本發明的具體實施例，其中類似的符號表示類似的元件，其中：圖1顯示根據本發明具體實施例的用以製造3D IC封裝的方法的一或多個步驟的剖面圖；圖2顯示根據本發明具體實施例的用以製造3D IC封裝的方法的一或多個步驟的剖面圖；圖3顯示根據本發明具體實施例的用以製造3D IC封裝的方法的一或多個步驟的剖面圖；圖4顯示根據本發明具體實施例的用以製造3D IC封裝的方法的一或多個步驟的剖面圖；圖5顯示根據本發明具體實施例的用以製造3D IC封裝的方法的一或多個步驟的剖面圖；圖6顯示根據本發明具體實施例的用以製造3D IC封裝的方法的一或多個步驟的剖面圖；圖7顯示根據本發明具體實施例的用以製造3D IC封裝的方法的一或多個步驟的剖面圖；圖8顯示根據本發明具體實施例的用以製造3D IC封裝的方法的一或多個步驟的剖面圖；圖9顯示根據本發明具體實施例的用以製造3D IC封裝的方法的一或多個步驟的剖面圖；圖10顯示根據本發明具體實施例的用以製造3D IC封裝的方法的一或多個步驟的剖面圖；圖11顯示根據本發明具體實施例的用以製造3D IC封裝的方法的一或多個步驟的剖面圖；圖12顯示根據本發明具體實施例的用以製造3D IC封裝的方法的一或多個步驟的剖面圖； 圖13顯示根據本發明具體實施例的用以製造3D IC封裝的方法的一或多個步驟及如此而形成的3D IC封裝的剖面圖；圖14顯示根據本發明具體實施例的3D IC封裝的示意俯視圖；以及圖15顯示根據本發明其他具體實施例的3D IC封裝的示意俯視圖；應注意到本發明的附圖並未按比例繪製。附圖旨在僅繪示本發明的典型態樣，因此不應視為限制本發明的範疇。在附圖中，類似的元件符號表示附圖之間的類似元件。
本發明的具體實施例提供3D IC封裝。底部晶粒具有與前裝置側相對的後互連側，後互連側具有複數個底部晶粒互連，例如延伸到其中的半導體通孔(TSV)。頂部晶粒具有與後側相對的前裝置側，前裝置側具有複數個頂部晶粒互連，例如微柱。3D IC封裝包含底部和頂部晶粒，它們兩個的前裝置側面向相同方向，例如向下。這種配置與傳統封裝形成對比，傳統封裝具有彼此面對的前裝置側，其以粗間距銅柱連接。3D IC封裝也包含中介層，其包含在底部晶粒和頂部晶粒之間的再分佈層(RDL)。RDL包含從其後側RDL互連延伸到其前側RDL互連的複數個佈線層。凸塊下金屬化(UBM)在第一位置處將後側RDL互連耦合到複數個頂部晶粒互連，且前側RDL互連在第二位置處耦合至複數個底部晶粒互連。前側RDL互連可具有與後側RDL連接不同的間距或數量。因此，RDL允許底部晶粒TSV的路由和扇出，而不管它們的數量或間距，以幾乎可適應頂部晶粒上任何的微柱配置。形成3D IC封裝的方法的具體實施例不需要將部件重新引入到晶圓廠中。此外，互連的第一位置和第二位置可不部分重疊。因此，如將要描述的，封裝可在兩個晶粒之間以對齊之外的方式適應互連的定位，這除了其 他益處之外還允許整體佔用空間的潛在降低。
參照圖1到圖13，將描述根據本發明的具體實施例的形成3D IC封裝100(圖13)的方法。每一圖式顯示了程序的一或多個步驟的剖面圖。
圖1到圖6顯示提供一IC底部晶粒晶圓102，其包含了複數個IC底部晶粒104於其中。IC底部晶粒104的最終分離位置由虛線顯示。每一IC底部晶粒104具有與前裝置側112相對的後互連側110。每一IC底部晶粒104可包含任何現在已知或以後將開發的互補金屬氧化物半導體(CMOS)裝置。前裝置側112可包含任何現在已知或以後將開發的CMOS裝置。如圖5和圖6所示，提供IC底部晶粒晶圓102，使得後互連側110具有由後側介電層122圍繞的複數個暴露的底部晶粒互連120。後側介電層122可包含適用於混合接合的任何無機介電質(例如氧化物)，如本文將進一步描述的。如將進一步描述的，最終形成暴露的底部晶粒互連120的底部晶粒互連可有變化。在圖5的示例中，暴露的底部晶粒互連120為半導體通孔(TSV)。從描述中可明顯看出，它們可採用其他形式，例如規則排列的通孔，金屬線等。
參考圖1，IC底部晶粒晶圓102可使用任何現在已知的或以將後開發的技術來製造，例如微影。如本領域所理解的，前裝置側112包含其中的IC底部晶粒104的主動裝置，例如電晶體、電阻器、電容器等。這些裝置(未示出)非常小(例如奈米)且位於IC底部晶粒晶圓102的最外面的基板層106中，如圖1所示。基板層106(僅示於圖1)可包含但不限於矽、鍺、矽鍺、碳化矽、及主要由一或多種III-V族化合物半導體所組成者，其具有由化學式AlX1GaX2InX3AsY1PY2NY3SbY4所定義的成分，其中X1、X2、X3、Y1、Y2、Y3及Y4代表相對比例，其每一者大於或等於零且X1+X2+X3+Y1+Y2+Y3+Y4=1(1為總相對摩爾量)。其他合適的基板包含具有成分ZnA1CdA2SeB1TeB22的II-VI化合物半導體，其中A1、A2、B1及B2為相對比例，其每一者大於或等於零且A1+A2+B1+B2=1(1為總摩爾量)。
後互連側110可具有在其中的多個不同層中的各種底部晶 粒互連124。在所示的示例中，後互連側110可包含後段製程(BEOL)互連部分126，其包含使用任何現在已知的或以後將開發的製程(例如鑲嵌或雙鑲嵌製程)在介電層(未單獨標記)中形成的任何數量的傳統BEOL金屬層和通孔層(未單獨標記)。BEOL互連部分126以傳統方式耦合到每一IC底部晶粒104中的前裝置側112中的裝置。BEOL互連部分126的介電層(未單獨標記)可包含但不限於：氮化矽(Si3N4)、氧化矽(SiO2)、氟化SiO2(FSG)、氫化碳氧化矽(SiCOH)、多孔SiCOH、硼-磷-矽酸鹽玻璃(BPSG)、半矽氧烷、包含矽(Si)、碳(C)、氧(O)及/或氫(H)原子的碳(C)摻雜氧化物(即有機矽酸鹽)、熱固性聚亞芳基醚、SiLK(可從Dow Chemical公司獲得的聚亞芳基醚)、可從JSR公司獲得的旋塗含矽-碳的聚合物材料、其他低介電常數(<3.9)材料或其層。在BEOL互連部分126中形成金屬或通孔層的導體可包含例如銅或鋁，其具有需要的任何合適的襯層，例如氮化鈦。如所理解的，BEOL互連部分126中的每一漸進金屬和通孔層可比底下的更大，以擴大互連的尺寸。
參考圖1到圖5，在一具體實施例中，後互連側110也可包含後側半導體層128，其具有最外面的底部晶粒互連130於其中。最外面的底部晶粒互連130耦合到BEOL互連部分126中的互連。在所示的示例中，後側半導體層128中最外面的底部晶粒互連130可包含例如由銅所製成的TSV 131。
圖2顯示了將第一載體140耦合到IC底部晶粒晶圓102的前裝置側112(圖1的具體實施例)。第一載體140可包含例如矽或玻璃，且可藉由任何現在已知或以後將開發的黏著劑142耦合至前裝置側112。黏著劑142的厚度可根據前裝置側112的結構形式而變化。
圖3到圖5顯示了在後側介電層122內產生暴露的底部晶粒互連120的程序。圖3顯示了蝕刻以顯露在IC底部晶粒晶圓102的後互連側110上的每一IC底部晶粒104的複數個底部晶粒互連130(即TSV 131)的範圍。在此處，可使用例如後側半導體層128(例如，矽)的乾式蝕刻移除將TSV 131的外部範圍顯露至半導體表面上方約5微米。TSV 131在此階段仍可具有其氧化物襯層(未示出)。蝕刻通常是指從基板(或基板上形成的結構)移除材料，且有時在遮罩就位的情況下進行，使得可從基板的某些區域選擇性地移除材料，同時使在基板其他區域的材料不受影響。通常有兩種蝕刻類型：(i)濕式蝕刻和(ii)乾式蝕刻。濕式蝕刻使用溶劑(例如酸)進行，可根據其能力來選擇溶劑以選擇性地溶解給定的材料(例如氧化物)，同時使另一種材料(例如多晶矽)相對完整。這種選擇性蝕刻給定材料的能力是許多半導體製造程序的基礎。濕式蝕刻通常會等向性地蝕刻均勻材料(例如，氧化物)，但濕式蝕刻也可異向性地蝕刻單晶材料(例如矽晶圓)。可使用電漿來執行乾式蝕刻。藉由調整電漿的參數，電漿系統可在數種模式下操作。普通的電漿蝕刻產生在晶圓表面反應的高能自由基，中性電荷，。由於中性粒子從各個角度攻擊晶圓，因此此程序是等向性的。離子研磨或濺射蝕刻以高能的惰性氣體離子轟擊晶圓，其大致上從一個方向接近晶圓，因此此過程是高度異向性的。反應性離子蝕刻(RIE)在濺射和電漿蝕刻之間的中間條件下操作。在本例中，可使用對TSV氧化物襯層具有選擇性的毯覆式半導體乾式蝕刻移除(不使用遮罩)。
圖4顯示了在複數個底部晶粒互連130、131的範圍上沉積後側介電層122。「沉積」可包含適合於待沉積材料的任何現在已知或以後將開發的技術，其包含但不限於例如：化學氣相沉積(CVD)、低壓CVD(LPCVD)、電漿增強CVD(PECVD)、半大氣壓CVD(SACVD)和高密度電漿CVD(HDPCVD)、快速熱CVD(RTCVD)、超高真空CVD(UHVCVD)、有限反應處理CVD(LRPCVD)、金屬有機CVD(MOCVD)、濺射沉積、離子束沉積、電子束沉積、雷射輔助沉積、熱氧化、熱氮化、旋塗方法、物理氣相沉積(PVD)、原子層沉積(ALD)、化學氧化、分子束磊晶(MBE)、電鍍、蒸發。在此處裡，CVD可能是合適的。
如本文所述，後側介電層122可包含適合於混合接合的任何 無機介電質(例如氧化物)，如本文進一步描述。圖5顯示了平面化後側介電層122和複數個底部晶粒互連130，從而產生暴露的底部晶粒互連120，即具有後側介電層122的暴露TSV 131。平面化是指使表面更為平面(即更平坦和/或光滑)的各種程序。化學機械拋光(CMP)是目前使用的傳統平面化製程，其通過化學反應和機械力的組合使表面平面化。CMP使用包含磨蝕性和腐蝕性化學成分的漿料與通常具有比晶圓更大直徑的拋光墊和保持環。墊和晶圓藉由動態拋光頭壓在一起，並藉由塑料保持環固定在適當位置。動態拋光頭繞不同的旋轉軸旋轉(即，非同心的)。這將移除材料，並使任何「形貌」變得均勻，從而使晶圓平坦且平面。其他目前使用的傳統平面化技術可包含：(i)氧化；(ii)化學蝕刻；(iii)離子佈植損壞的錐度控制；(iv)低熔點玻璃薄膜的沉積：(v)重新濺射所沉積的薄膜以使其平滑；(vi)光敏聚醯亞胺(PSPI)薄膜；(vii)新樹脂；(viii)低黏度液體環氧樹脂；(ix)旋塗玻璃(SOG)材料；及/或(x)犧牲回蝕刻。如圖5所示，IC底部晶粒104包含由後側介電層122圍繞的複數個暴露的底部晶粒互連120，即TSV 131。
圖6顯示了在暴露的底部晶粒互連120上加入焊墊層144於IC底部晶粒晶圓102上的一選擇性具體實施例。焊墊層144可連接到暴露的底部晶粒互連(例如，TSV 131)，以在其最外面表面處產生進一步暴露的底部晶粒互連120’。在需要虛設焊墊146以使用例如CMP來促進平面性的情況下，可能需要焊墊層144。焊墊層144可使用任何現在已知的或以後將開發的製程製造，例如單一鑲嵌製程。焊墊層144的介電層可由與後側介電層122相同的材料所製成，例如氧化物。
圖7顯示了針對IC底部晶粒晶圓102中的每個IC底部晶粒104(例如，圖5)產生包含再分佈層(RDL)152的中介層150。中介層150包含前側154和後側156。第二載體158耦合至其後側156。第二載體158可包含任何先前描述的第一載體140的材料(圖5)。RDL 152可包含從中介層150的後側156上的後側RDL互連160延伸到中介層150的前側154上的前側RDL互連 162的複數個佈線層(未標記)。佈線層形成於介電層164內(未單獨標記)，且可包含橫向延伸的導線層及/或垂直通孔層，即任何形式的BEOL佈線。最外面的介電層164包含適合於混合接合的無機介電質，例如氧化物。如圖所示，後側RDL互連160可具有比前側RDL互連162更大的間距。以這種方式，如將要描述的，前側RDL互連162可具有組態為與每一IC底部晶粒104的TSV 131配合的間距(圖5)，且後側RDL互連可具有組態為與具有比TSV 131更大間距的頂部晶粒互連(例如微柱)配合的間距。
圖8和圖9顯示將中介層150的前側154混合接合到IC底部晶粒晶圓102的後互連側110。針對每一相應的IC底部晶粒104，前側RDL互連162的至少一部分可操作地在相應IC底部晶粒104的第一位置處(在圓圈內)耦合至相應IC底部晶粒104的複數個暴露的底部晶粒互連120。混合接合包含使用由後側介電層122和中介層150的介電層164和底部晶粒互連120、前側RDL互連162(即，由銅製成)所形成的銅-氧化物層172(圖9)。混合接合可包含任何現在已知或以後將開發的處理。在一具體實施例中，如圖8所示，混合接合可包含電漿激活176圍繞複數個暴露的底部晶粒互連120的後側介電層122及圍繞中介層150的前側RDL互連162的介電層164。圖9顯示了將中介層150的前側154與IC底部晶粒晶圓102的後互連側110接觸，將後側介電層122接合至圍繞中介層150的前側RDL互連162的介電層164。亦即，產生銅-氧化物層172。如本領域所理解的，電漿激活在後側介電層122和介電層164上產生懸空氫氧化物(OH)鍵，這導致後側介電層122和介電層164之間在接觸時的黏合，即透過凡得瓦力。混合接合還可包含(如圖9所示)退火178，使前側RDL互連162與其相應的複數個暴露的底部晶粒互連120一起擴散。退火可針對互連的特定金屬或金屬合金(例如銅)在任何溫度和持續時間下進行。
圖10顯示了從中介層150移除第二載體158(圖9)，在第二位置180處(在圓圈內)暴露後側RDL互連160。取決於材料，可使用多種方式來 移除第二載體158(圖9)。舉例來說，在第二載體158包含塊矽的情況下，第二載體可藉由以下來移除：背面研磨以移除大部分的塊矽層、及乾式或濕式蝕刻以移除最終矽層並暴露後側RDL互連160。
圖11顯示在第二位置180處在暴露的後側RDL互連160上形成凸塊下金屬化(UBM)184。可使用任何現在已知或以後將開發的製程來形成UBM 184。在一示例中，可將通孔開口蝕刻到介電層164中以允許接觸到後側RDL互連160，然後以傳統的方式形成在後側RDL互連160上的UBM184，一般經由在圖案化區域中的合適UBM冶金的微影圖案化電鍍，然後剝除光阻劑和電鍍晶種層。UBM 184可包含適用於後側RDL互連160(例如由銅製成)的任何適當的導體材料(例如，銅、鎳等)以及到頂部晶粒190(圖13)的預期焊料，例如錫、錫-銀、錫-鉛等。
圖12顯示了從IC底部晶粒晶圓102(圖12)移除第一載體140(圖11)，以及將IC底部晶粒晶圓102(圖11)與中介層150切割為複數個IC底部晶粒104(僅示出一個)。舉例來說，可使用針對移除第二載體158(圖9)所描述的任何程序來移除第一載體140(圖11)。IC底部晶粒晶圓102可使用任何現在已知或以後將開發的切割製程來進行切割，例如使用刀片、雷射或電漿。每一IC底部晶粒104包含中介層150的相應RDL 152和相應UBM 184。圖12也顯示了提供包含複數個頂部晶粒互連192的IC頂部晶粒190。頂部晶粒互連192可採用任何現在已知或以後將開發的形式。在一具體實施例中，如圖12所示，IC頂部晶粒190的複數個頂部晶粒互連192可包含微柱配置，其組態以電性地耦合到選定的IC底部晶粒104的UBM184。頂部晶粒190可採用多種形式中的任一種，例如但不限於：CMOS、微機電系統(MEMS)或記憶體。
圖13顯示了根據本發明具體實施例的3D IC封裝100的形成。3D IC封裝100可藉由將IC頂部晶粒190的複數個頂部晶粒互連192耦合至在選定的IC底部晶粒104上的UBM 184來形成。耦合可根據任何現在已知 或以後將開發的晶片封裝製程，例如在頂部晶粒190上形成微柱並焊接到UBM 184。IC底部晶粒104可耦合到任何現在已知或以後將開發的電路板，例如使用受控塌陷晶片連接(C4)層198、球柵陣列(BGA)層疊板200及焊球202。
在圖13中，第一位置170與第二位置180對準(即部分重疊)，其中中介層150的前側RDL互連162在第一位置170處耦合至暴露的底部晶粒互連120，且中介層150的後側RDL互連160在第二位置180處經由UBM 184耦合到頂部晶粒互連192。也就是說，RDL 152在頂部晶粒190及/或IC底部晶粒104的覆蓋區內進行佈線。圖14顯示了3D IC封裝100電連接的示意俯視圖。在此範例中，IC底部晶粒104、具有RDL 152的中介層150和頂部晶粒190顯示為具有相同的外部尺寸並對齊；因此僅顯示一個方框。應理解到，它們可具有不同的外部尺寸且仍可根據此具體實施例對準，例如圖13。在此處，與傳統結構相比，中介層150的RDL 152致能在IC底部晶粒104的後互連側110上的精細間距互連(例如TSV 131(僅示出其中的少量))與具有較大間距尺寸的頂部晶粒互連192的整合。在IC底部晶粒104上的TSV 131放置通常由頂部晶粒190微柱間距驅動的情況下，RDL 152允許將微柱連接「扇入」到較小的TSV覆蓋區域。舉例來說，用於標準高帶寬記憶體(HBM)的頂部晶粒190在約20平方毫米(mm2)的覆蓋區中可具有約6600個頂部晶粒互連192，迫使在IC底部晶粒104上具有例如5微米(μm)直徑的TSV 131具有約55μm的間距。然而，使用RDL 152的同樣約為6600個頂部晶粒互連192可降低至約1.5mm2的覆蓋區，即前側RDL互連162在該覆蓋區內。在此情況下，IC底部晶粒104上的相同直徑的TSV 131可具有約15μm的間距。RDL 152可包含盡可能多的級別以適應更高密度的路由。
參考圖15，顯示了根據其他具體實施例的3D IC封裝100電連接的示意俯視圖。在此處，中介層150的前側RDL互連162(圖13)耦合到底部晶粒互連120(圖13)的第一位置170與中介層150的後側RDL互連160耦合 至頂部晶粒互連192的第二位置180可不部分重疊，亦即不對齊。也就是說，RDL 152可在頂部晶粒190及/或IC底部晶粒104的覆蓋區之外進行佈線。在此處，頂部晶粒190可放置在與底部晶粒互連120不同的位置，具有重新分配到頂部晶粒互連192的能力，允許使用改良的熱解決方案和更小的覆蓋區。
無論具體實施例如何，本發明的教導都適用於實際上任何技術節點，包含7奈米(nm)產品。此外，隨著3D/TSV產品採用的增加，本發明的具體實施例可在較舊的技術節點上實現。
回到圖13，顯示了根據本發明具體實施例的3D IC封裝100。3D IC封裝100可包含IC底部晶粒104，其具有與前裝置側112相對的後互連側110。後互連側110具有延伸到其的複數個底部晶粒互連120，其每一者可包含TSV 131。
3D IC封裝100也可包含頂部晶粒190，其具有與後側212相對的前裝置側210。前裝置側210具有複數個頂部晶粒互連192，其可包含組態以(尺寸、間距等)電耦合到UBM 184的微柱配置。中介層150(包含RDL 152)可位於IC底部晶粒104和IC頂部晶粒190之間。RDL 152可包含從其後側RDL互連160延伸到其前側RDL互連162的複數個佈線層。如本文所述，後側RDL互連160可具有比前側RDL互連162更大的間距。IC底部晶粒104可包含圍繞複數個底部晶粒互連120的後側介電層122。如所描述的，後側介電層122可結合到中介層150的介電層164。也可選擇性地提供包含IC底部晶粒104的複數個底部晶粒互連120的焊墊層144(圖6和圖13)。如本文所述，中介層150和IC底部晶粒104可混合接合在一起。
3D IC封裝100也可包含UBM 184，其在第一位置170處將後側RDL互連160耦合至複數個頂部晶粒互連192。前側RDL互連162經由UBM 184在第二位置180處耦合至複數個底部晶粒互連120(即，TSV 131或焊墊146)。如圖13和圖14所示，第一位置170可與第二位置180部分重疊。或者， 如圖15所示，第一位置170可不與第二位置180部分重疊。除非另有說明，否則本文所述的任何互連及/或佈線層可包含作為導體的銅，可能具有任何適當的耐火金屬線。
如上所述的方法用於3D IC封裝的製造。最終產品可為包含積體電路晶片的任何產品，範圍從玩具和其他低端應用到具有顯示器、鍵盤或其他輸入裝置的高級電腦產品及中央處理器。
此處使用的術語僅用於描述特定具體實施例的目的，且並不意圖限制本發明。如本文所使用的，單數形式「一」、「一個」和「這個」也包含複數形式，除非上下文另有明確指示。將進一步理解，當在本說明書中使用術語「包括」及/或「包含」時，表示所述特徵、整數、步驟、操作、元件及/或組件的存在，但不排除一或多個其他特徵、整數、步驟、操作、元件、組件及/或其群組的存在或添加。「選擇性的」或「選擇性地」表示隨後描述的事件或情況可發生或可不發生，且該描述包含事件發生的情況以及事件不發生的情況。
在整個說明書和申請專利範圍中使用的近似語言可用於修改可在不導致與其相關的基本功能改變的情況下允許變化的任何定量表示。因此，由一或多個術語(例如「約」、「大約」和「實質上」)修飾的數值不限於指定的精確數值。至少在某些情況下，近似語言可對應用於量測數值的儀器的準確度。此處和整個說明書和申請專利範圍中，除非上下文或語言另有說明，範圍限制可組合及/或互換，且這些範圍被確定並包含其中所包含的所有子範圍。應用於一範圍的特定數值的「近似」適用於兩個數值，且除非另外取決於量測數值的儀器的準確度，否則可指示所述數值的+/- 10%。
以下申請專利範圍中的所有裝置或步驟功能元件的相應結構、材料、動作及等效物旨在包含用以執行與其他權利要求中明確主張的元件結合的功能的任何結構、材料或動作。已出於說明和描述的目的提出 了對本發明的描述，但並不意圖窮舉或將本發明限制於所公開的形式。在不脫離本發明的範疇和精神的情況下，許多修改和變化對於所屬技術領域中具有通常知識者將是顯而易見。選擇和描述具體實施例是為了最佳解釋本發明的原理和實際應用，並使所屬技術領域中具有通常知識者能夠理解本發明以得到具有適用於預期的特定用途的各種修改的各種具體實施例。
100:3D IC封裝
104:IC底部晶粒
110:後互連側
112:前裝置側
120:底部晶粒互連
122:後側介電層
131:半導體通孔
150:中介層
152:再分佈層
160:後側RDL互連
162:前側RDL互連
164:介電層
170:第一位置
180:第二位置
184:凸塊下金屬化
190:頂部晶粒
192:頂部晶粒互連
198:受控塌陷晶片連接層
200:球柵陣列層疊板
202:焊球

Claims (20)

  1. 一種用以形成一三維(3D)積體電路(IC)封裝的方法，該方法包含：提供包含複數個IC底部晶粒於其中的一IC底部晶粒晶圓，每一IC底部晶粒具有與一前裝置側相對的一後互連側，該後互連側具有由一後側介電層圍繞的複數個暴露的底部晶粒互連；將一第一載體耦合至該IC底部晶粒晶圓的該前裝置側；針對在該IC底部晶粒晶圓中的每一IC底部晶粒產生包含一再分佈層(RDL)的一中介層，該中介層具有一前側、一後側及耦合至其該後側的一第二載體，該RDL包含複數個佈線層，該佈線層從該中介層的該後側上的後側RDL互連延伸至該中介層的該前側上的前側RDL互連；將該中介層的該前側混合接合至該IC底部晶粒晶圓的該後側，其中針對每一相應的IC底部晶粒，該前側RDL互連的至少一部分在該相應的IC底部晶粒的一第一位置處操作地耦合至該相應的IC底部晶粒的該複數個暴露的底部晶粒互連；從該中介層移除該第二載體，在一第二位置處暴露該後側RDL互連；在該第二位置處的該暴露的後側RDL互連上形成一凸塊下金屬化(UBM)；移除該第一載體並將該IC底部晶粒晶圓與該中介層切割成複數個IC底部晶粒，每一IC底部晶粒包含該中介層的一相應RDL和一相應UBM；提供包含複數個頂部晶粒互連的一IC頂部晶粒；以及藉由將該IC頂部晶粒的該複數個頂部晶粒互連耦合至在一選定IC底部晶粒上的該UBM來形成該3D IC封裝。
  2. 如申請專利範圍第1項所述的方法，在進行混合接合之前，更包含： 蝕刻以顯露在該IC底部晶粒晶圓的該後互連側上的每一IC底部晶粒的複數個底部晶粒互連的一範圍；在該複數個底部晶粒互連的該範圍內沉積該後側介電層；以及平面化該後側介電層和複數個底部晶粒互連，暴露該複數個底部晶粒互連。
  3. 如申請專利範圍第2項所述的方法，更包含在蝕刻以顯露之前加入一焊墊層至該IC底部晶粒晶圓，該焊墊層包含複數個底部晶粒互連。
  4. 如申請專利範圍第1項所述的方法，其中該IC頂部晶粒的該複數個頂部晶粒互連包含組態以電耦合至該選定IC底部晶粒的該UBM的一微柱配置。
  5. 如申請專利範圍第1項所述的方法，其中該IC底部晶粒晶圓的該複數個底部晶粒互連包含半導體通孔。
  6. 如申請專利範圍第1項所述的方法，其中該混合接合包含：電漿激活圍繞該複數個暴露的底部晶粒互連的該後側介電層和圍繞該中介層的該前側RDL互連的一介電層；將該中介層的該前側接觸該IC底部晶粒晶圓的該後互連側，將該後側介電層接合到圍繞該中介層的該前側RDL互連的該介電層；以及退火以使該前側RDL互連與該複數個暴露的底部晶粒互連中的相應者一起擴散。
  7. 如申請專利範圍第1項所述的方法，其中該後側RDL互連具有比該前側RDL互連更大的一間距。
  8. 如申請專利範圍第1項所述的方法，其中該第一位置與該第二位置不部分重疊。
  9. 一種三維(3D)積體電路(IC)封裝，包含：具有與一前裝置側相對的一後互連側的一IC底部晶粒，該後互連側具有向其延伸的複數個底部晶粒互連；具有與一後側相對的一前裝置側的一IC頂部晶粒，該前裝置側具有複數個頂部晶粒互連；在該IC底部晶粒及該IC頂部晶粒之間包含一再分佈層(RDL)的一中介層，該RDL包含從其後側RDL互連延伸至其前側RDL互連的複數個佈線層；以及一凸塊下金屬化(UBM)，其在一第一位置處將該後側RDL互連耦合至該複數個頂部晶粒互連；其中該前側RDL互連在一第二位置處耦合至該複數個底部晶粒互連。
  10. 如申請專利範圍第9項所述的3D IC封裝，更包含圍繞該IC底部晶粒上的該複數個底部晶粒互連的一後側介電層，該後側介電層接合到該中介層的一介電層。
  11. 如申請專利範圍第10項所述的3D IC封裝，其中該後側介電層包含一佈線層，該佈線層包含該IC底部晶粒的該複數個底部晶粒互連。
  12. 如申請專利範圍第9項所述的3D IC封裝，其中該IC頂部晶粒的該頂部晶粒互連包含組態以電耦合至該UBM的一微柱配置。
  13. 如申請專利範圍第9項所述的3D IC封裝，其中每一個該底部晶粒互連包含半導體通孔(TSV)。
  14. 如申請專利範圍第9項所述的3D IC封裝，其中該中介層與該IC底部晶粒混合接合在一起。
  15. 如申請專利範圍第9項所述的3D IC封裝，其中該後側RDL互連具有比該前側RDL互連更大的一間距。
  16. 如申請專利範圍第9項所述的3D IC封裝，其中該第一位置與該第二位置不部分重疊。
  17. 如申請專利範圍第9項所述的3D IC封裝，其中該第一位置與該第二位置部分重疊。
  18. 一種三維(3D)積體電路(IC)封裝，包含：具有與一前裝置側相對的一後互連側的一IC底部晶粒，該後互連側具有暴露於其中的複數個半導體通孔(TSV)；具有一前裝置側的一IC頂部晶粒，該前裝置側具有暴露於其中的複數個微柱；在該IC底部晶粒及該IC頂部晶粒之間包含一再分佈層(RDL)的一中介層，該RDL包含從其後側RDL互連延伸至其前側RDL互連的複數個佈線層；以及一凸塊下金屬化(UBM)，其在一第一位置處將該後側RDL互連耦合至該複數個頂部晶粒互連； 其中該前側RDL互連在一第二位置處耦合至該複數個底部晶粒互連；以及其中該後側RDL互連具有比該前側RDL互連更大的一間距。
  19. 如申請專利範圍第18項所述的3D IC封裝，其中該第一位置與該第二位置不部分重疊。
  20. 如申請專利範圍第18項所述的3D IC封裝，其中該中介層與該IC底部晶粒混合接合在一起。
TW107147434A 2018-01-29 2018-12-27 具有ｒｄｌ中介層的三維ｉｃ封裝與相關方法 TWI702658B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/882,036 2018-01-29
US15/882,036 US10388631B1 (en) 2018-01-29 2018-01-29 3D IC package with RDL interposer and related method

Publications (2)

Publication Number Publication Date
TW201941313A TW201941313A (zh) 2019-10-16
TWI702658B true TWI702658B (zh) 2020-08-21

Family

ID=67393677

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107147434A TWI702658B (zh) 2018-01-29 2018-12-27 具有ｒｄｌ中介層的三維ｉｃ封裝與相關方法

Country Status (2)

Country Link
US (2) US10388631B1 (zh)
TW (1) TWI702658B (zh)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109285825B (zh) * 2017-07-21 2021-02-05 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
KR102574452B1 (ko) * 2018-07-03 2023-09-04 삼성전자 주식회사 반도체 칩 및 이를 포함하는 반도체 패키지
US11342256B2 (en) 2019-01-24 2022-05-24 Applied Materials, Inc. Method of fine redistribution interconnect formation for advanced packaging applications
IT201900006740A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di strutturazione di substrati
IT201900006736A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di fabbricazione di package
US11404600B2 (en) 2019-06-11 2022-08-02 Meta Platforms Technologies, Llc Display device and its process for curing post-applied underfill material and bonding packaging contacts via pulsed lasers
US11374148B2 (en) 2019-06-11 2022-06-28 Facebook Technologies, Llc Dielectric-dielectric and metallization bonding via plasma activation and laser-induced heating
US11931855B2 (en) 2019-06-17 2024-03-19 Applied Materials, Inc. Planarization methods for packaging substrates
DE102019211371A1 (de) * 2019-07-30 2021-02-04 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zum Herstellen eines elektronischen Schaltungsbauelements und elektronisches Schaltungsbauelement
US11410902B2 (en) * 2019-09-16 2022-08-09 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
KR20210065353A (ko) 2019-11-27 2021-06-04 삼성전자주식회사 반도체 패키지
US11862546B2 (en) * 2019-11-27 2024-01-02 Applied Materials, Inc. Package core assembly and fabrication methods
CN113347786B (zh) 2020-02-18 2023-12-26 财团法人工业技术研究院 具导电通孔阵列基板的电子装置
US11289453B2 (en) 2020-02-27 2022-03-29 Qualcomm Incorporated Package comprising a substrate and a high-density interconnect structure coupled to the substrate
US11257790B2 (en) 2020-03-10 2022-02-22 Applied Materials, Inc. High connectivity device stacking
US11454884B2 (en) 2020-04-15 2022-09-27 Applied Materials, Inc. Fluoropolymer stamp fabrication method
US11400545B2 (en) 2020-05-11 2022-08-02 Applied Materials, Inc. Laser ablation for package fabrication
US11232951B1 (en) 2020-07-14 2022-01-25 Applied Materials, Inc. Method and apparatus for laser drilling blind vias
US11676832B2 (en) 2020-07-24 2023-06-13 Applied Materials, Inc. Laser ablation system for package fabrication
US11521937B2 (en) 2020-11-16 2022-12-06 Applied Materials, Inc. Package structures with built-in EMI shielding
US11404318B2 (en) 2020-11-20 2022-08-02 Applied Materials, Inc. Methods of forming through-silicon vias in substrates for advanced packaging
US20220165669A1 (en) * 2020-11-25 2022-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device structure, stacked semiconductor device structure and method of manufacturing semiconductor device structure
US11817380B2 (en) * 2021-02-26 2023-11-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of forming same
US11705365B2 (en) 2021-05-18 2023-07-18 Applied Materials, Inc. Methods of micro-via formation for advanced packaging
US11881446B2 (en) 2021-12-23 2024-01-23 Nanya Technology Corporation Semiconductor device with composite middle interconnectors
US20230207522A1 (en) * 2021-12-24 2023-06-29 Intel Corporation Reconstituted wafer-to-wafer hybrid bonding interconnect architecture with known good dies

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9412661B2 (en) * 2012-11-21 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming package-on-package structure
US9768048B2 (en) * 2013-03-15 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package on-package structure

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080277778A1 (en) 2007-05-10 2008-11-13 Furman Bruce K Layer Transfer Process and Functionally Enhanced Integrated Circuits Products Thereby
KR101739939B1 (ko) * 2011-03-16 2017-05-26 삼성전자주식회사 반도체 장치의 제조 방법
US8975726B2 (en) * 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same
KR101411813B1 (ko) 2012-11-09 2014-06-27 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US20150371938A1 (en) 2014-06-19 2015-12-24 Invensas Corporation Back-end-of-line stack for a stacked device
US9933566B2 (en) * 2015-11-13 2018-04-03 Cisco Technology, Inc. Photonic chip with an evanescent coupling interface

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9412661B2 (en) * 2012-11-21 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming package-on-package structure
US9768048B2 (en) * 2013-03-15 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package on-package structure

Also Published As

Publication number Publication date
US11037906B2 (en) 2021-06-15
US20190237430A1 (en) 2019-08-01
US20190304954A1 (en) 2019-10-03
TW201941313A (zh) 2019-10-16
US10388631B1 (en) 2019-08-20

Similar Documents

Publication Publication Date Title
TWI702658B (zh) 具有ｒｄｌ中介層的三維ｉｃ封裝與相關方法
US20210313196A1 (en) 3D Packages and Methods for Forming the Same
TWI691026B (zh) 製造半導體元件的方法
TWI744411B (zh) 半導體裝置、晶粒堆疊結構、封裝結構及其製造方法
US10157890B2 (en) Semiconductor structure and method of manufacturing the same
CN109411443B (zh) 垂直堆叠晶圆及其形成方法
US20200126938A1 (en) 3D Packages and Methods for Forming the Same
US8202800B2 (en) Method of forming through silicon via with dummy structure
TWI783269B (zh) 封裝、半導體封裝及其形成方法
Civale et al. 3-D wafer-level packaging die stacking using spin-on-dielectric polymer liner through-silicon vias
TW201308556A (zh) 使用多層介層窗的３ｄ積體電路
TW202109804A (zh) 接合結構及其形成方法
TW201807791A (zh) 半導體裝置結構
Beyne Through-silicon via technology for 3D IC
TW201843776A (zh) 形成用於接合晶圓之積體電路結構之方法及所產生的結構
TWI752627B (zh) 半導體元件及其製造方法
Lu et al. 3D integration using adhesive, metal, and metal/adhesive as wafer bonding interfaces
US11810882B2 (en) Solder based hybrid bonding for fine pitch and thin BLT interconnection
TWI825572B (zh) 晶片封裝結構及其形成方法
WO2022252087A1 (en) Method of manufacturing active reconstructed wafers
US20220359268A1 (en) Through wafer isolation element backside processing
TW202326998A (zh) 具有堆疊結構的半導體元件
TW202410298A (zh) 具有金屬平面層的基板穿孔以及製造其之方法
TW202414546A (zh) 封裝件及製造半導體裝置的方法
TW202315029A (zh) 封裝結構及其形成方法