TW202109804A - 接合結構及其形成方法 - Google Patents

接合結構及其形成方法 Download PDF

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TW202109804A
TW202109804A TW108138581A TW108138581A TW202109804A TW 202109804 A TW202109804 A TW 202109804A TW 108138581 A TW108138581 A TW 108138581A TW 108138581 A TW108138581 A TW 108138581A TW 202109804 A TW202109804 A TW 202109804A
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layer
bonding
stop layer
conductive
pads
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TW108138581A
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TWI718722B (zh
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陳憲偉
陳潔
陳明發
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例提供一種裝置，包含：內連線結構，在基底上方；多個第一導電接墊，在內連線結構上方且連接至內連線結構；平坦化終止層，在多個第一導電接墊中的第一導電接墊的側壁及頂表面上方延伸；表面介電層，在平坦化終止層上方延伸；以及多個第一接合墊，在表面介電層內且連接至多個第一導電接墊。

Description

接合結構及其形成方法
在晶圓間（wafer-to-wafer）接合技術中，已開發出各種方法來將兩個封裝組件（諸如晶圓）接合在一起。一些晶圓接合方法包含熔融接合、共熔接合、直接金屬接合、混合接合以及類似者。在熔融接合中，將晶圓的氧化物表面接合至另一晶圓的氧化物表面或矽表面。在共熔接合中，將兩種共熔材料放置在一起，且施加高壓及高溫。共熔材料因此而熔化。當熔化的共熔材料固化時，晶圓接合在一起。在直接金屬對金屬接合中，在高溫下將兩個金屬墊抵靠彼此按壓，且金屬墊的相互擴散使得金屬墊接合。在混合接合中，兩個晶圓的金屬墊經由直接金屬對金屬接合而彼此接合，且兩個晶圓中的一者的氧化物表面接合至另一晶圓的氧化物表面或矽表面。
以下揭露內容提供用於實施本發明的不同特徵的許多不同實施例或實例。下文描述組件及佈置的具體實例以簡化本揭露。當然，這些組件及佈置僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，第一特徵形成於第二特徵上方或第二特徵上可包含第一特徵及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可形成於第一特徵與第二特徵之間以使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露可在各種實例中重複附圖標號及/或字母。此重複為出於簡單性及清晰的目的，且本身不規定所論述的各種實施例及/或配置之間的關係。
此外，為易於描述，本文中可使用諸如「在...之下」、「在...下方」、「下部」、「在...上方」、「上部」以及類似者的空間相對術語，以描述如圖式中所示出的一個元件或特徵相對於另一（些）元件或特徵的關係。除圖式中所描繪的定向之外，空間相對術語亦意欲涵蓋裝置在使用或操作中的不同定向。設備可以其他方式定向（旋轉90度或處於其他定向），且本文中所使用的空間相對描述詞可同樣相應地進行解釋。
根據一些實施例，提供一種接合結構及方法。在內連線結構上方形成表面介電層，且在表面介電層中形成接合墊。藉由使用平坦化終止層，可減小表面介電層的厚度。此可跨表面介電層提供增加的熱傳導，所述熱傳導可使在較高溫度下的裝置效能提高。另外，由於表面介電層更薄，可減小裝置的總體尺寸。
圖1至圖12示出根據一些實施例的在裝置結構100的形成中的中間階段的剖面圖。圖1示出根據一些實施例的基底102及基底102上方形成的特徵。基底102可為半導體基底，諸如塊狀半導體、絕緣體上半導體（semiconductor-on-insulator；SOI）基底、半導體晶圓或類似者，所述半導體基底可經摻雜（例如經p型摻雜劑或n型摻雜劑摻雜）或未經摻雜。大體而言，SOI基底包含絕緣層上形成的半導體材料層。絕緣層可為例如內埋氧化物（buried oxide；BOX）層、氧化矽層或類似者。絕緣層設置於基底（通常為矽基底或玻璃基底）上。亦可使用其他基底，諸如多層基底或梯度基底。在一些實施例中，基底的半導體材料可包含：矽；鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其組合。
在一些實施例中，基底102及其上形成的特徵用於形成裝置晶粒。在此類實施例中，可在基底102的頂表面上形成積體電路裝置。例示性積體電路裝置可包含互補金屬氧化物半導體（complementary metal-oxide semiconductor；CMOS）電晶體、鰭式場效電晶體（fin field-effect transistors；FinFET）、電阻器、電容器、二極體、類似者或其組合。本文中未示出積體電路裝置的細節。在一些實施例中，基底102用於形成插入式（interposer）結構。在此類實施例中，基底102上未形成諸如電晶體或二極體的主動裝置。可在基底102中形成諸如電容器、電阻器、電感器或類似者的被動裝置。在基底102為插入式結構的部分的一些實施例中，基底102亦可為介電基底。在一些實施例中，穿孔（未示出）可形成為延伸穿過基底102，以使基底102的相對側上的組件互連。
在圖1中，在基底102上方形成介電層104。介電層104可包含包括一或多種材料的一或多個層。在積體電路裝置在基底102上形成的實施例中，介電層104可填充積體電路裝置的電晶體的閘極堆疊（未示出）之間的空間。在一些實施例中，介電層104可為層間介電（inter-layer dielectric；ILD）層。介電層104可由磷矽酸鹽玻璃（phosphosilicate glass；PSG）、硼矽酸鹽玻璃（borosilicate glass；BSG）、硼摻磷矽酸鹽玻璃（boron-doped phosphosilicate glass；BPSG）、氟摻矽玻璃（fluorine-doped silicate glass；FSG）、正矽酸四乙酯（tetraethyl orthosilicate；TEOS）、類似者或其組合形成。在一些實施例中，介電層104可包含由具有低於約3.0的k值的低介電常數（low-k）介電材料形成的層。在一些實施例中，使用旋塗製程形成介電層104，或使用沉積方法（諸如電漿增強式化學氣相沉積（plasma enhanced chemical vapor deposition；PECVD）、可流動化學氣相沉積（flowable chemical vapor deposition；FCVD）、低壓化學氣相沉積（low pressure chemical vapor deposition；LPCVD）或類似者）形成所述介電層。
另外，在圖1中，在介電層104中形成接觸插塞（contact plug）106。接觸插塞106電性連接至基底102的積體電路裝置。舉例而言，接觸插塞106可為連接至積體電路裝置的電晶體的閘極電極（未示出）的閘極接觸插塞，及/或可為電性連接至電晶體的源極/汲極區的源極/汲極接觸插塞。在形成介電層104之後，經由介電層104形成用於接觸插塞106的開口。可使用可接受的微影及蝕刻技術形成開口。舉例而言，光阻可在介電層上方形成且經圖案化，且可藉由蝕刻介電層104使用經圖案化的光阻作為蝕刻罩幕以在介電層104中形成開口。可使用適合的濕式蝕刻製程、乾式蝕刻製程或其組合來蝕刻介電層104。在一些實施例中，諸如擴散障壁層、黏著層或類似者的襯層（liner）可在開口中形成，且導電材料可隨後在開口中的襯層上方形成。襯層可包含鈦、氮化鈦、鉭、氮化鉭、類似者或其組合。導電材料可包含鈷、銅、銅合金、銀、金、鎢、鋁、鎳、類似者或其組合。在形成導電材料之後，可執行平坦化製程（諸如研磨製程、化學機械拋光（chemical-mechanical polish；CMP）製程或類似者）以自介電層104的表面移除過量材料。剩餘襯層及導電材料由此形成接觸插塞106。
根據一些實施例，在圖2中，在接觸插塞106及介電層104上方形成內連線結構108。內連線結構108在基底102中形成的裝置之間提供佈線及電性連接，且可為重佈線結構。內連線結構108可包含可為金屬間介電（inter-metal dielectric；IMD）層的多個絕緣層110。絕緣層110中的每一者包含一或多個金屬線112及/或其中形成的通孔113。金屬線112及通孔113可藉由接觸插塞106電性連接至基底102的主動裝置及/或被動裝置。金屬線112可為例如重佈線層。
在一些實施例中，絕緣層110可由具有低於約3.0的k值的低介電常數介電材料形成。絕緣層110可由具有小於2.5的k值的額外低介電常數（extra-low-k；ELK）介電材料形成。在一些實施例中，絕緣層110可由含氧及/或含碳的低介電常數介電材料、三氧化矽烷（Hydrogen SilsesQuioxane；HSQ）、甲基矽倍半氧烷（MethylSilsesQuioxane；MSQ）、類似者或其組合形成。在一些實施例中，絕緣層110中的一些或全部由非低介電常數介電材料，諸如氧化矽、碳化矽（SiC）、碳氮化矽（SiCN）、碳氮氧化矽（SiOCN）或類似者來形成。在一些實施例中，由碳化矽、氮化矽或類似者形成的蝕刻終止層（未示出）可在絕緣層110之間形成。在一些實施例中，IMD層110由多孔材料（諸如SiOCN、SiCN、SiOC、SiOCH或類似者）形成，且可藉由旋塗式塗覆法或沉積製程（諸如電漿增強式化學氣相沉積（PECVD）、CVD、PVD或類似者）形成。在一些實施例中，內連線結構108可包含一或多種其他類型的層，諸如擴散障壁層（未示出）。
在一些實施例中，可使用單金屬鑲嵌製程及/或雙金屬鑲嵌製程、第一通孔製程或第一金屬製程而形成內連線結構108。在一實施例中，使用可接受的微影及蝕刻技術形成絕緣層110，且在其中形成開口（未示出）。擴散障壁層（未示出）可在開口中形成且可包含諸如TaN、Ta、TiN、Ti、CoW或類似者的材料，且可藉由諸如CVD、ALD或類似者的沉積製程在開口中形成。導電材料可由銅、鋁、鎳、鎢、鈷、銀、其組合或類似者在開口中形成，且可藉由電化學鍍覆製程、CVD、ALD、PVD、類似者或其組合在開口中的擴散障壁層上方形成。在形成導電材料之後，可使用例如諸如CMP的平坦化製程來移除過量導電材料，由此在最底部IMD層110的開口中保留金屬線112。可隨後重複製程以形成額外絕緣層110及其中的金屬線112以及通孔113。在一些實施例中，可形成最頂部絕緣層110及形成於其中的金屬線112，所述最頂部絕緣層及金屬線的厚度大於內連線結構108的其他絕緣層110的厚度。在一些實施例中，最頂部金屬線112中的一或多者為與基底102電隔離的虛設線。
在圖3中，在內連線結構108上方形成鈍化層114，且在鈍化層114中形成一或多個開口116。鈍化層114可包括一或多種材料的一或多個層。舉例而言，鈍化層114可包含氮化矽、氧化矽、氮氧化矽、類似者或組合的一或多個層。鈍化層114可藉由適合的製程（諸如CVD、PECVD、PVD、ALD、類似者或其組合）形成。鈍化層114可形成為具有比最頂部絕緣層110的厚度更大的厚度。
可使用適合的微影及蝕刻製程在鈍化層114中形成開口116。舉例而言，光阻可在鈍化層114上方形成且經圖案化，且隨後經圖案化的光阻可用作蝕刻罩幕。可使用適合的濕式蝕刻製程及/或乾式蝕刻製程來蝕刻鈍化層114。形成開口116以暴露出用於電性連接的金屬層112的部分（例如內連線結構108的最頂部金屬層112）。
根據一些實施例，在圖4中，在鈍化層114上方形成導電接墊118。一或多個導電接墊118可形成為延伸穿過開口116，且與內連線結構108的最頂部金屬線112中的一或多者進行電性連接。在一些實施例中，導電接墊118藉由首先在鈍化層114及開口116上方形成晶種層而形成。在一些實施例中，晶種層為可由不同材料形成的包括一或多個層的金屬層。可使用例如物理氣相沉積（physical vapor deposition；PVD）或類似者形成晶種層。在晶種層上形成並圖案化光阻，且在光阻的開口中及晶種層的暴露部分上形成導電材料。在一些實施例中，可藉由鍍覆製程（諸如使用電鍍製程或無電式電鍍製程或類似者）形成導電材料。導電材料可包含一或多種材料，諸如銅、鈦、鎢、金、鈷、鋁、類似者或其組合。隨後使用例如適合的灰化製程或剝離製程，諸如使用氧電漿或類似者而移除光阻及在其上不形成導電材料的晶種層的部分。一旦移除光阻，則可使用可接受的蝕刻製程，諸如濕式蝕刻製程或乾式蝕刻製程來移除晶種層的剩餘暴露部分。晶種層的剩餘部分及導電材料形成導電接墊118。
在一些實施例中，可藉由首先沉積導電材料的毯覆層來形成導電接墊118。舉例而言，CVD、PVD或類似者可用於在鈍化層114及開口116上方以及在金屬層112上方沉積鋁層。光阻層（未分別示出）可隨後在鋁層上方形成，且鋁層可經蝕刻以形成導電接墊118。其他實施例中可使用其他技術形成導電接墊118，且全部此類技術視為在本揭露的範疇內。
在一些實施例中，在執行額外處理步驟之前，電性連接至內連線結構108的導電接墊118可用作測試墊。舉例而言，導電接墊118可經探測為晶圓接收測試、電路測試、良裸晶粒（Known Good Die；KGD）測試或類似者的部分。可執行探測以驗證基底102的主動裝置或被動裝置，或在基底102或內連線結構108內的相應電連接件（例如金屬線112或通孔113）的功能性。可藉由接觸探測針（未示出）對導電接墊118執行探測。探測針可為包含例如可連接至測試設備的多個探測針的探針卡的部分。
在一些實施例中，導電接墊118的導電材料可不同於金屬線112的導電材料。舉例而言，導電接墊118可為鋁，且金屬線112可為銅，但可使用其他導電材料。在一些實施例中，導電接墊118可具有在約2微米與約30微米之間的寬度W或在約20微米與約100微米之間的長度（例如垂直於寬度）。在一些實施例中，導電接墊118可具有在約500奈米與約3000奈米之間的厚度。在一些情況下，較厚的導電接墊118可具有當探測時變得受損的較低風險。因此，導電接墊118可具有比金屬線112更大的厚度。為降低在探測期間損壞的機率，導電接墊118亦可由比金屬線112的導電材料（例如銅）較不軟的導電材料（例如鋁）形成。本揭露中描述的實施例可實現使用導電接墊118的更大厚度，而無需增加結構（例如裝置結構100）的總厚度。
根據一些實施例，轉向圖5，在導電接墊118及鈍化層114上方形成第一終止層120。在一些實施例中，第一終止層120可用作用於後續CMP製程的終止層（參見圖7）。第一終止層120可包括介電材料，諸如碳化矽、碳氧化矽、氮化矽、氧化矽、類似者或其組合。可使用諸如CVD、PVD、ALD或類似者的製程形成第一終止層120。第一終止層120沉積於導電接墊118的頂表面上方，且可共形地沉積於鈍化層114及導電接墊118的頂表面上方及導電接墊118的側壁上方。在一些實施例中，可形成具有在約300埃與約1500埃之間的厚度T1的第一終止層120。第一終止層120可形成為適合於終止或減緩下文在圖7中描述的平坦化製程的厚度。在一些情況下，較厚的第一終止層120可用於避免在下文描述的平坦化製程期間暴露導電接墊118。在一些實施例中，第一終止層120亦用作蝕刻終止（參見例如圖10及圖16），且可選擇第一終止層120的厚度使得在平坦化之後保持第一終止層120的足夠厚度以充當蝕刻終止。
轉向圖6，在第一終止層120上方形成介電層122。介電層122可由一或多種介電材料（諸如氧化矽、氮化矽、SiOCH、SiCH、類似者或其組合）的一或多個層形成。可藉由沉積製程（諸如CVD、PECVD、PVD、ALD、類似者或其組合）形成介電層122。在一些實施例中，介電層122及第一終止層120由不同的介電材料製成。介電層122可形成為具有比導電接墊118的厚度更大的厚度，使得介電層122的材料橫向環繞導電接墊118，且使得介電層122可經平坦化（參見下文），而無需暴露導電接墊118。
在圖7中，對介電層122執行平坦化製程。平坦化製程可為例如CMP製程。第一終止層120用於終止或減緩接近導電接墊118的頂表面的平坦化製程。如圖7中所示，在已執行平坦化製程之後，第一終止層120的一部分可保留在導電接墊118的頂表面上方。在一些實施例中，保留在導電接墊118上的第一終止層120的厚度T2可在約100埃與約300埃之間，諸如約在約50埃與約150埃之間。在一些實施例中，厚度T1與厚度T2的比率可在3比1與約50比1之間。保留的第一終止層120的厚度T2可足夠厚以保護導電接墊118。在一些情況下，較小厚度T2實現在導電接墊118與表面介電層126（參見例如圖17）的頂表面之間的較小總距離，所述厚度可改良熱導率且降低在最終裝置中的電容效應。在一些實施例中，第一終止層120的部分可保留在導電接墊118上，以便隨後用作蝕刻終止層（參見例如圖10）。在一些實施例中，可控制平坦化製程，使得保留的第一終止層120的厚度T2可足以充當蝕刻終止。
轉向圖8，在介電層122及第一終止層120上方形成第二終止層124。第二終止層124可隨後用作蝕刻終止層（參見圖10）。在一些實施例中，第二終止層124為與第一終止層120相同的材料，但在其他實施例中，第一終止層120及第二終止層124可為不同材料。第二終止層124可包括材料，諸如碳化矽、碳氧化矽、氮化矽、氧化矽、類似者或其組合。可使用諸如CVD、PVD、ALD或類似者的製程形成第二終止層124。在一些情況下，使用第二終止層124可改良第二終止層124的表面平坦度及在後續製程步驟期間的表面平坦度。在一些實施例中，第二終止層124可形成為具有在約150埃與約1500埃之間（諸如約300埃）的厚度。在一些實施例中，第二終止層124的厚度可足以充當蝕刻終止層（參見例如圖10）。在一些情況下，較厚的第二終止層124可改良第二終止層124的表面平坦度及隨後形成的特徵的表面平坦度。
轉向圖9，在第二終止層124上方形成表面介電層126。表面介電層126可由一或多種介電材料的一或多個層形成，且可包括含矽材料，諸如氧化矽、氮氧化矽、氮化矽或類似者。在一些實施例中，表面介電層126及第二終止層124由不同的介電材料製成。可藉由沉積製程（諸如CVD、PECVD、PVD、ALD、類似者或其組合）形成表面介電層126。在一實施例中，表面介電層126包括氧化矽，且可替代性地稱作「接合氧化物（bonding oxide）」。
根據一些實施例，在圖10中，在表面介電層126中形成開口127。可使用可接受的微影及蝕刻技術來形成開口127。舉例而言，微影製程可包含以下步驟：在表面介電層126上方形成光阻（未示出）；圖案化光阻以具有對應於開口127的開口；使接墊開口127延伸穿過光阻且至表面介電層126中；以及隨後移除光阻。光阻可為單層光阻、雙層光阻、三層光阻或類似者。執行蝕刻製程使得蝕刻在第二終止層124上停止。可執行額外的蝕刻製程以使開口127延伸穿過第二終止層124。在第二終止層124在第一終止層120上的一些區域中，開口127可延伸穿過第二終止層124及第一終止層120兩者。舉例而言，在導電接墊118上方的區域中，開口127可延伸穿過第二終止層124及第一終止層120，以暴露出導電接墊118的頂表面。延伸穿過第二終止層124及第一終止層120的實例開口在圖10中標示為開口127A。在一些實施例中，開口127可具有在約1微米與約5微米之間的寬度，但其他寬度為可能的。在一些實施例中，開口127可具有楔形（tapered）輪廓，諸如具有在約1微米與約2微米之間的底部寬度及在約2微米與約5微米之間的頂部寬度。在一些情況下，開口127A的寬度可在導電接墊118的寬度W的約10%與約100%之間。以此方式，開口127A的寬度可使得多個開口127A可在單個導電接墊118上方形成。
根據一些實施例，轉向圖11，在開口127中形成接合墊128。接合墊128可具有類似於在其中形成所述接合墊的開口127的尺寸，且可具有類似形狀（例如具有楔形輪廓）。接合墊128可由包含金屬或金屬合金（諸如銅、銀、金、鎢、鈷、鋁、類似者或其組合）的導電材料形成。在一些實施例中，接合墊128及導電接墊118可為不同的導電材料。舉例而言，接合墊128可為銅，且導電接墊118可為鋁，但其他材料為可能的。在一些實施例中，接合墊128的形成包含以下步驟：在開口127中沉積晶種層（未示出），所述晶種層可包含銅、銅合金、鈦或類似者；及隨後使用例如鍍覆製程、無電式鍍覆製程或類似者填充開口127的剩餘部分。可使用諸如CMP製程的平坦化製程自表面介電層126移除過量導電材料及晶種層。圖11中所示的製程代表可用於形成接合墊128的實例製程，且其他製程或技術（諸如金屬鑲嵌製程、雙金屬鑲嵌製程或另一種製程）可用於其他實施例中。開口127A中形成的接合墊128可進行與導電接墊118的電性連接，且多個接合墊128可進行與同一導電接墊118的電性連接。以此方式，可形成具有電性連接至基底102中的裝置的接合墊128的裝置結構100。
仍參考圖11，在一些實施例中，可形成一些接合墊，而無需電性連接至導電接墊118。無需電性連接的接合墊可為例如「虛設」接合墊，所述虛設接合墊可在移除過量導電材料的平坦化步驟之後降低不均勻負載且改良表面平坦度。藉由改良表面平坦度，可獲得表面之間的較佳接合（參見圖21）。實例虛設接合墊在圖11中指定為接合墊128D。在一些實施例中，轉向圖12，可形成虛設導電接墊118，所述導電接墊的實例指定為虛設導電接墊118D。形成虛設導電接墊118D亦可降低負載效應且進一步改良表面平坦度。虛設導電接墊118D可用於包含下文描述的本文所描述的實施例中的任一者。虛設導電接墊118D可或可不電性連接至任何金屬線112。如圖12中所示，虛設接合墊128D可形成為與虛設導電接墊118D接觸。在一些實施例中，不形成虛設接合墊128D及/或虛設導電接墊118D。
返回至圖11，使用第一終止層120作為用於平坦化製程的終止（參見圖7）可實現更薄的表面介電層126。舉例而言，表面介電層126可形成為具有在約0.5微米與約8微米之間的厚度T3，諸如約1.5微米或約6微米，但可使用其他厚度T3。在一些情況下，本文描述的實施例製程可減小表面介電層126的厚度多達約50%。藉由減小表面介電層126的厚度，可減小接合墊128的高度，從而可降低接合墊128的電阻且改良裝置的電氣效能。另外，藉由形成如本文所描述的更薄的表面介電層126，可減小導電接墊118上方的所有介電層的合併厚度（例如表面介電層126、第一終止層120以及第二終止層124的合併厚度）。以此方式減小介電層的合併厚度可降低（例如跨介電層）對熱傳導的阻隔，且可改良裝置的熱效能。更薄的表面介電層126亦可降低不合需要的電容效應。具有更薄的表面介電層126亦可減小最終裝置或封裝的總厚度。
圖13至圖17示出根據一些實施例的在裝置結構150的形成中的中間階段。圖13至圖17為在其中省略第二終止層124的第二實施例的剖面圖。藉由省略第二終止層124的形成，可減少製程步驟的數目。
轉向圖13，類似於圖6示出結構，其中已在第一終止層120上方形成介電層122。第一終止層120可類似於先前在圖5中所描述的終止層，且在一些實施例中可形成為具有在約500埃與約1500埃之間的厚度T4（諸如約500埃）。第一終止層120可形成為適合於終止或減緩下文在圖14中描述的平坦化製程的厚度。介電層122可為與先前在圖6中所描述類似的材料，且可以類似的方式形成。
在圖14中，使用第一終止層120對介電層122執行平坦化製程。如圖14中所示，第一終止層120的部分保留在導電接墊118上。在一些實施例中，保留在導電接墊118上的第一終止層120的厚度T5可在約100埃與約500埃之間，諸如約300埃。在圖14中所示的實施例中，由於下文圖16中所描述的圖14中所示的第一終止層120用作平坦化終止層且用作蝕刻終止層，保留的第一終止層120的厚度T5可大於圖7中所示的保留的第一終止層120的厚度T2。
轉向圖15，在第一終止層120上方形成表面介電層126，所述表面介電層可類似於先前在圖9中所描述的表面介電層126。在圖16中，在表面介電層126中形成開口127。可使用如先前所描述的可接受的微影及蝕刻技術來形成開口127。可使用第一終止層120作為蝕刻終止來形成開口127。開口127隨後可延伸穿過第一終止層120以暴露出導電接墊118。以此方式，第一終止層120被用作平坦化終止層及蝕刻終止層。
轉向圖17，接合墊128在開口127中形成以與導電接墊118進行電性連接。接合墊128可以如先前所描述的類似方式形成。以此方式，可使用單個終止層（第一終止層120）形成裝置結構150，且因此可使用較少製程步驟形成所述裝置結構。裝置結構150亦保留上文關於圖11所描述的更薄表面介電層126的益處。
圖18至圖21示出根據一些實施例的在裝置結構160的形成中的中間階段。圖18至圖21為第三實施例的剖面圖，在所述第三實施例中，可經由介電層122及鈍化層114形成接合墊通孔以將一些接合墊133電性連接至內連線結構108的金屬層線。除提供額外電性連接以外，接合墊通孔可提供經改良的熱傳導且因此改良裝置的熱效能。
轉向圖18，在第二終止層124上方形成表面介電層126，其可類似於先前在圖9中所描述的第二終止層124及表面介電層126。在一些實施例中，如圖18中所示，藉由第一終止層120及第二終止層124來包封介電層122的部分。在圖19中，在表面介電層126中形成第一開口131A。可使用如先前所描述的可接受的微影及蝕刻技術來形成第一開口131A。可使用第二終止層124及/或第一終止層120作為蝕刻停止層形成第一開口131A。第一開口131A隨後可延伸穿過第二終止層124及/或第一終止層120以暴露出導電接墊118。
轉向圖20，通孔開口131B形成為延伸穿過介電層122及鈍化層114。在不位於導電接墊118上方的開口131A的底部形成通孔開口131B。通孔開口131B暴露出用於電性連接的金屬層112。可使用可接受的微影及蝕刻技術來形成通孔開口131B。微影製程可包含以下步驟：在表面介電層126上方及第一開口131A中形成光阻（未示出）；圖案化光阻以具有對應於通孔開口131B的開口；使通孔開口131B延伸穿過光阻及穿過鈍化層114；以及隨後移除光阻。在一些實施例中，通孔開口131B可具有在約1微米與約3微米之間的較小寬度，或可具有在第一開口131A的寬度的約50%與約100%之間的寬度。
轉向圖21，在開口131A及開口131B中形成接合墊133A及通孔接合墊133B，以與導電接墊118及金屬線112進行電性連接。接合墊133A與導電接墊118進行電性連接，且通孔接合墊133B與金屬線112進行電性連接。接合墊133A及通孔接合墊133B可以類似於先前所描述的接合墊128的方式形成。以此方式，可使接合墊與內連線結構108進行額外電性連接件。在一些實施例中，接合通孔接墊133B中的一或多者可不電性連接，且可為用於降低負載及改良平坦度的「虛設」特徵。在一些實施例中，虛設通孔接合墊133B可連接至與內連線結構108隔離的金屬層線112。如圖21中所示，導電接墊118藉由第一終止層120及/或第二終止層124與表面介電層126分隔開。
根據一些實施例，轉向圖22，繪示包括兩個接合在一起的裝置結構的裝置封裝1000。裝置封裝1000包含第一裝置結構100及第二裝置結構200，所述裝置結構中的任一者或兩者可類似於先前所描述的裝置結構100、裝置結構150或裝置結構160。第一裝置結構100的接合墊128及表面介電層126接合至第二裝置結構200的接合墊228及表面介電層226。在一些實施例中，第一裝置結構100的接合墊128及第二裝置結構200的接合墊228為相同材料。在一些實施例中，第一裝置結構100的表面介電層126及第二裝置結構200的表面介電層226為相同材料。
在圖22中，使用例如直接接合或混合接合將第二裝置結構200接合至第一裝置結構100。在執行接合之前，可對第二裝置結構200或第一裝置結構100執行表面處理。在一些實施例中，表面處理包含電漿處理。電漿處理可在真空環境（例如真空腔室，未示出）中執行。用於產生電漿的製程氣體可為含氫氣的氣體，所述含氫氣的氣體包含：包含氫氣（H2 ）及氬氣（Ar）的第一氣體；包含H2 及氮氣（N2 ）的第二氣體；或包含H2 及氦氣（He）的第三氣體。亦可使用純的或實質上純的H2 、Ar或N2 用為製程氣體來執行電漿處理，所述電漿處理處理接合墊128或接合墊228及表面介電層126或表面介電層226的表面。第二裝置結構200或第一裝置結構100可以相同的表面處理製程或以不同的表面處理製程來處理。在一些實施例中，可在表面處理之後清洗第二裝置結構200或第一裝置結構100。清洗可包含執行化學品清洗及去離子水清洗/沖洗。
接著，可用第二裝置結構200及第一裝置結構100執行預接合製程。第二裝置結構200及第一裝置結構100經對準，其中第二裝置結構200的接合墊228對準至第一裝置結構100的接合墊128。在對準之後，第二裝置結構200及第一裝置結構100抵靠彼此按壓。按壓力在一些實施例中可為每晶粒小於約5牛頓，但亦可使用更大或更小的力。預接合製程可在室溫下（例如在約21℃至約25℃的溫度下）執行，但可使用更高溫度。舉例而言，預接合時間可小於約1分鐘。
在預接合之後，第二裝置結構200的表面介電層226及第一裝置結構100的表面介電層126彼此接合。接合界面在圖22及圖23中標記為「B」。第二裝置結構200及第一裝置結構100在下文組合地稱為裝置封裝1000。可在後續退火步驟中強化裝置封裝1000的接合。舉例而言，裝置封裝1000可在約300℃至約400℃的溫度下退火。舉例而言，可執行退火持續約1小時與約2小時之間的一段時間。在退火期間，接合墊128及接合墊228中的金屬可彼此擴散，使得亦形成金屬對金屬接合。因此，第二裝置結構200及第一裝置結構100的所得接合可為混合接合。在一些實施例中，在退火之後，在接合墊118及其對應的接合墊128之間無材料界面存在。
在一些實施例中，自第一裝置結構100的導電接墊118及第二裝置結構200的導電接墊218的距離在約1微米與約16微米之間，諸如約3微米或約12微米。在一些實施例中，自導電接墊118至界面B的距離不同於自導電接墊218至界面B的距離。在一些實施例中，一或多個接合墊128可沿界面B與其對應的接合墊228偏移。在一些實施例中，接合墊128及其對應的接合墊228可與導電接墊118、導電接墊228、內連線結構108及/或內連線結構208電隔離。完全電隔離的接合墊128或接合墊228可在某些情況下視為「虛設」導電特徵。在一些實施例中，一或多個接合墊128可電性連接至內連線結構108（例如類似於圖21中所示的通孔接合墊133B），且接合墊228中的一或多者可電性連接至內連線結構208。在一些實施例中，連接至導電接墊118的接合墊128可接合至未連接至導電接墊218的接合墊228。在一些實施例中，接合墊128或接合墊228可具有楔形輪廓，其中最大寬度靠近界面B。在一些實施例中，接合墊128可具有不同於接合墊228的寬度或輪廓。
轉向圖23，繪示裝置封裝1100。裝置封裝1100類似於裝置封裝1000，除了第三裝置結構300接合至第一裝置結構100以及第二裝置結構200以外。第三裝置結構300及第一裝置結構100可以與針對圖22所描述的類似方式接合。形成裝置封裝的所有此類變化涵蓋在本揭露的範疇內。在一些實施例中，可在接合之後對裝置封裝1000或裝置封裝1100執行單體化製程。
圖24至圖28示出根據一些實施例的在包含在裝置封裝1200的封裝1300的形成中的中間步驟。圖24示出在已接合於裝置封裝1200中的第四裝置結構400及第五裝置結構500。第四裝置結構400及第五裝置結構500可類似於先前所描述的裝置結構100、裝置結構150、裝置結構160、裝置結構200或裝置結構300，且裝置封裝1200可類似於先前所描述的裝置封裝1000或裝置封裝1100。
圖24亦示出載板基底721，所述載板基底721具有黏著層723及在黏著層723上方的聚合物層725。在一些實施例中，載板基底721包含例如諸如玻璃或氧化矽的基於矽的材料，或諸如氧化鋁的其他材料、這些材料中的任一者的組合或類似者。載板基底721可為平坦的以容納諸如接合對（bonded pair）的半導體裝置的附接件。將黏著層723放置於載板基底721上以便有助於上覆結構（例如聚合物層725）的黏附。在一些實施例中，黏著層723可包含光熱轉換（light to heat conversion；LTHC）材料或紫外線膠，所述黏著層在暴露於紫外光時失去其黏著特性。然而，亦可使用其他類型的黏著劑，諸如壓敏黏著劑、可輻射固化黏著劑、環氧化物、這些的組合或類似者。可將成半液體或凝膠形式的黏著層723放置至載板基底721上，所述黏著層在壓力下可容易變形。
將聚合物層725放置於黏著層723上方，且使用所述聚合物層以提供對例如接合對的保護。在一些實施例中，聚合物層725可為聚苯并噁唑（PBO），但可替代性地使用任何適合的材料，諸如聚醯亞胺或聚醯亞胺衍生物。可使用例如旋塗製程將聚合物層725放置為在約2微米與約15微米之間的厚度，諸如約5微米，但可替代地使用任何適合的方法及厚度。將接合對附接至該聚合物層725上。在一些實施例中，可使用例如取放製程放置接合對。然而，可使用放置接合對的任何適合的方法。
在一些實施例中，在聚合物層725上方形成諸如介電穿孔（through-dielectric vias；TDV）727的穿孔。在一些實施例中，晶種層（未示出）首先在聚合物層725上方形成。晶種層為導電材料的薄層，所述晶種層有助於在後續處理步驟期間形成較厚層。在一些實施例中，晶種層可包含約500埃厚的鈦層，隨後約3,000埃厚的銅層。視所需材料而定，可使用諸如濺鍍、蒸發或PECVD製程的製程來產生晶種層。一旦形成晶種層，則可在晶種層上方形成並圖案化光阻（未示出）。隨後在經圖案化的光阻內形成TDV 727。在一些實施例中，TDV 727包含一或多種導電材料，諸如銅、鎢、其他導電金屬或類似者，且可例如藉由電鍍、無電式電鍍或類似者而形成。在一些實施例中，使用電鍍製程，其中將晶種層及光阻浸沒或浸入於電鍍溶液中。一旦已使用光阻及晶種層形成TDV 727，則可使用適合的移除製程移除光阻。在一些實施例中，可使用電漿灰化製程來移除光阻，藉此可升高光阻的溫度直至光阻經歷熱分解且可經移除為止。然而，可替代性地使用任何其他適合的製程，諸如濕式剝離。移除光阻可暴露出晶種層的底層部分。一旦已形成TDV 727，則隨後例如使用濕式蝕刻製程或乾式蝕刻製程來移除晶種層的暴露部分。TDV 727可形成為在約180微米與約200微米之間的高度，所述TDV具有約190微米的臨界尺寸及約300微米的間距。
圖25示出用包封體729包封接合對及TDV 727。包封體729可為模製化合物，諸如樹脂、聚醯亞胺、PPS、PEEK、PES、耐熱性晶體樹脂、這些的組合或類似者。圖26示出包封體729的薄化以便暴露出TDV 727及接合對。可例如使用CMP製程或另一種製程來執行薄化。
圖27示出具有一或多個層的重佈線結構800在包封體729上方的形成。在一些實施例中，可藉由首先在包封體729上方形成第一重佈線鈍化層801來形成重佈線結構800。在一些實施例中，第一重佈線鈍化層801可為聚苯并噁唑（PBO），但可替代性地使用任何適合的材料，諸如聚醯亞胺或聚醯亞胺衍生物，諸如低溫固化聚醯亞胺。可使用例如旋塗製程將第一重佈線鈍化層801放置為在約5微米與約17微米之間的厚度，諸如約7微米，但可替代地使用任何適合的方法及厚度。
一旦已形成第一重佈線鈍化層801，則可形成穿過第一重佈線鈍化層801的第一重佈線通孔803以便與接合對及TDV 727進行電性連接。在一些實施例中，可藉由使用金屬鑲嵌製程、雙金屬鑲嵌製程或另一種製程來形成第一重佈線通孔803。在已形成第一重佈線通孔803之後，第一重佈線層805在第一重佈線通孔803上方形成且與所述第一重佈線通孔電性連接。在一些實施例中，可藉由首先經由適合的形成製程（諸如CVD或濺鍍）形成鈦銅合金的晶種層（未示出）來形成第一重佈線層805。可隨後形成光阻（亦未示出）以覆蓋晶種層，且光阻可隨後經圖案化以暴露出晶種層的位於第一重佈線層805期望定位的位置的那些部分。
一旦光阻已形成且經圖案化，則諸如銅的導電材料可經由諸如鍍覆的沉積製程在晶種層上形成。導電材料可形成為具有約1微米與約10微米之間的厚度，諸如約4微米。然而，雖然所論述的材料及方法適合於形成導電材料，但這些材料僅為例示性的。可替代地使用諸如AlCu或Au的任何其他適合的材料及諸如CVD或PVD的任何其他適合的形成製程以形成第一重線佈層805。
在已形成第一重佈線層805之後，可形成並圖案化第二重佈線鈍化層807以幫助隔離第一重佈線層805。在一些實施例中，第二重佈線鈍化層807可類似於第一重佈線鈍化層801，諸如為正型PBO，或可不同於第一重佈線鈍化層801，諸如為負型材料（諸如低溫固化聚醯亞胺）。第二重佈鈍化層807可放置為具有約7微米的厚度。一旦處於適當位置，則可使用例如微影罩幕及蝕刻製程來圖案化第二重佈線鈍化層807以形成開口，或若第二重佈線鈍化層807的材料為感光性的，則暴露第二重佈線鈍化層807的材料且使所述材料顯影。然而，可使用任何適合的材料及圖案化方法。
在第二重佈線鈍化層807已經圖案化之後，第二重佈線層809可形成為延伸穿過第二重佈線鈍化層807內形成的開口且與第一重佈線層805進行電性連接。在一些實施例中，可使用類似於第一重佈線層805的材料及製程來形成第二重佈線層809。舉例而言，可藉由經圖案化的光阻塗覆且覆蓋晶種層，諸如銅的導電材料可塗覆至晶種層上，可移除經圖案化的光阻，且可使用導電材料作為罩幕來蝕刻晶種層。在一些實施例中，第二重佈線層809形成為約4微米的厚度。然而，可使用任何適合的材料或製造製程。
在已形成第二重佈線層809之後，在第二重佈線層809上方塗覆第三重佈線鈍化層811以便幫助隔離及保護第二重佈線層809。在一些實施例中，第三重佈線鈍化層811可由與第二重佈線鈍化層807類似的材料且以類似方式形成為約7微米的厚度。舉例而言，第三重佈線鈍化層811可由已如上文關於第二重佈線鈍化層807所描述的經塗覆且經圖案化的PBO或低溫固化的聚醯亞胺形成。然而，可使用任何適合的材料或製造製程。
在第三重佈線鈍化層811已經圖案化之後，第三重佈線層813可形成為延伸穿過第三重佈線鈍化層811內形成的開口且與第二重佈線層809進行電性連接。在一些實施例中，可使用類似於第一重佈線層805的材料及製程來形成第三重佈線層813。舉例而言，可藉由經圖案化的光阻塗覆且覆蓋晶種層，諸如銅的導電材料可塗覆至晶種層上，可移除經圖案化的光阻，且可使用導電材料作為罩幕來蝕刻晶種層。在一些實施例中，第三重佈線層813形成為約5微米的厚度。然而，可使用任何適合的材料或製造製程。
在已形成第三重佈線層813之後，可在第三重佈線層813上方形成第四重佈線鈍化層815以便幫助隔離及保護第三重佈線層813。在一些實施例中，第四重佈線鈍化層815可由與第二重佈線鈍化層807類似的材料及以類似方式形成。舉例而言，第四重佈線鈍化層815可由已如上文關於第二重佈線鈍化層807所描述的經塗覆且經圖案化的PBO或低溫固化的聚醯亞胺形成。在一些實施例中，第四重佈線鈍化層815形成為約8微米的厚度。然而，可使用任何適合的材料或製造製程。
在其他實施例中，可使用諸如雙金屬鑲嵌製程的金屬鑲嵌製程形成重佈線結構800的重佈線通孔及重佈線層。舉例而言，可在包封體729上方形成第一重佈線鈍化層。隨後使用一或多個微影步驟使第一重佈線鈍化層圖案化以在第一重佈線鈍化層內形成通孔的開口及導電線的開口兩者。導電材料可在通孔的開口及導電線的開口中形成，以形成第一重佈線通孔及第一重佈線層。額外重佈線鈍化層可在第一重佈線鈍化層上方形成，且重佈線通孔及導電線的額外集合可在如針對第一重佈線鈍化層所描述的額外重佈線鈍化層中形成，從而形成重佈線結構800。可使用此技術或其他技術來形成重佈線結構800。
圖27另外示出形成凸塊下金屬化物819及第三外部連接件817以與第三重佈線層813進行電接觸。在一些實施例中，凸塊下金屬化物819可各自包括三個導電材料層，諸如鈦層、銅層以及鎳層。然而，所屬領域中具通常知識者將認識到，存在適用於形成凸塊下金屬化物819的許多適合的材料及層佈置，諸如鉻/鉻銅合金/銅/金的佈置、鈦/鈦鎢/銅的佈置或銅/鎳/金的佈置。可用於凸塊下金屬化物819的任何適合的材料或材料層完全意欲包含於實施例的範疇內。
在一些實施例中，凸塊下金屬化物819藉由在第三重佈線層813上方且沿穿過第四重佈線鈍化層815的開口內部形成各層來產生。可使用諸如電化學鍍覆的鍍覆製程來執行各層的形成，但可取決於所需材料使用其他的形成製程，諸如濺鍍、蒸發或PECVD製程。凸塊下金屬化物819可形成為具有在約0.7微米至約10微米之間的厚度，諸如約5微米。
在一些實施例中，第三外部連接件817可被放置在凸塊下金屬化物819上，且可為包括諸如焊料的共熔材料的球柵陣列封裝（ball grid array；BGA），但可替代地使用任何適合的材料。在第三外部連接件817為焊料球的一些實施例中，可使用諸如直接落球製程的落球方法來形成第三外部連接件817。在另一實施例中，可藉由首先經由諸如蒸發、電鍍、印刷、焊料轉移的任何適合方法形成錫層，且隨後執行回焊以便使材料形成為所需凸塊形狀來形成焊料球。一旦已形成第三外部連接件817，則可執行測試以確保結構適用於進一步處理。
圖28示出經由聚合物層725的封裝700至TDV 727的接合。在接合封裝700之前，載板基底721及黏著層723自聚合物層725移除。亦使聚合物層725圖案化以暴露出TDV 727。在一些實施例中，可使用例如雷射鑽孔方法使聚合物層725圖案化。在此方法中，諸如光熱轉換（LTHC）層或水溶性保護膜（hogomax）層（未分別示出）的保護層首先沉積於聚合物層725上方。一旦受保護，則將雷射導向聚合物層725的需要移除以便暴露出底層TDV 727的那些部分。在雷射鑽孔製程期間，鑽孔能量可在0.1毫焦至約30毫焦的範圍內，且相對於聚合物層725的法線的鑽孔角度為約0度（垂直於聚合物層725）至約85度。在一些實施例中，可形成圖案化以在TDV 727上方形成具有在約100微米與約300微米之間（諸如約200微米）的寬度的開口。
在另一實施例中，可藉由以下步驟來使聚合物層725圖案化：首先將光阻（未單獨示出）塗覆於聚合物層725，及隨後使光阻暴露於圖案化能量源（例如圖案化光源）以便誘發化學反應，藉此在光阻暴露於圖案化光源的那些部分中誘發物理變化。顯影劑隨後塗覆至經暴露的光阻以利用物理變化且取決於所要圖案而選擇性地移除光阻的暴露部分或光阻的未暴露部分，且聚合物層725的底層暴露部分用例如乾式蝕刻製程來移除。然而，可使用任何其他適合的方法來圖案化聚合物層725。
在一些實施例中，封裝700包含基底702及耦接至基底702的一或多個堆疊晶粒710（晶粒710A及晶粒710B）。儘管示出一組堆疊晶粒710（晶粒710A及晶粒710B），但在其他實施例中，多個堆疊晶粒710（各自具有一或多個堆疊晶粒）可並列安置為耦接至基底702的相同表面。基底702可由半導體材料製成，所述半導體材料諸如矽、鍺、金剛石或類似者。在一些實施例中，亦可使用化合物材料，諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、矽鍺碳化物、磷化砷化鎵、磷化鎵銦、這些的組合以及類似者。另外，基底702可為絕緣層上矽（silicon-on-insulator；SOI）基底。大體而言，SOI基底包含半導體材料層，諸如磊晶矽、鍺、矽鍺、SOI、絕緣層上矽鍺（silicon germanium on insulator；SGOI）或其組合。在一個替代實施例中，基底702是基於諸如玻璃纖維加固樹脂芯的絕緣芯。一種實例芯材為諸如FR4的玻璃纖維樹脂。芯材的替代物包含雙馬來亞醯胺-三嗪（bismaleimide-triazine；BT）樹脂，或可替代地包含其他印刷電路板（printed circuit board；PCB）材料或膜。諸如味素累積膜（Ajinomoto build-up film；ABF）的累積膜或其他層壓物可用於基底702。
基底702可包含主動裝置及被動裝置（未示出）。諸如電晶體、電容器、電阻器、這些的組合以及類似者的廣泛多種裝置可用於產生封裝700的設計的結構性及功能性要求。可使用任何適合的方法來形成裝置。
基底702亦可包含金屬化層或導電通孔（未示出）。金屬化層可在主動裝置及被動裝置上方形成，且經設計以連接各種裝置以形成功能性電路。金屬化層可由介電材料（例如低介電常數介電材料）與導電材料（例如銅）的交替層形成，其中通孔使導電材料層互連，且可經由任何適合的製程（諸如沉積、鑲嵌、雙鑲嵌或類似製程）來形成。在一些實施例中，基底702實質上不含主動裝置及被動裝置。
基底702可在基底702的第一側上具有接合墊704以耦接至堆疊晶粒710，且在基底702的第二側上具有接合墊706以耦接至外部連接件901，基底702的第二側與第一側相對。在一些實施例中，藉由在基底702的第一側及第二側上將凹部（未示出）形成於介電層（未示出）中來形成接合墊704以及接合墊706。可形成凹部以允許接合墊704及接合墊706嵌入於介電層中。在其他實施例中，省略凹部，這是因為接合墊704及接合墊706可在介電層上形成。在一些實施例中，接合墊704及接合墊706包含由銅、鈦、鎳、金、鈀、類似者或其組合製成的薄晶種層（未示出）。接合墊704及接合墊706的導電材料可沉積於薄晶種層上方。導電材料可藉由電化學鍍覆製程、無電式鍍覆製程、CVD、原子層沉積（atomic layer deposition；ALD）、PVD、類似者或其組合形成。在一實施例中，接合墊704及接合墊706的導電材料為銅、鎢、鋁、銀、金、類似者、或其組合。
在一實施例中，接合墊704及接合墊706為包含三個導電材料層（諸如鈦層、銅層以及鎳層）的UBM。可使用材料及層的其他佈置，諸如鉻/鉻銅合金/銅/金的佈置、鈦/鈦鎢/銅的佈置或銅/鎳/金的佈置來形成接合墊704及接合墊706。可用於接合墊704及接合墊706的任何適合的材料或材料層全部意欲包含於當前申請案的範疇內。在一些實施例中，導電通孔延伸穿過基底702且將接合墊704中的至少一者耦接至接合墊706中的至少一者。
在所示出的實施例中，堆疊晶粒710藉由電線接合712耦接至基底702，但可使用其他連接件，諸如導電凸塊。在一實施例中，堆疊晶粒710為堆疊記憶體晶粒。舉例而言，堆疊晶粒710可為諸如低功率（low-power；LP）雙資料速率（double data rate；DDR）記憶體模組的記憶體晶粒，所述記憶體模組諸如LPDDR1、LPDDR2、LPDDR3、LPDDR4或類似記憶體模組。
堆疊晶粒710及電線接合712可由模製材料714包封。可例如使用壓縮模製將模製材料714模製於堆疊晶粒710及電線接合712上。在一些實施例中，模製材料714為模製化合物、聚合物、環氧樹脂、氧化矽填充物材料、類似者或其組合。可執行固化製程以固化模製材料714。固化製程可為熱固化、UV固化、類似者或其組合。
在一些實施例中，堆疊晶粒710及電線接合712內埋於模製材料714中，且在固化模製材料714之後，執行諸如研磨的平坦化步驟以移除模製材料714的過量部分且為封裝700提供實質上平坦的表面。
在一些實施例中，可形成外部連接件901以在封裝700與例如TDV 727之間提供外部連接。外部連接件901可為觸點凸塊，諸如微凸塊或受控塌陷晶粒連接（controlled collapse chip connection；C4）凸塊，且可包括諸如錫的材料，或諸如銀或銅的其他適合的材料。在外部連接件901為錫焊料凸塊的一些實施例中，外部連接件901可藉由首先經由任何適合的方法（諸如蒸發、電鍍、印刷、焊料轉移、植球等）形成例如約100微米厚度的錫層來形成。一旦錫層已形成於結構上，則執行回焊以便將材料塑形成所需凸塊形狀。
一旦已形成外部連接件901，則將外部連接件901與TDV 727對準且放置於TDV上方，並執行接合。舉例而言，在外部連接件901為焊料凸塊的一些實施例中，接合製程可包括回焊製程，藉此外部連接件901的溫度升高至外部連接件901將液化及流動的點，由此在外部連接件901再固化時將封裝700接合至TDV 727。可形成包封體903以包封及保護封裝700。包封體903可在聚合物層725與封裝700之間延伸，且在一些實施例中可為底膠。以此方式，可形成封裝1300。
實施例可達成優點。藉由使用導電接墊上方的平坦化終止層，平坦化製程可接近導電接墊的頂表面終止。此可使得形成更薄表面介電層（例如，「接合氧化物」）。藉由減小表面介電層的厚度，可減小含有裝置的封裝的總厚度。另外，更薄表面介電層提供經改良的熱傳導且因此可改良裝置的熱效能。
在一實施例中，一種裝置包含：內連線結構，在基底上方；多個第一導電接墊，在內連線結構上方且連接至所述內連線結構；平坦化終止層，在多個第一導電接墊中的第一導電接墊的側壁及頂表面上方延伸；表面介電層，在平坦化終止層上方延伸；以及多個第一接合墊，在表面介電層內且連接至多個第一導電接墊。在一實施例中，裝置包含在平坦化終止層上方延伸的蝕刻終止層，表面介電層所述蝕刻終止層上。在一實施例中，裝置包含在平坦化終止層與蝕刻終止層之間的第一介電層。在一實施例中，多個接合墊延伸穿過平坦化終止層及蝕刻終止層。在一實施例中，平坦化終止層包含碳化矽。在一實施例中，表面介電層具有在6微米與8微米之間的厚度。在一實施例中，裝置包含在內連線結構與多個第一導電接墊之間的第二介電層，其中平坦化終止層在第二介電層的頂表面上方延伸。在一實施例中，裝置包含在內連線結構上方的多個第二導電接墊，且包含多個第二接合墊，所述第二接合墊在表面介電層內且連接至多個第二導電接墊，其中第二導電接墊與內連線結構隔離。在一實施例中，多個第一導電接墊包含鋁。
在一實施例中，一種方法包含以下步驟：在內連線結構中形成第一金屬線；在內連線結構上方形成絕緣層；在絕緣層上方形成導電元件，導電元件延伸穿過絕緣層至第一金屬線；形成第一終止層，所述第一終止層在絕緣層上方延伸且在導電元件的側壁及頂表面上方延伸；在第一終止層上方形成第二絕緣層；使用第一終止層作物平坦化終止層對第二絕緣層執行平坦化製程；在第一終止層上方形成第二終止層，其中第二終止層與第二絕緣層的頂表面物理接觸，且與第一終止層的頂表面物理接觸；在第二終止層上方形成接合氧化層；以及在接合氧化層中形成第一接合墊。在一實施例中，在執行平坦化製程之後，在絕緣層上方的第一終止層的第一厚度大於在導電元件上方的第一終止層的第二厚度。在一實施例中，在接合氧化層中形成接合墊包含使用第二終止層作為蝕刻終止在接合氧化層中蝕刻開口。且在第一終止層中蝕刻開口以暴露出導電元件。在一實施例中，在接合氧化層中形成接合墊包含使用第二終止層作為蝕刻終止，在接合氧化層中蝕刻開口以暴露出第二絕緣層。在一實施例中，方法包含使接合氧化層中的開口延伸穿過第二絕緣層以暴露出內連線結構中的第二金屬線。
在一實施例中，一種裝置包含內連線結構，在半導體基底上方；多個導電接墊，在內連線結構上方且連接至所述內連線結構；第一蝕刻終止層，在多個導電接墊上方；介電層，在第一蝕刻終止層上方且環繞導電接墊，介電層的頂表面與第一蝕刻終止層的頂表面共面；接合層，在第一蝕刻終止層及介電層上方；以及接合層中的多個接合墊，多個接合墊連接至多個導電接墊。在一實施例中，裝置包含在第一蝕刻終止層及介電層上方的第二蝕刻終止層。在一實施例中，第二蝕刻終止層的材料與第一蝕刻終止層的材料相同。在一實施例中，裝置包含接合至多個接合墊及接合層的頂部封裝。在一實施例中，第一蝕刻終止層在多個導電接墊中的導電接墊的側壁上延伸。在一實施例中，至少一個接合墊自多個導電接墊上方延伸至多個導電接墊上方。
前文概述若干實施例的特徵，以使得在所屬領域中具通常知識者可較好地理解本揭露的態樣。所屬領域中具通常知識者應瞭解，其可易於使用本揭露作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。所屬領域中具通常知識者亦應認識到，此類等效構造並不脫離本揭露的精神及範疇，且所屬領域中具通常知識者可在不脫離本揭露的精神及範疇的情況下在本文中作出各種改變、替代以及更改。
100、150、160、200、300、400、500:裝置結構 102、702:基底 104、122:介電層 106:接觸插塞 108、208:內連線結構 110:絕緣層 112:金屬線 113:通孔 114:鈍化層 116、127、127A:開口 118、118D、218:導電接墊 120:第一終止層 124:第二終止層 126、226:表面介電層 128、128D、133A、228、704、706:接合墊 131A:第一開口 131B:通孔開口 133B:通孔接合墊 700、1300:封裝 710、710A、710B:堆疊晶粒 712:電線接合 714:模製材料 721:載板基底 723:黏著層 725:聚合物層 727:介電穿孔 729、903:包封體 800:重佈線結構 801:第一重佈線鈍化層 803:第一重佈線通孔 805:第一重佈線層 807:第二重佈線鈍化層 809:第二重佈線層 811:第三重佈線鈍化層 813:第三重佈線層 815:第四重佈線鈍化層 817:第三外部連接件 819:凸塊下金屬化物 901:外部連接件 1000、1100、1200:裝置封裝 B:接合界面 T1、T2、T3、T4、T5:厚度 W:寬度
結合隨附圖式閱讀以下詳細描述最佳地理解本揭露的各態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，為論述清楚起見，可任意增大或減小各種特徵的尺寸。 圖1A至圖11示出根據一些實施例的在用於形成裝置結構的製程中的中間步驟的剖面圖。 圖12示出根據一些實施例的在用於形成另一種裝置結構的製程中的中間步驟的剖面圖。 圖13至圖17示出根據一些實施例的在用於形成另一種裝置結構的製程中的中間步驟的剖面圖。 圖18至圖21示出根據一些實施例的在用於形成另一種裝置結構的製程中的中間步驟的剖面圖。 圖22示出根據一些實施例的在用於形成裝置封裝的製程中的中間步驟的剖面圖。 圖23示出根據一些實施例的在用於形成另一種裝置封裝的製程中的中間步驟的剖面圖。 圖24至圖28示出根據一些實施例的在用於形成封裝的製程中的中間步驟的剖面圖。
102:基底
104、122:介電層
106:接觸插塞
108:內連線結構
110:絕緣層
112:金屬線
113:通孔
114:鈍化層
118、118D:導電接墊
120:第一終止層
124:第二終止層
126:表面介電層
128、128D:接合墊

Claims (20)

  1. 一種接合結構，包括： 內連線結構，在基底上方； 多個第一導電接墊，在所述內連線結構上方且連接至所述內連線結構； 平坦化終止層，在所述多個第一導電接墊中的所述第一導電接墊的側壁及頂表面上方延伸； 表面介電層，在所述平坦化終止層上方延伸；以及 多個第一接合墊，在所述表面介電層內且連接至所述多個第一導電接墊。
  2. 如申請專利範圍第1項所述的接合結構，更包括在所述平坦化終止層上方延伸的蝕刻終止層，所述表面介電層在所述蝕刻終止層上。
  3. 如申請專利範圍第2項所述的接合結構，更包括在所述平坦化終止層與所述蝕刻終止層之間的第一介電層。
  4. 如申請專利範圍第2項所述的接合結構，其中所述多個接合墊延伸穿過所述平坦化終止層及所述蝕刻終止層。
  5. 如申請專利範圍第1項所述的接合結構，其中所述平坦化終止層包括碳化矽。
  6. 如申請專利範圍第1項所述的接合結構，其中所述表面介電層具有在6微米與8微米之間的厚度。
  7. 如申請專利範圍第1項所述的接合結構，更包括在所述內連線結構與所述多個第一導電接墊之間的第二介電層，其中所述平坦化終止層在所述第二介電層的頂表面上方延伸。
  8. 如申請專利範圍第1項所述的接合結構，更包括在所述內連線結構上方的多個第二導電接墊，且更包括在所述表面介電層內且連接至所述多個第二導電接墊的多個第二接合墊，其中所述第二導電接墊與所述內連線結構隔離。
  9. 如申請專利範圍第1項所述的接合結構，其中所述多個第一導電接墊包括鋁。
  10. 一種接合結構的形成方法，包括： 在內連線結構中形成第一金屬線； 在所述內連線結構上方形成絕緣層； 在所述絕緣層上方形成導電元件，所述導電元件延伸穿過所述絕緣層至所述第一金屬線； 形成第一終止層，所述第一終止層在所述絕緣層上方延伸且在所述導電元件的側壁及頂表面上方延伸； 在所述第一終止層上方形成第二絕緣層； 使用所述第一終止層作為平坦化終止層來對所述第二絕緣層執行平坦化製程； 在所述第一終止層上方形成第二終止層，其中所述第二終止層與所述第二絕緣層的頂表面物理接觸，且與所述第一終止層的頂表面物理接觸； 在所述第二終止層上方形成接合氧化層；以及 在所述接合氧化層中形成第一接合墊。
  11. 如申請專利範圍第10項所述的接合結構的形成方法，更包括： 其中，在執行所述平坦化製程之後，在所述絕緣層上方的所述第一終止層的第一厚度大於在所述導電元件上方的所述第一終止層的第二厚度。
  12. 如申請專利範圍第10項所述的接合結構的形成方法，其中在所述接合氧化層中形成接合墊包括： 使用所述第二終止層作為蝕刻終止層來在所述接合氧化層中蝕刻開口；以及 在所述第一終止層中蝕刻開口以暴露出所述導電元件。
  13. 如申請專利範圍第10項所述的接合結構的形成方法，其中在所述接合氧化層中形成接合墊包括： 使用所述第二終止層作為蝕刻終止，在所述接合氧化層中蝕刻開口以暴露出所述第二絕緣層。
  14. 如申請專利範圍第13項所述的接合結構的形成方法，更包括使所述接合氧化層中的所述開口延伸穿過所述第二絕緣層，以暴露出所述內連線結構中的第二金屬線。
  15. 一種接合結構，包括： 內連線結構，在半導體基底上方； 多個導電接墊，在所述內連線結構上方且連接至所述內連線結構； 第一蝕刻終止層，在所述多個導電接墊上方； 介電層，在所述第一蝕刻終止層上方且環繞所述多個導電接墊中的所述導電接墊，所述介電層的頂表面與所述第一蝕刻終止層的頂表面共面； 接合層，在所述第一蝕刻終止層及所述介電層上方；以及 多個接合墊，在所述接合層中，所述多個接合墊連接至所述多個導電接墊。
  16. 如申請專利範圍第15項所述的接合結構，更包括在所述第一蝕刻終止層及所述介電層上方的第二蝕刻終止層。
  17. 如申請專利範圍第16項所述的接合結構，其中所述第二蝕刻終止層的材料與所述第一蝕刻終止層的材料相同。
  18. 如申請專利範圍第15項所述的接合結構，更包括接合至所述多個接合墊且接合至所述接合層的頂部封裝。
  19. 如申請專利範圍第15項所述的接合結構，其中所述第一蝕刻終止層在所述多個導電接墊中的所述導電接墊的側壁上延伸。
  20. 如申請專利範圍第15項所述的接合結構，其中至少一個接合墊自所述多個導電接墊上方延伸至所述多個導電接墊下方。
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