CN112420657A - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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Publication number
CN112420657A
CN112420657A CN202010354425.8A CN202010354425A CN112420657A CN 112420657 A CN112420657 A CN 112420657A CN 202010354425 A CN202010354425 A CN 202010354425A CN 112420657 A CN112420657 A CN 112420657A
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layer
stop layer
over
conductive
pads
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陈宪伟
陈洁
陈明发
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种器件包括：互连结构，位于衬底上方；多个第一导电焊盘，位于互连结构上方并且连接到互连结构；平坦化停止层，在多个第一导电焊盘的第一导电焊盘的侧壁和顶面上方延伸；表面介电层，在平坦化停止层上方延伸；以及多个第一接合焊盘，位于表面介电层内，并且连接到多个第一导电焊盘。本发明的实施例还涉及半导体器件及其形成方法。

Description

半导体器件及其形成方法
技术领域
本发明的实施例涉及半导体器件及其形成方法。
背景技术
在晶圆至晶圆接合技术中，已经开发了各种方法来将两个封装组件(诸如晶圆)接合在一起。一些晶圆接合方法包括熔融接合、共晶接合、直接金属接合、混合接合等。在熔融接合中，晶圆的氧化物表面接合到另一晶圆的氧化物表面或硅表面。在共晶接合中，将两种共晶材料放在一起，并施加高压和高温。因此共晶材料熔化。当熔化的共晶材料固化时，晶圆接合在一起。在直接金属至金属接合中，两个金属焊盘在升高的温度下彼此压靠，并且金属焊盘的相互扩散引起金属焊盘的接合。在混合接合中，两个晶圆的金属焊盘通过直接金属至金属接合彼此接合，并且两个晶圆之一的氧化物表面接合到另一晶圆的氧化物表面或硅表面。
发明内容
本发明的实施例提供了一种半导体器件，包括：互连结构，位于衬底上方；多个第一导电焊盘，位于所述互连结构上方并且连接到所述互连结构；平坦化停止层，在所述多个第一导电焊盘的第一导电焊盘的侧壁和顶面上方延伸；表面介电层，在所述平坦化停止层上方延伸；以及多个第一接合焊盘，位于所述表面介电层内，并且连接到所述多个第一导电焊盘。
本发明的另一实施例提供了一种形成半导体器件的方法，包括：在互连结构中形成第一金属线；在所述互连结构上方形成绝缘层；在所述绝缘层上方形成导电元件，所述导电元件穿过所述绝缘层延伸到所述第一金属线；形成第一停止层，所述第一停止层在所述绝缘层上方延伸并且在所述导电元件的侧壁和顶面上方延伸；在所述第一停止层上方形成第二绝缘层；使用所述第一停止层作为平坦化停止层，对所述第二绝缘层执行平坦化工艺；在所述第一停止层上方形成第二停止层，其中，所述第二停止层物理接触所述第二绝缘层的顶面并且物理接触所述第一停止层的顶面；在所述第二停止层上方形成接合氧化物层；以及在所述接合氧化物层中形成接合焊盘。
本发明的又一实施例提供了一种半导体器件，包括：互连结构，位于半导体衬底上方；多个导电焊盘，位于所述互连结构上方并且连接到所述互连结构；第一蚀刻停止层，位于所述多个导电焊盘上方；介电层，位于所述第一蚀刻停止层上方并且围绕所述多个导电焊盘的导电焊盘，所述介电层的顶面与所述第一蚀刻停止层的顶面共面；接合层，位于所述第一蚀刻停止层和所述介电层上方；以及多个接合焊盘，位于所述接合层中，所述多个接合焊盘连接到所述多个导电焊盘。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图11示出了根据一些实施例的用于形成器件结构的工艺中的中间步骤的截面图。
图12示出了根据一些实施例的用于形成另一器件结构的工艺中的中间步骤的截面图。
图13至图17示出了根据一些实施例的用于形成另一器件结构的工艺中的中间步骤的截面图。
图18至图21示出了根据一些实施例的用于形成另一器件结构的工艺中的中间步骤的截面图。
图22示出了根据一些实施例的用于形成器件封装件的工艺中的中间步骤的截面图。
图23示出了根据一些实施例的用于形成另一器件封装件的工艺中的中间步骤的截面图。
图24至图28示出了根据一些实施例的用于形成封装件的工艺中的中间步骤的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征不同的实施例或实例。下面描述了组件和布置的具体实施例或实例以简化本发明。当然这些仅是实例而不旨在限制。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。如本文使用的，在第二部件上形成第一部件是指形成与第二部件直接接触的第一部件。此外，本发明可以在各个示例中重复参考数字和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括器件在使用或操作工艺中的不同方位。装置可以以其它方式定位(旋转90度或在其它方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。
根据一些实施例，提供了一种接合结构和方法。在互连结构上方形成表面介电层，并且在表面介电层中形成接合焊盘。通过使用平坦化停止层，可以减小表面介电层的厚度。这可以提供整个表面介电层的增加的热传导，这可以允许在较高温度下改善的器件性能。另外，由于较薄的表面介电层，可以减小器件的整体尺寸。
图1至图12示出了根据一些实施例的器件结构100的形成中的中间阶段的截面图。图1示出了根据一些实施例的衬底102和在衬底102上方形成的部件。衬底102可以是半导体衬底，诸如体半导体，绝缘体上半导体(SOI)衬底、半导体晶圆等，它们可以是掺杂的(例如，具有p型或n型掺杂剂)或未掺杂的。通常，SOI衬底包括在绝缘体层上形成的半导体材料层。绝缘体层可以是例如掩埋氧化物(BOX)层、氧化硅层等。绝缘体层设置在衬底(通常是硅或玻璃衬底)上。也可以使用其他衬底，诸如多层或梯度衬底。在一些实施例中，衬底的半导体材料可以包括硅；锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。
在一些实施例中，衬底102和在其上形成的部件用于形成器件管芯。在这样的实施例中，集成电路器件可以形成在衬底102的顶面上。示例性集成电路器件可以包括互补金属氧化物半导体(CMOS)晶体管、鳍式场效应晶体管(FinFET)、电阻器、电容器、二极管等或它们的组合。这里未示出集成电路器件的细节。在一些实施例中，衬底102用于形成中介层结构。在这样的实施例中，在衬底102上不形成诸如晶体管或二极管的有源器件。可以在衬底102中形成诸如电容器、电阻器、电感器等的无源器件。在衬底102是中介层结构的部分的一些实施例中，衬底102也可以是介电衬底。在一些实施例中，可以形成延伸穿过衬底102的通孔(未示出)，以互连衬底102的相对侧上的组件。
在图1中，在衬底102上方形成介电层104。介电层104可以具有包括一种或多种材料的一个或多个层。在集成电路器件形成在衬底102上的实施例中，介电层104可以填充集成电路器件的晶体管(未示出)的栅极堆叠件之间的空间。在一些实施例中，介电层104可以是层间介电(ILD)层。介电层104可以由磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、氟掺杂的硅酸盐玻璃(FSG)、正硅酸乙酯(TEOS)等或它们的组合形成。在一些实施例中，介电层104可以包括由k值低于约3.0的低k介电材料形成的层。在一些实施例中，介电层104使用旋涂工艺形成或使用诸如等离子体增强化学气相沉积(PECVD)、可流动化学气相沉积(FCVD)、低压化学气相沉积(LPCVD)等的沉积方法形成。
此外，在图1中，接触插塞106形成在介电层104中。接触插塞106电连接到衬底102的集成电路器件。例如，接触插塞106可以是连接到集成电路器件的晶体管(未示出)的栅电极的栅极接触插塞，和/或可以是电连接到晶体管的源极/漏极区的源极/漏极接触插塞。在形成介电层104之后，穿过介电层104形成用于接触插塞106的开口。可以使用可接受的光刻和蚀刻技术形成开口。例如，可以在介电层上方形成光刻胶并图案化光刻胶，并且通过使用图案化的光刻胶作为蚀刻掩模，通过蚀刻介电层104来形成介电层104中的开口。可以使用合适的湿蚀刻工艺、干蚀刻工艺或它们的组合来蚀刻介电层104。在一些实施例中，可以在开口中形成诸如扩散阻挡层、粘附层等的衬垫，然后可以在衬垫上方的开口中形成导电材料。衬垫可以包括钛、氮化钛、钽、氮化钽等或它们的组合。导电材料可以包括钴、铜、铜合金、银、金、钨、铝、镍等或它们的组合。在形成导电材料之后，可以执行平坦化工艺，诸如研磨工艺、化学机械抛光(CMP)工艺等，以从介电层104的表面去除多余的材料。剩余的衬垫和导电材料因此形成接触插塞106。
在图2中，根据一些实施例，在接触插塞106和介电层104上方形成互连结构108。互连结构108提供在衬底102中形成的器件之间的布线和电连接，并且可以是再分布结构。互连结构108可以包括多个绝缘层110，绝缘层110可以是金属间介电(IMD)层。每个绝缘层110包括形成在其中的一条或多条金属线112和/或通孔113。金属线112和通孔113可以通过接触插塞106电连接到衬底102的有源和/或无源器件。金属线112可以是例如再分布层。
在一些实施例中，绝缘层110可以由k值低于约3.0的低k介电材料形成。绝缘层110可以由k值小于2.5的超低k(ELK)介电材料形成。在一些实施例中，绝缘层110可以由含氧和/或含碳的低k介电材料、氢倍半硅氧烷(HSQ)，甲基倍半硅氧烷(MSQ)等或它们的组合形成。在一些实施例中，绝缘层110中的一些或全部由非低k介电材料形成，诸如氧化硅、碳化硅(SiC)、碳氮化硅(SiCN)、碳氮氧化硅(SiOCN)等。在一些实施例中，可以由碳化硅、氮化硅等形成的蚀刻停止层(未示出)形成在绝缘层110之间。在一些实施例中，IMD层110由诸如SiOCN、SiCN、SiOC、SiOCH等的多孔材料形成，并且可以通过旋涂或诸如等离子体增强化学气相沉积(PECVD)、CVD、PVD等的沉积工艺形成。在一些实施例中，互连结构108可以包括一个或多个其他类型的层，诸如扩散阻挡层(未示出)。
在一些实施例中，可以使用单镶嵌和/或双镶嵌工艺、先通孔工艺或先金属工艺来形成互连结构108。在实施例中，形成绝缘层110，并使用可接受的光刻和蚀刻技术在其中形成开口(未示出)。扩散阻挡层(未示出)可以形成在开口中并且可以包括诸如TaN、Ta、TiN、Ti、CoW等的材料，并且可以通过诸如CVD、ALD等的沉积工艺形成在开口中。导电材料可以由铜、铝、镍、钨、钴、银、它们的组合等形成在开口中，并且可以通过电化学镀工艺、CVD、ALD、PVD等或它们的组合在开口中形成在扩散阻挡层上方。在形成导电材料之后，可以使用诸如CMP的平坦化工艺去除多余的导电材料，从而在最底部的IMD层110的开口中留下金属线112。然后可以重复该工艺以在其中形成额外的绝缘层110和金属线112以及通孔113。在一些实施例中，最顶部的绝缘层110和形成在其中的金属线112的厚度可以形成为大于互连结构108的其他绝缘层110的厚度。在一些实施例中，最顶部的金属线112中的一个或多个是与衬底102电隔离的伪线。
在图3中，在互连结构108上方形成钝化层114，并且在钝化层114中形成一个或多个开口116。钝化层114可以包括一种或多种材料的一个或多个层。例如，钝化层114可以包括一层或多层氮化硅、氧化硅、氮氧化硅等或它们的组合。钝化层114可以通过合适的工艺形成，诸如CVD、PECVD、PVD、ALD等或它们的组合。可以形成钝化层114，钝化层114的厚度大于最顶部绝缘层110的厚度。
可以使用合适的光刻和蚀刻工艺来形成钝化层114中的开口116。例如，可以在钝化层114上方形成光刻胶并图案化光刻胶，然后将图案化的光刻胶用作蚀刻掩模。可以使用合适的湿蚀刻工艺和/或干蚀刻工艺蚀刻钝化层114。形成开口116以暴露金属层112的部分(例如，互连结构108的最顶部金属层112)以进行电连接。
在图4中，根据一些实施例，在钝化层114上方形成导电焊盘118。可以形成延伸穿过开口116并且与互连结构108的一个或多个最顶部金属线112电连接的一个或多个导电焊盘118。在一些实施例中，通过首先在钝化层114和开口116上方形成晶种层来形成导电焊盘118。在一些实施例中，晶种层是包括一个或多个层的金属层，其可以由不同的材料形成。可以使用例如物理气相沉积(PVD)等形成晶种层。在晶种层上形成并图案化光刻胶，并且在光刻胶的开口中和晶种层的暴露部分上形成导电材料。在一些实施例中，导电材料可以通过镀工艺形成，诸如使用电镀或化学镀工艺等。导电材料可以包括一种或多种材料，诸如铜、钛、钨、金、钴、铝等或它们的组合。然后使用例如合适的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶和其上未形成导电材料的晶种层的部分。一旦去除了光刻胶，就可以使用可接受的蚀刻工艺(诸如湿蚀刻工艺或干蚀刻工艺)去除晶种层的剩余暴露部分。晶种层的剩余部分和导电材料形成导电焊盘118。
在一些实施例中，可以通过首先沉积导电材料的毯状层来形成导电焊盘118。例如，可以使用CVD、PVD等在钝化层114和开口116上方以及金属层112上方沉积铝层。然后可以在铝层上方形成光刻胶层(未单独示出)，可以蚀刻铝层以形成导电焊盘118。在其他实施例中可以使用其他技术形成导电焊盘118，并且所有这些技术都被认为在本发明的范围内。
在一些实施例中，电连接到互连结构108的导电焊盘118可以在执行附加处理步骤之前用作测试焊盘。例如，可以探测导电焊盘118，作为晶圆验收测试、电路测试、已知良好芯片(KGD)测试等的一部分。可以执行探测以验证衬底102的有源或无源器件或衬底102或互连结构108(例如，金属线112或通孔113)内的相应电连接的功能。可以通过将探针(未示出)接触导电焊盘118来执行探测。探针可以是包括多个探针的探针卡的一部分，探针例如可以连接到测试设备。
在一些实施例中，导电焊盘118的导电材料可以与金属线112的导电材料不同。例如，导电焊盘118可以是铝，金属线112可以是铜，但是可以使用其他导电材料。在一些实施例中，导电焊盘118可具有介于约2μm与约30μm之间的宽度W或介于约20μm与约100μm之间的长度(例如，垂直于宽度)。在一些实施例中，导电焊盘118可具有介于约500nm与约3000nm之间的厚度。在一些情况下，较厚的导电焊盘118在被探测时可能具有较小的损坏风险。这样，导电焊盘118可以具有比金属线112更大的厚度。为了减小探测期间损坏的可能性，导电焊盘118也可以由比金属线112的导电材料(例如，铜)不太柔软的导电材料(例如，铝)形成。本发明中描述的实施例可以允许使用更大厚度的导电焊盘118而不增加结构(例如，器件结构100)的总厚度。
转到图5，根据一些实施例，在导电焊盘118和钝化层114上方形成第一停止层120。在一些实施例中，第一停止层120可以用作后续CMP工艺的停止层(参见图7)。第一停止层120可以包括介电材料，诸如碳化硅、碳氧化硅、氮化硅、氧化硅等或它们的组合。可以使用诸如CVD、PVD、ALD等工艺来形成第一停止层120。第一停止层120沉积在导电焊盘118的顶面上方，并且可以共形地沉积在钝化层114和导电焊盘118的顶面上方以及导电焊盘118的侧壁上方。在一些实施例中，第一停止层120可以形成为具有在约300埃到约1500埃之间的厚度T1。第一停止层120可以形成为适合于停止或减慢下面在图7中描述的平坦化工艺的厚度。在一些情况下，可以使用较厚的第一停止层120来避免在下面描述的平坦化工艺期间暴露导电焊盘118。在一些实施例中，第一停止层120还用作蚀刻停止(参见例如图10和图16)，并且可以选择第一停止层120的厚度，使得第一停止层120的足够厚度在平坦化之后保留以用作蚀刻停止。
转到图6，在第一停止层120上方形成介电层122。介电层122可以由一种或多种介电材料的一层或多层形成，诸如氧化硅、氮化硅、SiOCH、SiCH等或它们的组合。介电层122可以通过诸如CVD、PECVD、PVD、ALD等的沉积工艺或它们的组合形成。在一些实施例中，介电层122和第一停止层120由不同的介电材料制成。介电层122可以形成为具有大于导电焊盘118的厚度的厚度，使得介电层122的材料横向围绕导电焊盘118，并且使得介电层122可以被平坦化(参见下文)而不暴露导电焊盘118。
在图7中，对介电层122执行平坦化工艺。平坦化工艺可以是例如CMP工艺。第一停止层120用于停止或减缓导电焊盘118的顶面附近的平坦化工艺。如图7所示，第一停止层120的一部分可以在执行平坦化工艺之后保留在导电焊盘118的顶面上方。在一些实施例中，保留在导电焊盘118上的第一停止层120的厚度T2可以在约100埃和约300埃之间，诸如约50埃和约150埃之间。在一些实施例中，T1与T2的比率可以在约3比1和约50比1之间。剩余的第一停止层120的厚度T2可以足够厚以保护导电焊盘118。在一些情况下，较小的厚度T2允许导电焊盘118与表面介电层126的顶面之间的较小总距离(参见例如图17)，这可以改善导热性并减小最终器件中的电容效应。在一些实施例中，第一停止层120的一部分可以保留在导电焊盘118上，以便随后用作蚀刻停止(参见例如图10)。在一些实施例中，可以控制平坦化工艺，使得剩余的第一停止层120的厚度T2可以足以用作蚀刻停止。
转到图8，在介电层122和第一停止层120上方形成第二停止层124。第二停止层124可以随后用作蚀刻停止层(参见图10)。在一些实施例中，第二停止层124是与第一停止层120相同的材料，但是在其他实施例中，第一停止层120和第二停止层124可以是不同的材料。第二停止层124可以包括诸如碳化硅、碳氧化硅、氮化硅、氧化硅等或它们的组合的材料。可以使用诸如CVD、PVD、ALD等工艺来形成第二停止层124。在一些情况下，第二停止层124的使用可以改善第二停止层124的表面的平坦性和后续工艺步骤期间的表面的平坦性。在一些实施例中，第二停止层124可以形成为具有在约150埃和约1500埃之间的厚度，诸如约300埃。在一些实施例中，第二停止层124的厚度可足以用作蚀刻停止(参见例如图10)。在一些情况下，较厚的第二停止层124可以改善第二停止层124的表面和随后形成的部件的平坦性。
转到图9，在第二停止层124上方形成表面介电层126。表面介电层126可以由一种或多种介电材料的一层或多层形成，并且可以包括含硅材料，诸如氧化硅、氧氮化硅、氮化硅等。在一些实施例中，表面介电层126和第二停止层124由不同的介电材料制成。表面介电层126可以通过诸如CVD、PECVD、PVD、ALD等的沉积工艺或它们的组合形成。在实施例中，表面介电层126包括氧化硅，并且可选地称为“接合氧化物”。
在图10中，根据一些实施例，在表面介电层126中形成开口127。可以使用可接受的光刻和蚀刻技术形成开口127。例如，光刻工艺可以包括在表面介电层126上方形成光刻胶(未示出)，用对应于开口127的开口图案化光刻胶，使焊盘开口127延伸穿过光刻胶并进入表面介电层126，以及然后去除光刻胶。光刻胶可以是单层光刻胶、双层光刻胶、三层光刻胶等。执行蚀刻工艺，使得蚀刻在第二停止层124上停止。可以执行额外的蚀刻工艺以使开口127延伸穿过第二停止层124。在第二停止层124位于第一停止层120上的一些区域中，开口127可以延伸穿过第二停止层124和第一停止层120。例如，在导电焊盘118上方的区域中，开口127可以延伸穿过第二停止层124和第一停止层120以暴露导电焊盘118的顶面。延伸穿过第二停止层124和第一停止层120的示例性开口在图10中被指定为开口127A。在一些实施例中，开口127可以具有在约1μm和约5μm之间的宽度，但是其他宽度也是可能的。在一些实施例中，开口127可以具有锥形轮廓，诸如具有在约1μm和约2μm之间的底部宽度和在约2μm和约5μm之间的顶部宽度。在一些情况下，开口127A的宽度可以在导电焊盘118的宽度W的约10％和约100％之间。以这种方式，开口127A的宽度可以使得可以在单个导电焊盘118上方形成多个开口127A。
转到图11，根据一些实施例，在开口127中形成接合焊盘128。接合焊盘128可以具有与形成它们的开口127类似的尺寸，并且可以具有类似的形状(例如，具有锥形轮廓)。接合焊盘128可以由包括金属或金属合金的导电材料形成，诸如铜、银、金、钨、钴、铝等或它们的组合。在一些实施例中，接合焊盘128和导电焊盘118可以是不同的导电材料。例如，接合焊盘128可以是铜，导电焊盘118可以是铝，但是其他材料也是可能的。在一些实施例中，接合焊盘128的形成包括在开口127中沉积晶种层(未示出)，晶种层可以包括铜、铜合金、钛等，然后使用例如电镀工艺、化学镀工艺等填充开口127的剩余部分。可以使用诸如CMP工艺的平坦化工艺从表面介电层126去除多余的导电材料和晶种层。图11中所示的工艺表示可用于形成接合焊盘128的示例工艺，并且其他工艺或技术可用于其他实施例中，诸如镶嵌工艺、双镶嵌工艺或另一工艺。形成在开口127A中的接合焊盘128可以与导电焊盘118电连接，并且多个接合焊盘128可以与相同的导电焊盘118电连接。以这种方式，可以形成具有接合焊盘128的器件结构100，接合焊盘128电连接到衬底102中的器件。
仍然参考图11，在一些实施例中，可以形成一些接合焊盘而不与导电焊盘118电连接。没有电连接的接合焊盘可以是例如“伪”接合焊盘，“伪”接合焊盘可以减少不均匀负载，并且改善在去除多余导电材料的平坦化步骤之后的表面平坦性。通过改善表面平坦性，可以获得表面之间更好的接合(参见图21)。示例性伪接合焊盘在图11中被指定为接合焊盘128D。转到图12，在一些实施例中，可以形成伪导电焊盘118，伪导电焊盘118的示例被指定为伪导电焊盘118D。形成伪导电焊盘118D还可以减小负载效应并进一步改善表面平坦性。伪导电焊盘118D可用于本文所述的任何实施例中，包括下面描述的那些。伪导电焊盘118D可以或可以不与任何金属线112电连接。伪接合焊盘128D可以形成为与伪导电焊盘118D接触，如图12所示。在一些实施例中，未形成伪接合焊盘128D和/或伪导电焊盘118D。
回到图11，使用第一停止层120作为平坦化工艺(参见图7)的停止可以允许更薄的表面介电层126。例如，可以形成厚度T3在约0.5μm和约8μm之间的表面介电层126，诸如约1.5μm或约6μm，但是可以使用其他厚度T3。在一些情况下，本文描述的实施例工艺可以将表面介电层126的厚度减小多达约50％。通过减小表面介电层126的厚度，可以减小接合焊盘128的高度，这可以减小接合焊盘128的电阻并改善器件的电性能。另外，通过形成如本文所述的较薄表面介电层126，导电焊盘118之上的所有介电层的组合厚度(例如，表面介电层126、第一停止层120和第二停止层124的组合厚度)可以减小。以这种方式减小介电层的组合厚度可以减小热传导的阻挡(例如，跨越介电层)，并且可以改善器件的热性能。较薄的表面介电层126还可以减小不期望的电容效应。具有较薄的表面介电层126还可以减小最终器件或封装件的总厚度。
图13至图17示出了根据一些实施例的器件结构150的形成中的中间阶段。图13至图17是第二实施例的剖视图，其中省略了第二停止层124。通过省略第二停止层124的形成，可以减少工艺步骤的数量。
转到图13，示出了与图6类似的结构，其中在第一停止层120上方形成介电层122。第一停止层120可以类似于先前在图5中描述的那样，并且在一些实施例中，可以形成为厚度T4在约500埃和约1500埃之间，诸如约500埃。第一停止层120可以形成为适合于停止或减慢下面在图14中描述的平坦化工艺的厚度。介电层122可以是与先前在图6中描述的材料类似的材料，并且可以以类似的方式形成。
在图14中，使用第一停止层120对介电层122执行平坦化工艺。如图14所示，第一停止层120的部分保留在导电焊盘118上。在一些实施例中，保留在导电焊盘118上的第一停止层120的厚度T5可以在约100埃到约500埃之间，诸如约300埃。在图14所示的实施例中，由于图14中所示的第一停止层120用作平坦化停止层和蚀刻停止层的事实，剩余的第一停止层120的厚度T5可以大于图7中所示的剩余的第一停止层120的厚度T2，如下面图16中所述。
转到图15，在第一停止层120上方形成表面介电层126，其可以类似于先前在图9中描述的表面介电层126。在图16中，在表面介电层126中形成开口127。可以使用如前所述的可接受的光刻和蚀刻技术形成开口127。可以使用第一停止层120作为蚀刻停止来形成开口127。然后，开口127可以延伸穿过第一停止层120，以暴露导电焊盘118。以这种方式，第一停止层120既用作平坦化停止层又用作蚀刻停止层。
转到图17，在开口127中形成接合焊盘128以与导电焊盘118电连接。接合焊盘128可以以与前述相似的方式形成。以这种方式，可以使用单个停止层(第一停止层120)形成器件结构150，因此可以使用更少的工艺步骤形成器件结构150。器件结构150还保留了上面参照图11描述的较薄表面介电层126的益处。
图18至图21示出了根据一些实施例的器件结构160的形成中的中间阶段。图18至图21是第三实施例的截面图，其中可以穿过介电层122和钝化层114形成接合焊盘通孔，以将一些接合焊盘133电连接到互连结构108的金属层线。除了提供额外的电连接，接合焊盘通孔可以提供改善的热传导并因此改善器件的热性能。
转到图18，在第二停止层124上方形成表面介电层126，它们可类似于先前在图9中描述的表面介电层126和第二停止层124。在一些实施例中，介电层122的部分被第一停止层120和第二停止层124包围，如图18所示。在图19中，第一开口131A形成在表面介电层126中。如前所述可以使用可接受的光刻和蚀刻技术形成第一开口131A。可以使用第二停止层124和/或第一停止层120作为蚀刻停止来形成第一开口131A。然后，第一开口131A可以延伸穿过第二停止层124和/或第一停止层120，以暴露导电焊盘118。
转到图20，形成延伸穿过介电层122和钝化层114的通孔开口131B。通孔开口131B形成在开口131A的底部，不位于导电焊盘118上方。通孔开口131B暴露金属层112以用于电连接。可以使用可接受的光刻和蚀刻技术形成通孔开口131B。光刻工艺可以包括在表面介电层126上方和第一开口131A中形成光刻胶(未示出)，用对应于通孔开口131B的开口图案化光刻胶，使通孔开口131B延伸穿过光刻胶并穿过钝化层114，以及然后去除光刻胶。在一些实施例中，通孔开口131B可以具有在约1μm和约3μm之间的较小宽度，或者可以具有在第一开口131A的宽度的约50％和约100％之间的宽度。
转到图21，在开口131A和131B中形成接合焊盘133A和通孔接合焊盘133B，以与导电焊盘118和金属线112电连接。接合焊盘133A与导电焊盘118电连接，并且通孔接合焊盘133B与金属线112电连接。接合焊盘133A和通孔接合焊盘133B可以以与前述接合焊盘128类似的方式形成。以这种方式，可以从接合焊盘到互连结构108进行额外的电连接。在一些实施例中，通孔接合焊盘133B中的一个或多个可以不电连接，并且可以是用于减小负载并且改善平坦性的“伪”部件。在一些实施例中，伪通孔接合焊盘133B可以连接到与互连结构108隔离的金属层线112。如图21所示，导电焊盘118通过第一停止层120和/或第二停止层124与表面介电层126分隔开。
转到图22，示出了根据一些实施例的包括接合在一起的两个器件结构的器件封装件1000。器件封装件1000包括第一器件结构100和第二器件结构200，其中任一个或两者可以类似于先前描述的器件结构100、150或160。第一器件结构100的接合焊盘128和表面介电层126接合到第二器件结构200的接合焊盘228和表面介电层226。在一些实施例中，第一器件结构100的接合焊盘128和第二器件结构200的接合焊盘228是相同的材料。在一些实施例中，第一器件结构100的表面介电层126和第二器件结构200的表面介电层226是相同的材料。
在图22中，使用例如直接接合或混合接合将第二器件结构200接合到第一器件结构100。在执行接合之前，可以对第二器件结构200或第一器件结构100执行表面处理。在一些实施例中，表面处理包括等离子体处理。等离子体处理可以在真空环境(例如，真空室，未示出)中执行。用于生成等离子体的工艺气体可以是含氢气体，含氢气体包括含有氢气(H2)和氩气(Ar)的第一气体、含有H2和氮气(N2)的第二气体或含有H2和氦气(He)的第三气体。等离子体处理也可以使用纯的或基本上纯的H2、Ar或N2作为工艺气体来执行，工艺气体处理接合焊盘128或228以及表面介电层126或226的表面。第二器件结构200或第一器件结构100可以用相同的表面处理工艺处理，或者用不同的表面处理工艺处理。在一些实施例中，可以在表面处理之后清洁第二器件结构200或第一器件结构100。清洁可以包括执行化学清洁和去离子水清洁/冲洗。
接下来，可以利用第二器件结构200和第一器件结构100执行预接合工艺。第二器件结构200和第一器件结构100对准，第二器件结构200的接合焊盘228与第一器件结构100的接合焊盘128对准。在对准之后，第二器件结构200和第一器件结构100彼此压靠在一起。在一些实施例中，压力可小于每管芯约5牛顿，但也可使用更大或更小的力。预接合工艺可以在室温下进行(例如，在约21℃至约25℃的温度下)，但是可以使用更高的温度。例如，预接合时间可短于约1分钟。
在预接合之后，第二器件结构200的表面介电层226和第一器件结构100的表面介电层126彼此接合。接合界面在图22和图23中标记为“B”。第二器件结构200和第一器件结构100组合在下文中称为器件封装件1000。可以在随后的退火步骤中加强器件封装件1000的接合。例如，器件封装件1000可以在约300℃至约400℃的温度下退火。退火可以进行例如约1小时至约2小时的时间。在退火期间，接合焊盘128和228中的金属可以彼此扩散，从而也形成金属至金属接合。因此，所得到的接合第二器件结构200和第一器件结构100可以是混合接合。在一些实施例中，在退火之后，在接合焊盘118与其对应的接合焊盘128之间不存在材料界面。
在一些实施例中，第一器件结构100的导电焊盘118和第二器件结构200的导电焊盘218的距离在约1μm和约16μm之间，诸如约3μm或约12μm。在一些实施例中，从导电焊盘118到界面B的距离不同于从导电焊盘218到界面B的距离。在一些实施例中，一个或多个接合焊盘128可以沿着界面B与它们对应的接合焊盘228偏移。在一些实施例中，接合焊盘128及其对应的接合焊盘228可以与导电焊盘118、导电焊盘218、互连结构108和/或互连结构208电隔离。在某些情况下，完全电隔离的接合焊盘128或接合焊盘228可被认为是“伪”导电部件。在一些实施例中，接合焊盘128中的一个或多个可以电连接到互连结构108(例如，类似于图21中所示的通孔接合焊盘133B)，并且接合焊盘228中的一个或多个可以电连接到互连结构208。在一些实施例中，连接到导电焊盘118的接合焊盘128可以接合到未连接到导电焊盘218的接合焊盘228。在一些实施例中，接合焊盘128或接合焊盘228可以具有锥形轮廓，在界面B附近具有最大的宽度。在一些实施例中，接合焊盘128可以具有与接合焊盘228不同的宽度或轮廓。
转到图23，示出了器件封装件1100。器件封装件1100类似于器件封装件1000，除了第二器件结构200之外，第三器件结构300还接合到第一器件结构100。第三器件结构300和第一器件结构100可以以与图22所述类似的方式接合。形成器件封装件的所有这些变化都在本发明的范围内。在一些实施例中，可以在接合之后对器件封装件1000或器件封装件1100执行分割工艺。
图24至图28示出了根据一些实施例的形成包括器件封装件1200的封装件1300的中间步骤。图24示出了已经接合成器件封装件1200中的第四器件结构400和第五器件结构500。第四器件结构400和第五器件结构500可以类似于前面描述的器件结构100、150、160、200或300，并且器件封装件1200可以类似于先前描述的器件封装件1000或1100。
图24还示出了载体衬底721，粘合剂层723和聚合物层725位于粘合剂层723上方。在一些实施例中，载体衬底721包括例如硅基材料，诸如玻璃或氧化硅或其他材料，诸如氧化铝、这些材料中的任何材料的组合等。载体衬底721可以是平坦的，以适应诸如接合对1200的半导体器件的附接。粘合剂层723放置在载体衬底721上，以有助于上面的结构(例如，聚合物层725)的粘附。在一些实施例中，粘合剂层723可以包括光热转换(LTHC)材料或紫外胶，当暴露于紫外光时失去其粘合性。然而，也可以使用其他类型的粘合剂，诸如压敏粘合剂、可辐射固化粘合剂、环氧树脂、这些的组合等。粘合剂层723可以以半液体或凝胶形式放置在载体基底721上，在压力下易于变形。
聚合物层725放置在粘合剂层723上方并用于为例如接合对1200提供保护。在一些实施例中，聚合物层725可以是聚苯并恶唑(PBO)，但是可以可选地利用任何合适的材料，诸如聚酰亚胺或聚酰亚胺衍生物。聚合物层725可以使用例如旋涂工艺放置至约2μm至约15μm之间的厚度，诸如约5μm，但是可以可选地使用任何合适的方法和厚度。接合对1200附着在聚合物层725上。在一些实施例中，接合对1200可以使用例如拾放工艺放置。然而，可以使用放置接合对1200的任何合适的方法。
在一些实施例中，在聚合物层725上方形成诸如介电通孔(TDV)727的通孔。在一些实施例中，首先在聚合物层725上方形成晶种层(未示出)。晶种层是导电材料的薄层，其有助于在随后的处理步骤中形成较厚的层。在一些实施例中，晶种层可以包括约500埃厚的钛层，接着是厚度约为3000埃的铜层。可以使用诸如溅射、蒸发或PECVD工艺的工艺来产生晶种层，这取决于期望的材料。一旦形成晶种层，就可以在晶种层上方形成光刻胶(未示出)并图案化光刻胶。然后在图案化的光刻胶内形成TDV 727。在一些实施例中，TDV 727包括一种或多种导电材料，诸如铜、钨、其他导电金属等，并且可以例如通过电镀、化学镀等形成。在一些实施例中，使用电镀工艺，其中将晶种层和光刻胶浸没或浸入电镀溶液中。一旦使用光刻胶和晶种层形成TDV 727，就可以使用合适的去除工艺去除光刻胶。在一些实施例中，可以使用等离子体灰化工艺来去除光刻胶，由此可以增加光刻胶的温度，直到光刻胶经历热分解并且可以被去除。然而，可以可选地使用任何其他合适的工艺，诸如湿条。去除光刻胶可以暴露下面的晶种层的部分。一旦形成TDV 727，然后例如使用湿或干蚀刻工艺去除晶种层的暴露部分。TDV 727可以形成为约180μm至约200μm之间的高度，临界尺寸为约190μm，间距为约300μm。
图25示出了利用密封剂729对接合对1200和TDV 727进行封装。密封剂729可以是模塑料，诸如树脂、聚酰亚胺、PPS、PEEK、PES、耐热晶体树脂、这些的组合等。图26示出了密封剂729的减薄以暴露TDV 727和接合对1200。可以例如使用CMP工艺或其他工艺来执行减薄。
图27示出了在密封剂729上方形成具有一个或多个层的再分布结构800。在一些实施例中，可以通过首先在密封剂729上方形成第一再分布钝化层801来形成再分布结构800。在一些实施例中，第一再分布钝化层801可以是聚苯并恶唑(PBO)，但是也可以可选地使用任何合适的材料，诸如聚酰亚胺或聚酰亚胺衍生物，诸如低温固化的聚酰亚胺。可以使用例如旋涂工艺将第一再分布钝化层801放置为约5μm和约17μm之间的厚度，诸如约7μm，但是可以可选地使用任何合适的方法和厚度。
一旦形成第一再分布钝化层801，就可以形成穿过第一再分布钝化层801的第一再分布通孔803，以便与接合对1200和TDV 727形成电连接。在一些实施例中，第一再分布通孔803可以通过使用镶嵌工艺、双镶嵌工艺或其他工艺形成。在已形成第一再分布通孔803之后，在第一再分布通孔803上方形成与第一再分布通孔803电连接的第一再分布层805。在一些实施例中，可通过最初通过合适的形成工艺(诸如CVD或溅射)形成钛铜合金的晶种层(未示出)来形成第一再分布层805。然后可以形成光刻胶(也未示出)以覆盖晶种层，然后可以图案化光刻胶以暴露第一再分布层805的期望位置的晶种层的那些部分。
一旦形成并图案化光刻胶，就可以通过诸如镀的沉积工艺在晶种层上形成诸如铜的导电材料。导电材料可以形成为具有介于约1μm和约10μm之间的厚度，诸如约4μm。然而，虽然所讨论的材料和方法适合于形成导电材料，但这些材料仅仅是示例性的。任何其他合适的材料(诸如AlCu或Au)以及任何其他合适的形成工艺(诸如CVD或PVD)可以可选地用于形成第一再分布层805。
在已形成第一再分布层805之后，可形成第二再分布钝化层807并将其图案化以帮助隔离第一再分布层805。在一些实施例中，第二再分布钝化层807可类似于第一再分布钝化层801，诸如为正性PBO，或者可以与第一再分布钝化层801不同，诸如为诸如低温固化的聚酰亚胺的负性材料。第二再分布钝化层807可以放置为约7μm的厚度。一旦就位，可以使用例如光刻掩模和蚀刻工艺图案化第二再分布钝化层807以形成开口，或者如果第二再分布钝化层807的材料是光敏的，则曝光和显影第二再分布钝化层807的材料。然而，可以使用任何合适的材料和图案化方法。
在已经图案化第二再分布钝化层807之后，可以形成第二再分布层809以延伸穿过在第二再分布钝化层807内形成的开口并且与第一再分布层805形成电连接。在一些实施例中，可以使用与第一再分布层805类似的材料和工艺来形成第二再分布层809。例如，可以通过图案化的光刻胶施加和覆盖晶种层，可以将诸如铜的导电材料施加到晶种层上，可以去除图案化的光刻胶，并且可以使用导电材料作为掩模来蚀刻晶种层。在一些实施例中，第二再分布层809形成为约4μm的厚度。然而，可以使用任何合适的材料或制造工艺。
在形成第二再分布层809之后，在第二再分布层809上方施加第三再分布钝化层811，以帮助隔离和保护第二再分布层809。在一些实施例中，第三再分布钝化层811可以由与第二再分布钝化层807类似的材料和类似的方式形成至约7μm的厚度。例如，第三再分布钝化层811可以由PBO或低温固化的聚酰亚胺形成，其已经如上关于第二再分布钝化层807所述来施加和图案化。然而，可以利用任何合适的材料或制造工艺。
在已经图案化第三再分布钝化层811之后，可以形成第三再分布层813以延伸穿过在第三再分布钝化层811内形成的开口并且与第二再分布层809形成电连接。在一些实施例中，可以使用与第一再分布层805类似的材料和工艺来形成第三再分布层813。例如，可以通过图案化的光刻胶施加和覆盖晶种层，可以将诸如铜的导电材料施加到晶种层上，可以去除图案化的光刻胶，并且可以使用导电材料作为掩模来蚀刻晶种层。在一些实施例中，第三再分布层813形成为5μm的厚度。然而，可以使用任何合适的材料或制造工艺。
在形成第三再分布层813之后，可以在第三再分布层813上方形成第四再分布钝化层815，以帮助隔离和保护第三再分布层813。在一些实施例中，第四再分布钝化层815可以由与第二再分布钝化层807类似的材料和类似的方式形成。例如，第四再分布钝化层815可以由PBO或低温固化的聚酰亚胺形成，其已经如上关于第二再分布钝化层807所述来施加和图案化。在一些实施例中，第四再分布钝化层815形成为约8μm的厚度。然而，可以利用任何合适的材料或制造工艺。
在其他实施例中，再分布结构800的再分布通孔和再分布层可以使用镶嵌工艺形成，诸如双镶嵌工艺。例如，可以在密封剂729上方形成第一再分布钝化层。然后使用一个或多个光刻步骤对第一再分布钝化层进行图案化，以在第一再分布钝化层内形成用于通孔的开口和用于导线的开口。可以在用于通孔的开口和用于导线的开口中形成导电材料，以形成第一再分布通孔和第一再分布层。可以在第一再分布钝化层上方形成附加的再分布钝化层，并且可以在附加的再分布钝化层中形成再分布通孔和导线的附加组，如针对第一再分布钝化层所描述的，形成再分布结构800。这个或其他技术可以用于形成再分布结构800。
图27另外示出了用于与第三再分布层813电接触的凸块下金属化819和第三外部连接件817的形成。在一些实施例中，凸块下金属化819可各自包括三层导电材料，诸如钛层、铜层和镍层。然而，本领域普通技术人员将认识到，存在许多合适的材料和层的布置，诸如适合于形成凸块下金属化819的铬/铬铜合金/铜/金的布置、钛/钛钨/铜的布置或者铜/镍/金的布置。可用于凸块下金属化819的任何合适的材料或材料层完全旨在包括在实施例的范围内。
在一些实施例中，通过在第三再分布层813上方并且沿着穿过第四再分布钝化层815的开口内部形成每个层来产生凸块下金属化819。可以使用镀工艺(诸如电镀)来执行每层的形成，但是可以使用其他形成工艺，诸如溅射、蒸发或PECVD工艺，这取决于所需的材料。凸块下金属化819可以形成为具有介于约0.7μm和约10μm之间的厚度，诸如约5μm。
在一些实施例中，第三外部连接件817可以放置在凸块下金属化819上，并且可以是球栅阵列(BGA)，BGA包括诸如焊料的共晶材料，但是可以可选地使用任何合适的材料。在第三外部连接件817是焊球的一些实施例中，第三外部连接件817可以使用落球方法形成，诸如直接落球工艺。在另一实施例中，可以通过首先通过任何合适的方法(诸如蒸发、电镀、印刷、焊料转移)形成锡层，然后执行回流，以便将材料成形为所需的凸块形状来形成焊球。一旦形成了第三外部连接件817，就可以执行测试以确保该结构适合于进一步处理。
图28示出了封装件700通过聚合物层725接合到TDV 727。在接合封装件700之前，从聚合物层725去除载体衬底721和粘合剂层723。还图案化聚合物层725以暴露TDV 727。在一些实施例中，可以使用例如激光钻孔方法图案化聚合物层725。在这种方法中，首先在聚合物层725上方沉积保护层，诸如光热转换(LTHC)层或hogomax层(未单独示出)。一旦受到保护，激光就被引导到聚合物层725的期望被去除的那些部分以暴露下面的TDV 727。在激光钻孔工艺期间，钻孔能量可以在0.1mJ至约30mJ的范围内，并且相对于聚合物层725的法线的钻孔角度为约0度(垂直于聚合物层725)至约85度。在一些实施例中，可以执行图案化以在TDV 727上方形成开口，该开口具有介于约100μm和约300μm之间的宽度，诸如约200μm。
在另一实施例中，可以通过首先将光刻胶(未单独示出)施加到聚合物层725，然后将光刻胶暴露于图案化的能量源(例如，图案化的光源)，以便诱导化学反应，从而引起暴露于图案化的光源的光刻胶的那些部分的物理变化来图案化聚合物层725。然后将显影剂施加到曝光的光刻胶以利用物理变化并根据所需图案选择性地去除光刻胶的曝光部分或光刻胶的未曝光部分，并且用例如干蚀刻工艺去除下面的聚合物层725的暴露部分。然而，可以使用用于图案化聚合物层725的任何其他合适的方法。
在一些实施例中，封装件700包括衬底702和耦合到衬底702的一个或多个堆叠管芯710(710A和710B)。尽管示出了一组堆叠管芯710(710A和710B)，但在其他实施例中，多个堆叠管芯710(每个具有一个或多个堆叠管芯)可以并排设置为耦合到衬底702的同一表面。衬底702可以由半导体材料制成，诸如硅、锗、金刚石等。在一些实施例中，还可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷化镓砷、磷化镓铟、它们的组合等的化合物材料。另外，衬底702可以是绝缘体上硅(SOI)衬底。通常，SOI衬底包括半导体材料层，诸如外延硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合。在一个可选实施例中，衬底702基于绝缘芯，诸如玻璃纤维增强树脂芯。一种示例芯材料是玻璃纤维树脂，诸如FR4。芯材料的替代物包括双马来酰亚胺-三嗪(BT)树脂，或者可选地，其他印刷电路板(PCB)材料或膜。诸如味之素积层膜(ABF)或其他层压板的构建膜可用于衬底702。
衬底702可以包括有源和无源器件(未示出)。诸如晶体管、电容器、电阻器、这些的组合等的各种器件可用于生成封装件700的设计的结构和功能要求。可使用任何合适的方法形成器件。
衬底702还可以包括金属化层或导电通孔(未示出)。金属化层可以形成在有源和无源器件上方，并设计成连接各种器件以形成功能电路。金属化层可以由交替的介电层(例如，低k介电材料)和导电材料层(例如，铜)形成，其中通孔互连导电材料层并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些实施例中，衬底702基本上没有有源和无源器件。
衬底702可以在衬底702的第一侧上具有接合焊盘704以耦合到堆叠管芯710，并且在衬底702的第二侧上具有接合焊盘706以耦合到外部连接件901，第二侧与衬底702的第一侧相对。在一些实施例中，通过在衬底702的第一和第二侧上的介电层(未示出)中形成凹槽(未示出)来形成接合焊盘704和706。可以形成凹槽以允许接合焊盘704和706嵌入介电层中。在其他实施例中，省略凹槽，因为接合焊盘704和706可以形成在介电层上。在一些实施例中，接合焊盘704和706包括由铜、钛、镍、金、钯等或它们的组合制成的薄晶种层(未示出)。接合焊盘704和706的导电材料可以沉积在薄晶种层上方。导电材料可以通过电化学镀工艺、化学镀工艺、CVD、原子层沉积(ALD)、PVD等或它们的组合形成。在实施例中，接合焊盘704和706的导电材料是铜、钨、铝、银、金等或它们的组合。
在实施例中，接合焊盘704和接合焊盘706是UBM，UBM包括三层导电材料，诸如钛层、铜层和镍层。材料和层的其他布置(诸如铬/铬铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置)可用于形成接合焊盘704和706。可以用于接合焊盘704和706的任何合适的材料或材料层完全旨在包括在本申请的范围内。在一些实施例中，导电通孔延伸穿过衬底702并将至少一个接合焊盘704耦合到接合焊盘706中的至少一个。
在所示实施例中，堆叠管芯710通过引线接合712耦合到衬底702，但是可以使用其他连接，诸如导电凸块。在实施例中，堆叠管芯710是堆叠的存储器管芯。例如，堆叠管芯710可以是存储器管芯，诸如低功率(LP)双倍数据速率(DDR)存储器模块，诸如LPDDR1、LPDDR2、LPDDR3、LPDDR4等存储器模块。
堆叠管芯710和引线接合712可以由模制材料714密封。模制材料714可以模制在堆叠管芯710和引线接合712上，例如，使用压缩模制。在一些实施例中，模制材料714是模塑料、聚合物、环氧树脂、氧化硅填充材料等或它们的组合。可以执行固化工艺以固化模制材料714。固化工艺可以是热固化、UV固化等或它们的组合。
在一些实施例中，堆叠管芯710和引线接合712被掩埋在模制材料714中，并且在模制材料714固化之后，执行诸如研磨的平坦化步骤以去除模制材料714的多余部分，并且为封装件700提供基本平坦的表面。
在一些实施例中，外部连接件901可以形成为在封装件700和例如TDV727之间提供外部连接。外部连接件901可以是接触凸块，诸如微凸块或受控塌陷芯片连接(C4)凸块并且可以包括诸如锡的材料或其他合适的材料，诸如银或铜。在外部连接件901是锡焊料凸块的一些实施例中，可以通过最初通过任何合适的方法(诸如蒸发、电镀、印刷、焊料转移、球放置等)形成锡层至例如约100μm的厚度而形成外部连接件901。一旦在结构上形成了锡层，就执行回流以将材料成形为所需的凸起形状。
一旦形成外部连接件901，外部连接件901与TDV 727对准并放置在TDV 727上方，并且执行接合。例如，在外部连接件901是焊料凸块的一些实施例中，接合工艺可以包括回流工艺，由此外部连接件901的温度升高到外部连接件901将液化和流动的点，从而一旦外部连接件901重新固化，就将封装件700接合到TDV 727。可以形成密封剂903以密封和保护封装件700。密封剂903可以在聚合物层725和封装件700之间延伸，并且在一些实施例中可以是底部填充物。以这种方式，可以形成封装件1300。
实施例可以实现优点。通过在导电焊盘上方使用平坦化停止层，可以在导电焊盘的顶面附近停止平坦化工艺。这可以形成更薄的表面介电层(例如，“接合氧化物”)。通过减小表面介电层的厚度，可以减小包含器件的封装件的总厚度。另外，较薄的表面介电层提供改善的热传导，因此可以改善器件的热性能。
在实施例中，器件包括：互连结构，位于衬底上方；多个第一导电焊盘，位于互连结构上方并且连接到互连结构；平坦化停止层，在多个第一导电焊盘的侧壁和顶面上方延伸；表面介电层，在平坦化停止层上方延伸；以及多个第一接合焊盘，位于表面介电层内，并且连接到多个第一导电焊盘。在实施例中，器件包括在平坦化停止层上方延伸的蚀刻停止层，表面介电层位于蚀刻停止层上。在实施例中，该器件包括位于平坦化停止层和蚀刻停止层之间的第一介电层。在实施例中，多个第一接合焊盘延伸穿过平坦化停止层和蚀刻停止层。在实施例中，平坦化停止层包括碳化硅。在实施例中，表面介电层的厚度在6μm和8μm之间。在实施例中，该器件包括位于互连结构和多个第一导电焊盘之间的第二介电层，其中平坦化停止层在第二介电层的顶面上方延伸。在实施例中，该器件包括位于互连结构上方的多个第二导电焊盘，并且包括位于表面介电层内并且连接到多个第二导电焊盘的多个第二接合焊盘，其中第二导电焊盘与互连结构隔离。在实施例中，多个第一导电焊盘包括铝。
在实施例中，一种方法包括：在互连结构中形成第一金属线，在互连结构上方形成绝缘层，在绝缘层上方形成导电元件，导电元件穿过绝缘层延伸到第一金属线，形成第一停止层，第一停止层在绝缘体层上方延伸并且在导电元件的侧壁和顶面上方延伸，在第一停止层上方形成第二绝缘层，使用第一停止层作为平坦化停止层，对第二绝缘层执行平坦化工艺，在第一停止层上方形成第二停止层，其中第二停止层物理接触第二绝缘层的顶面并且物理接触第一停止层的顶面，在第二停止层上方形成接合氧化物层，以及在接合氧化物层中形成接合焊盘。在实施例中，在执行平坦化工艺之后，绝缘层上方的第一停止层的第一厚度大于导电元件上方的第一停止层的第二厚度。在实施例中，在接合氧化物层中形成接合焊盘包括使用第二停止层作为蚀刻停止来在接合氧化物层中蚀刻开口。并且在第一停止层中蚀刻开口以暴露导电元件。在实施例中，在接合氧化物层中形成接合焊盘包括使用第二停止层作为蚀刻停止，在接合氧化物层中蚀刻开口以暴露第二绝缘层。在实施例中，该方法包括使接合氧化物层中的开口延伸穿过第二绝缘层，以暴露互连结构中的第二金属线。
在实施例中，器件包括：互连结构，位于半导体衬底上方；多个导电焊盘，位于互连结构上方并且连接到互连结构；第一蚀刻停止层，位于多个导电焊盘上方；介电层，位于第一蚀刻停止层上方并且围绕导电焊盘，介电层的顶面与第一蚀刻停止层的顶面共面；接合层，位于第一蚀刻停止层和介电层上方；以及多个接合焊盘，位于接合层中，多个接合焊盘连接到多个导电焊盘。在实施例中，该器件包括位于第一蚀刻停止层和介电层上方的第二蚀刻停止层。在实施例中，第二蚀刻停止层的材料与第一蚀刻停止层的材料相同。在实施例中，该器件包括顶部封装件，该顶部封装件接合到多个接合焊盘和接合层。在实施例中，第一蚀刻停止层在多个导电焊盘的导电焊盘的侧壁上延伸。在实施例中，至少一个接合焊盘从多个导电焊盘之上延伸到多个导电焊盘下方。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基底来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并且不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体器件，包括：
互连结构，位于衬底上方；
多个第一导电焊盘，位于所述互连结构上方并且连接到所述互连结构；
平坦化停止层，在所述多个第一导电焊盘的第一导电焊盘的侧壁和顶面上方延伸；
表面介电层，在所述平坦化停止层上方延伸；以及
多个第一接合焊盘，位于所述表面介电层内，并且连接到所述多个第一导电焊盘。
2.根据权利要求1所述的半导体器件，还包括在所述平坦化停止层上方延伸的蚀刻停止层，所述表面介电层位于所述蚀刻停止层上。
3.根据权利要求2所述的半导体器件，还包括位于所述平坦化停止层和所述蚀刻停止层之间的第一介电层。
4.根据权利要求2所述的半导体器件，其中，所述多个第一接合焊盘延伸穿过所述平坦化停止层和所述蚀刻停止层。
5.根据权利要求1所述的半导体器件，其中，所述平坦化停止层包括碳化硅。
6.根据权利要求1所述的半导体器件，其中，所述表面介电层的厚度在6μm和8μm之间。
7.根据权利要求1所述的半导体器件，还包括位于所述互连结构和所述多个第一导电焊盘之间的第二介电层，其中，所述平坦化停止层在所述第二介电层的顶面上方延伸。
8.根据权利要求1所述的半导体器件，还包括位于所述互连结构上方的多个第二导电焊盘，并且还包括位于所述表面介电层内并且连接到所述多个第二导电焊盘的多个第二接合焊盘，其中，所述第二导电焊盘与所述互连结构隔离。
9.一种形成半导体器件的方法，包括：
在互连结构中形成第一金属线；
在所述互连结构上方形成绝缘层；
在所述绝缘层上方形成导电元件，所述导电元件穿过所述绝缘层延伸到所述第一金属线；
形成第一停止层，所述第一停止层在所述绝缘层上方延伸并且在所述导电元件的侧壁和顶面上方延伸；
在所述第一停止层上方形成第二绝缘层；
使用所述第一停止层作为平坦化停止层，对所述第二绝缘层执行平坦化工艺；
在所述第一停止层上方形成第二停止层，其中，所述第二停止层物理接触所述第二绝缘层的顶面并且物理接触所述第一停止层的顶面；
在所述第二停止层上方形成接合氧化物层；以及
在所述接合氧化物层中形成接合焊盘。
10.一种半导体器件，包括：
互连结构，位于半导体衬底上方；
多个导电焊盘，位于所述互连结构上方并且连接到所述互连结构；
第一蚀刻停止层，位于所述多个导电焊盘上方；
介电层，位于所述第一蚀刻停止层上方并且围绕所述多个导电焊盘的导电焊盘，所述介电层的顶面与所述第一蚀刻停止层的顶面共面；
接合层，位于所述第一蚀刻停止层和所述介电层上方；以及
多个接合焊盘，位于所述接合层中，所述多个接合焊盘连接到所述多个导电焊盘。
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