WO2021031419A1 - 第一晶圆及其形成方法、晶圆堆叠结构 - Google Patents

第一晶圆及其形成方法、晶圆堆叠结构 Download PDF

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WO2021031419A1
WO2021031419A1 PCT/CN2019/119524 CN2019119524W WO2021031419A1 WO 2021031419 A1 WO2021031419 A1 WO 2021031419A1 CN 2019119524 W CN2019119524 W CN 2019119524W WO 2021031419 A1 WO2021031419 A1 WO 2021031419A1
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layer
wafer
interconnection
hole
electrically connected
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PCT/CN2019/119524
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English (en)
French (fr)
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胡杏
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武汉新芯集成电路制造有限公司
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Priority to US16/626,785 priority Critical patent/US11211348B2/en
Publication of WO2021031419A1 publication Critical patent/WO2021031419A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas

Definitions

  • the invention belongs to the technical field of integrated circuit manufacturing, and specifically relates to a first wafer and a forming method thereof, and a wafer stack structure.
  • wafer bonding is a common technology to achieve wafer integration.
  • the interconnection between wafers must be realized when wafer bonding is contracted.
  • wafer bonding is The flatness of the wafer surface to be bonded has high requirements. Therefore, before bonding, a chemical mechanical polishing (CMP) process is required to planarize the wafer surface, and then an etching process is used to form interconnect holes, which are exposed.
  • CMP chemical mechanical polishing
  • the metal layer of the wafer to be interconnected is usually formed by electroplating copper in the interconnect hole to form an interconnect layer electrically connected to the metal layer.
  • the entire process capability will be simultaneously restricted by the CMP process capability, the etching process process capability, and the copper electroplating process capability.
  • the limitation is mainly reflected in that if the surface flatness before wafer bonding is poor, then a thicker dielectric layer must be formed on the wafer surface to compensate for the poor flatness, and the CMP polishing required for a thicker dielectric layer increases
  • a thicker dielectric layer needs to be retained after polishing, and the interconnection holes are etched The remaining dielectric layer exposes the metal layer.
  • the thicker the remaining dielectric layer the deeper the etching depth. Under the CD (critical dimension) of the same interconnection hole, the greater the aspect ratio, the more difficult it is to fill with the copper electroplating process. Large, the entire process window is small.
  • the object of the present invention is to provide a first wafer, a method for forming the same, and a wafer stack structure, which reduces the process difficulty of filling an interconnection layer in a hole with a high aspect ratio and increases the process window.
  • a first wafer including:
  • the first switch hole of the metal layer, the first interconnection layer that fills the first switch hole and is electrically connected to the first metal layer, and the first interconnection layer located on the surface of the first dielectric layer and the first interconnection layer An insulating layer, a first contact hole penetrating the first insulating layer and exposing the first interconnection layer, and a second interconnection filling the first contact hole and electrically connected to the first interconnection layer Floor.
  • the material of the first interconnection layer includes tungsten; the material of the second interconnection layer includes copper.
  • first contact hole is arranged corresponding to the first switch hole, and each of the first switch hole and the first contact hole includes a plurality of holes distributed at intervals.
  • the present invention also provides a method for forming the first wafer, including:
  • a first dielectric layer is formed on the first substrate, and a first metal layer is embedded in the first dielectric layer;
  • first insulating layer Forming a first insulating layer, the first insulating layer covering the surface of the first dielectric layer and the first interconnection layer;
  • a second interconnection layer is formed, and the second interconnection layer fills the first contact hole and is electrically connected to the first interconnection layer.
  • the present invention also provides a wafer stack structure, including:
  • the first wafer includes a first substrate, a first dielectric layer on the first substrate, and a first metal embedded in the first dielectric layer Layer, a first switch hole that penetrates part of the first dielectric layer and exposes the first metal layer, a first interconnect layer that fills the first switch hole and is electrically connected to the first metal layer, is located
  • the first insulating layer on the surface of the first dielectric layer and the first interconnection layer, the first contact hole penetrating the first insulating layer and exposing the first interconnection layer, and filling the first contact
  • the second wafer includes a second substrate, a second dielectric layer on the second substrate, a second metal layer embedded in the second dielectric layer, the first wafer and the In the second wafer bonding, the first metal layer is electrically connected to the second metal layer.
  • the second dielectric layer exposes the surface of the second metal layer, the second metal layer of the second wafer is in contact with the second interconnection layer of the first wafer, and It is electrically connected and forms a bonding interface.
  • the second wafer further includes a second switch hole and a third interconnection layer; the second switch hole penetrates part of the second dielectric layer and exposes the second metal layer; the third The interconnection layer fills the second switch hole and is electrically connected to the second metal layer.
  • the third interconnection layer of the second wafer is in contact with and electrically connected to the second interconnection layer of the first wafer, and forms a bonding interface.
  • the second wafer further includes a second insulating layer, a second contact hole, and a fourth interconnection layer, and the second insulating layer is located on the surface of the second dielectric layer and the third interconnection layer;
  • the second contact hole penetrates the second insulating layer and exposes the third interconnection layer;
  • the fourth interconnection layer fills the second contact hole;
  • the fourth interconnection layer and the first Three interconnection layers are electrically connected;
  • the fourth interconnection layer of the second wafer is in contact with and electrically connected to the second interconnection layer of the first wafer, and a bonding interface is formed.
  • the wafer stack structure further includes: a third wafer, the third wafer including a third substrate, a third dielectric layer on the third substrate, and embedded in the third wafer.
  • the present invention has the following beneficial effects:
  • the first switch hole is filled with the first interconnection layer electrically connected to the first metal layer; the first The contact hole is filled with a second interconnection layer; the second interconnection layer is electrically connected to the first interconnection layer; through the second interconnection layer in the first contact hole, the first switch hole
  • the interconnection layer draws out the first metal layer in the first wafer, that is, fills the respective interconnection layers in sections through the first contact hole and the first switch hole, which reduces the aspect ratio of the first metal layer when the first metal layer is drawn.
  • the process difficulty of filling the interconnection layer with copper electroplating in the hole increases the process window. It solves the problem that the deep hole is difficult to fill when the interconnection hole between the stacked wafers to be bonded and interconnected is small in size and large in depth.
  • FIG. 1 is a schematic cross-sectional view of a first wafer according to an embodiment of the present invention
  • FIG. 2 is a schematic flowchart of a method for forming a first wafer according to an embodiment of the present invention
  • 3 to 8 are schematic diagrams of various steps of a method for forming a first wafer according to an embodiment of the present invention.
  • FIG. 9 is a schematic cross-sectional view of a first wafer stack structure according to an embodiment of the present invention.
  • FIG. 10 is a schematic cross-sectional view of a second type of wafer stack structure according to an embodiment of the present invention.
  • FIG. 11 is a schematic cross-sectional view of a third wafer stack structure according to an embodiment of the present invention.
  • FIG. 12 is a schematic cross-sectional view of a fourth wafer stack structure according to an embodiment of the present invention.
  • A-bonding interface B-bonding interface
  • An embodiment of the present invention provides a first wafer, as shown in FIG. 1,
  • the first wafer 10 includes a first substrate 101, a first dielectric layer 102 on the first substrate 101, a first metal layer 103 embedded in the first dielectric layer 102, and a first switch hole (The hole filled in the first interconnect layer 105), the first interconnect layer 105, the first insulating layer 106, the first contact hole (the hole filled in the second interconnect layer 108), and the second interconnect layer 108, the The first switch hole penetrates part of the first dielectric layer 102 of the first wafer 10 where it is located and exposes a part of the first metal layer 103; the first switch hole is filled with electrical connection with the metal layer 103
  • the first interconnection layer 105; the first insulating layer 106 is located on the surface of the dielectric layer 102 and the first interconnection layer 105; the first contact hole penetrates the insulating layer 106 and exposes the The first interconnection layer 105; the first contact hole is filled with a second interconnection layer 108; the second interconnection layer 108 is electrically connected to the first
  • FIG. 2 is a schematic flow chart of a method for forming a first wafer according to an embodiment of the present invention. As shown in FIG. 2, an embodiment of the present invention provides a method for forming a first wafer, including:
  • a first dielectric layer is formed on the first substrate, and a first metal layer is embedded in the first dielectric layer;
  • first insulating layer Forming a first insulating layer, the first insulating layer covering the surface of the first dielectric layer and the first interconnection layer;
  • a second interconnection layer is formed, and the second interconnection layer fills the first contact hole and is electrically connected to the first interconnection layer.
  • a first substrate 101 is provided, and a first dielectric layer first portion 102a is formed on the first substrate 101, and a plurality of first metal layers 103 are formed on the first dielectric layer 102a.
  • the second portion 102b of the first dielectric layer covering the first metal layer 103, the first portion 102a of the first dielectric layer and the second portion 102b of the first dielectric layer are formed on the first portion 102a of the first dielectric layer.
  • the first dielectric layer 102 is formed, and the surface of the first dielectric layer 102 is planarized by CMP.
  • a first switch hole 104 is formed, and the first switch hole 104 penetrates part of the first dielectric layer 102 and exposes a part of the first metal layer 103.
  • the first switch hole 104 is filled with a first interconnect layer 105 electrically connected to the first metal layer 103;
  • the first interconnect layer 105 includes metal tungsten, which has high conductivity and high conductivity.
  • the filling ability It can be formed by evaporation, sputtering or chemical vapor deposition (CVD) process, preferably CVD method for tungsten deposition.
  • CVD tungsten has low resistivity, high resistance to electromigration, and excellent flatness when filling small through holes.
  • CVD tungsten can also be selectively deposited on metal. Tungsten in the CVD method can be prepared from tungsten chloride, tungsten fluoride and tungsten hydroxy.
  • the main reaction gases are tungsten hexafluoride and hydrogen or monosilane.
  • the hole-filling ability of tungsten can be improved by changing the following parameters: For example, 1. Increase the ratio of WF 6 /SiH 4 during nucleation, and the partial pressure occupied by WF 6 and SiH 4 and the total pressure of the reaction chamber; 2. Increase the rapid deposition of WF 6 /H 2 ratio and reaction chamber pressure; 3. Increase the preheating pressure; 4. Decrease the reaction temperature.
  • the first interconnection layer 105 will also cover the surface of the first dielectric layer 102.
  • the first interconnection layer on the surface of the first dielectric layer 102 can be removed by CMP or an etch-back process and the surface is planarized, leaving The first interconnect layer 105 in the first switch hole 104 is described below.
  • a first insulating layer 106 is formed, and the first insulating layer 106 covers the surface of the first dielectric layer 102 and the first interconnection layer 105; the first insulating layer 106 may As an etch stop layer for subsequently forming the first contact hole (hole filled with the second interconnect layer 108). Further, a passivation layer 107 is also formed on the surface of the first insulating layer 106; the passivation layer 107 is, for example, an oxide layer, which protects the surface of the first wafer 10.
  • a first contact hole (a hole filled in the second interconnection layer 108) is formed.
  • the first contact hole penetrates the passivation layer 107 and the first insulating layer 106 and exposes the first contact hole.
  • the first contact hole (hole filled by the second interconnection layer 108) is arranged corresponding to the first switch hole (hole filled by the first interconnection layer 105).
  • the second interconnection layer 108 includes copper and can be formed by electroplating, and then the surfaces of the passivation layer 107 and the second interconnection layer 108 are planarized by a CMP process to form a flat bonding interface.
  • the first wafer 10 further includes a first etch stop layer, and the first etch stop layer is located between the first metal layer 103 and the second portion 102b of the first dielectric layer.
  • the embodiment of the present invention also provides a wafer stack structure, including: a first wafer and a second wafer.
  • the first wafer includes a first substrate, a first dielectric layer on the first substrate, a first metal layer embedded in the first dielectric layer, and a portion of the first dielectric layer And exposes the first switch hole of the first metal layer, the first interconnect layer that fills the first switch hole and is electrically connected to the first metal layer, and is located between the dielectric layer and the first interconnection layer.
  • the first insulating layer on the surface of the connecting layer, the first contact hole that penetrates the first insulating layer and exposes the first interconnection layer, fills the first contact hole and is electrically connected to the first interconnection layer The second interconnection layer.
  • the second wafer includes a second substrate, a second dielectric layer on the second substrate, a second metal layer embedded in the second dielectric layer, the first wafer and the In the second wafer bonding, the first metal layer is electrically connected to the second metal layer.
  • the first switch hole is filled with the first interconnection layer electrically connected to the metal layer; the first contact hole is filled with a second interconnection layer; the second interconnection The connecting layer is electrically connected to the first interconnection layer; the second interconnection layer of the first wafer is electrically connected to the metal layer of the second wafer.
  • the interconnection of the two wafers that are bonded is realized through the second interconnection layer in the first contact hole and the first interconnection layer in the first switch hole, that is, the first contact hole and the first switch hole are distributed and filled with each
  • the interconnection layer reduces the process difficulty of copper electroplating for holes with a large aspect ratio and increases the process window. It solves the problem that the deep hole is difficult to fill when the interconnection hole between the stacked wafers to be bonded and interconnected is small in size and large in depth.
  • the wafer stack structure includes: a first wafer 10 and a second wafer 20.
  • the first wafer 10 includes a first substrate 101, a first dielectric layer 102 on the first substrate 101, a first metal layer 103 embedded in the first dielectric layer 102, and a first switch hole (The hole filled in the first interconnect layer 105), the first interconnect layer 105, the first insulating layer 106, the first contact hole (the hole filled in the second interconnect layer 108), and the second interconnect layer 108, the The first switch hole penetrates part of the first dielectric layer 102 of the first wafer 10 where it is located and exposes a part of the first metal layer 103; the first switch hole is filled with electrical connection with the metal layer 103
  • the first interconnection layer 105; the first insulating layer 106 is located on the surface of the dielectric layer 102 and the first interconnection layer 105; the first contact hole penetrates the insulating layer 106 and exposes the The first interconnection layer 105
  • the second wafer 20 includes a second substrate 201, a second dielectric layer 202 located on the second substrate 201, and a second metal layer 203 embedded in the second dielectric layer 202.
  • the first wafer 10 is bonded to the second wafer 20, and the first metal layer 103 is electrically connected to the second metal layer 203.
  • the second dielectric layer 202 exposes the surface of the second metal layer 203, the second metal layer 203 of the second wafer 20 and the second metal layer 203 of the first wafer 10
  • the interconnection layer 108 contacts and is electrically connected, and forms a bonding interface A.
  • This embodiment is suitable for the interconnection holes (the holes from the bonding interface A to the upper surface of the first metal layer 103) of the first wafer 10 to be bonded with a small size and a relatively deep depth (that is, a relatively large depth and width).
  • the second metal layer 203 of the second wafer 20 is exposed (for example, in a semi-finished state), and the depth of the interconnection hole of the first wafer 10 is the distance from the bonding interface A to the upper surface of the first metal layer 103.
  • the second wafer 20 further includes a second switch hole (a hole filled with the third interconnection layer 205) and a third interconnection layer 205;
  • the second dielectric layer 202 exposes the second metal layer 203;
  • the third interconnect layer 205 fills the second switch hole and is electrically connected to the second metal layer 203.
  • the third interconnection layer 205 of the second wafer 20 and the second interconnection layer 108 of the first wafer 10 are in contact and electrically connected to form a bonding interface A.
  • This embodiment is suitable for the interconnection hole (the hole from the bonding interface A to the first metal layer 103) of the first wafer 10 to be bonded with a smaller size and a larger depth (that is, a larger depth and width).
  • the interconnection hole (from the bonding interface A to the hole of the second metal layer 203) of the wafer 20 has a smaller depth.
  • the depth of the interconnect hole of the first wafer 10 is the distance from the bonding interface A to the first metal layer 103
  • the depth of the interconnect hole of the second wafer 20 is from the bonding interface A to the second metal layer 203. the distance.
  • the second wafer 20 further includes a second insulating layer 206, a second contact hole (a hole filled by the fourth interconnection layer 208), and a fourth interconnection layer 208.
  • the second insulating layer 206 is located on the surface of the second dielectric layer 202 and the third interconnection layer 205; the second contact hole (hole filled by the fourth interconnection layer 208) penetrates the second insulating layer 206 and is exposed The third interconnection layer 205; the fourth interconnection layer 208 fills the second contact hole; the fourth interconnection layer 208 is electrically connected to the third interconnection layer 205; the second The fourth interconnection layer 208 of the wafer 20 and the second interconnection layer 108 of the first wafer 10 are in contact and electrically connected, and a bonding interface A is formed.
  • the second wafer 20 and the first wafer 10 have the same or similar structure.
  • This embodiment is suitable for applications where the interconnect holes (holes from the bonding interface to the metal layer) of the two wafers to be bonded and electrically connected are small in size and relatively deep (that is, relatively large in depth and width).
  • the depth of the interconnection hole of the first wafer is the distance from the bonding interface A to the first metal layer 103
  • the depth of the interconnection hole of the second wafer 20 is the distance from the bonding interface A to the second metal layer 203 distance.
  • the first wafer 10 and/or the second wafer 20 may be thinned .
  • the first contact hole (hole filled by the second interconnection layer 108) and the first switch hole (hole filled by the first interconnection layer 105) are arranged correspondingly, and each first The switch hole and each first contact hole each include a plurality of holes distributed at intervals, that is, each first switch hole and each first contact hole is an array hole group composed of a plurality of holes.
  • each second switch hole (hole filled by the third interconnect layer 205) and each second contact hole (hole filled by the fourth interconnect layer 208) is an array hole group composed of a plurality of holes.
  • the second interconnection layer 108 is in contact with the fourth interconnection layer 208, which increases the reliability of the interconnection and reduces the heat generated during the operation of the interconnection layer at intervals.
  • the multiple spaced holes can be smaller in size and higher in density, which can also meet the interconnection requirements of certain specific applications.
  • the signals that need to be interconnected are signals with high density and low current.
  • the holes and the interconnection layers in the holes need to be smaller and denser.
  • an embodiment of the present invention also provides a wafer stack structure, including three wafers, namely a first wafer 10, a second wafer 20 and a third wafer 30.
  • the first wafer 10 is the same as that described above, and will not be repeated here.
  • the second wafer 20 includes a second substrate 201, a second dielectric layer 202 located on the second substrate 201, and a second metal layer 203 embedded in the second dielectric layer 202.
  • the second dielectric layer 202 exposes the surface of the second metal layer 203, and the second metal layer 203 of the second wafer 20 is in contact with the second interconnect layer 108 of the first wafer 10 And it is electrically connected to form a bonding interface A.
  • the third wafer 30 includes a third substrate 301, a third dielectric layer 302 located on the third substrate 301, and a third metal layer 303 embedded in the third dielectric layer 302; the second The wafer 20 is bonded to the third wafer 30 to form a bonding interface B.
  • the second wafer 20 and the third wafer 30 are formed with openings exposing the third metal layer 303 and the second metal layer 203, and the openings are filled with a fifth interconnect Layer 304, the third metal layer 303 and the second metal layer 203 are electrically connected through the fifth interconnect layer 304.
  • the second interconnection layer 108 is in contact with and electrically connected to the second metal layer 203, shortening the interconnection distance between wafers, thereby reducing parasitic capacitance and power loss, and improving transmission speed.
  • metal-to-metal second interconnection layer 108 to second metal layer 203
  • dielectric layer to dielectric layer second dielectric layer 202 to passivation layer 107
  • hybrid bonding (passivation layer 107 usually uses and dielectric
  • the layer is the same material, which can be understood as a dielectric layer) to form the first bonding interface A, and then through the subsequent heat treatment process, the metal ions are diffused to enhance the bonding force, and the metal interconnection is realized while the bonding force is enhanced, so that the first crystal The bonding strength of the circle 10 and the second wafer 20 is higher, and the interconnection of the three wafers is finally realized.
  • the first wafer 10 and the second wafer 20 are bonded to each other, the first wafer 10 and/or the second wafer 20 are thinned; After the second wafer 20 and the third wafer 30 are bonded, the third wafer 30 is thinned.
  • the present invention can realize a multi-wafer stacking structure including the first wafer 10 according to actual needs, the second wafer 20 can have multiple structures, the third wafer 30 can also have multiple structures, and adjacent wafers are bonded , To achieve higher density multi-wafer stacking and interconnection, so that the final device has more powerful functions.
  • the present invention does not limit which of the first wafer and the second wafer must be placed above or below, but the positions of the upper and lower wafers can be interchanged.
  • this article for the sake of simplicity and convenience of description, only one positional relationship between the two wafers is shown, and those skilled in the art can understand that all the technical content described in this article is also applicable to the "first crystal
  • the positions of the "circle” and the "second wafer” are upside down, the positional relationship of the layers of the stacked semiconductor device is also upside down accordingly.
  • it can also be decided whether to upside down according to actual needs, so as to determine which wafer is on top and which wafer is on the bottom.
  • first, second, third, “fourth” and other numbers are only used to distinguish different parts or processes with the same name, and do not imply the order Or location relationship, etc.
  • first substrate and second substrate for various components with the same name, such as “first substrate” and “second substrate”, “first dielectric layer” and “second dielectric layer”, etc., it does not mean that they all have the same The structure or components.
  • the substrate may be a semiconductor substrate made of any semiconductor material (such as Si, SiC, SiGe, etc.) suitable for semiconductor devices.
  • the substrate may also be various composite substrates such as silicon-on-insulator (SOI) and silicon germanium-on-insulator.
  • SOI silicon-on-insulator
  • silicon germanium-on-insulator Those skilled in the art understand that the substrate is not subject to any restrictions, but can be selected according to actual applications.
  • Various device (not limited to semiconductor device) components may be formed in the substrate.
  • the substrate may also have been formed with other layers or components, such as gate structures, contact holes, dielectric layers, metal connections, and through holes.
  • the first switch hole is filled with the first interconnect layer electrically connected to the first metal layer
  • the first contact hole is filled with a second interconnect layer; the second interconnect layer is electrically connected to the first interconnect layer; through the second interconnect layer in the first contact hole, the first switch
  • the first interconnection layer in the hole leads the first metal layer in the first wafer, that is, the first contact hole and the first switch hole are filled with the respective interconnection layers, which reduces the lead-out of the first metal layer. It is difficult to fill the holes with high aspect ratio by electroplating copper, which increases the process window.
  • the deep hole is difficult to fill when the interconnection hole between the stacked wafers to be bonded and interconnected is small in size and large in depth.
  • the thickness of multi-wafer stacks is reduced, so that the overall device thickness after multi-wafer stacking and packaging is reduced, and the packaging density is increased, so that more wafers can be accommodated in a unit volume to meet the increasingly thin and light requirements of semiconductor products.
  • the wafer integration capability is improved, and wafers with different functions are integrated on a package, so it can provide great advantages in terms of performance, function and size.

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Abstract

一种第一晶圆（10）及其形成方法、晶圆堆叠结构，第一晶圆（10）包括：第一衬底（101）、位于第一衬底（101）上的第一介质层（102）、嵌设于第一介质层（102）中的第一金属层（103）、贯穿部分第一介质层（102）并暴露出第一金属层（103）的第一开关孔（104）、填充第一开关孔（104）并与第一金属层（103）电连接的第一互连层（105）、位于所述介质层（102）和所述第一互连层（105）表面的第一绝缘层（106）、贯穿所述第一绝缘层（106）且暴露出所述第一互连层（105）的第一接触孔、填充所述第一接触孔并与所述第一互连层（105）电连接的第二互连层（108）。通过第一接触孔和第一开关孔（104）分段填充各自的互连层（105，108），降低了在引出第一金属层（103）的高深宽比的孔中采用电镀铜方式填充互连层（105，108）的工艺难度，增大了工艺窗口。

Description

第一晶圆及其形成方法、晶圆堆叠结构 技术领域
本发明属于集成电路制造技术领域，具体涉及第一晶圆及其形成方法、晶圆堆叠结构。
背景技术
在高度集成化的半导体发展的趋势下，晶圆键合是实现晶圆集成的常用技术，晶圆键合同时还需实现晶圆之间的互连，实际工艺中，晶圆键合对键合的晶圆表面的平整度有较高的要求，因此键合之前需采用化学机械抛光(CMP)工艺对晶圆表面进行平坦化处理，随后采用刻蚀工艺形成互连孔，互连孔暴露出需互连的晶圆的金属层，在互连孔中通常采用电镀铜形成与所述金属层电连接的互连层。
在现有的工艺流程下，整个工艺能力会同时受到CMP的制程能力，刻蚀工艺制程能力以及电镀铜制程能力的制约。制约主要体现在如果晶圆键合之前的表面平整度较差，那么势必需要在晶圆表面形成较厚的介质层以弥补平整度较差，而较厚的介质层所需的CMP研磨量增加，为保证CMP平坦化后整个晶圆的一致性(平整度)，在厚度方向上又不能研磨太多，如此一来，研磨后需要保留较厚的介质层，而互连孔是通过刻蚀保留的介质层以暴露出金属层，保留的介质层厚度越厚，刻蚀深度越深，同一互连孔的CD(临界尺寸)下，深宽比越大，采用电镀铜的工艺填充难度较大，整个工艺窗口较小。
发明内容
本发明的目的在于提供一种第一晶圆及其形成方法、晶圆堆叠结构，降低了在高深宽比的孔中填充互连层的工艺难度，增大了工艺窗口。
为解决上述技术问题，本发明提供一种第一晶圆，包括：
第一衬底、位于所述第一衬底上的第一介质层、嵌设于所述第一介质层中的第一金属层、贯穿部分所述第一介质层并暴露出所述第一金属层的第一开关孔、填充所述第一开关孔并与所述第一金属层电连接的第一互连层、位于所述第一介质层和所述第一互连层表面的第一绝缘层、贯穿所述第一绝缘层且暴露出所述第一互连层的第一接触孔、填充所述第一接触孔并与所述第一互连层电连接的第二互连层。
进一步的，所述第一互连层的材质包括：钨；所述第二互连层的材质包括：铜。
进一步的，所述第一接触孔与所述第一开关孔对应设置，且所述第一开关孔和所述第一接触孔各自包括多个间隔分布的孔。
本发明还提供一种第一晶圆的形成方法，包括：
提供第一衬底，所述第一衬底上形成有第一介质层，所述第一介质层中嵌设有第一金属层；
形成第一开关孔，所述第一开关孔贯穿部分所述第一介质层并暴露出所述第一金属层；
形成第一互连层，所述第一互连层填充所述第一开关孔并与所述第一金属层电连接；
形成第一绝缘层，所述第一绝缘层覆盖所述第一介质层和所述第一互连层表面；
形成第一接触孔，所述第一接触孔贯穿所述第一绝缘层，且暴露出所述第一互连层；以及，
形成第二互连层，所述第二互连层填充所述第一接触孔并与所述第一互连层电连接。
本发明还提供一种晶圆堆叠结构，包括：
第一晶圆和第二晶圆，所述第一晶圆包括第一衬底、位于所述第一衬底 上的第一介质层、嵌设于所述第一介质层中的第一金属层、贯穿部分所述第一介质层并暴露出所述第一金属层的第一开关孔、填充所述第一开关孔并与所述第一金属层电连接的第一互连层、位于所述第一介质层和所述第一互连层表面的第一绝缘层、贯穿所述第一绝缘层且暴露出所述第一互连层的第一接触孔、填充所述第一接触孔并与所述第一互连层电连接的第二互连层；
所述第二晶圆包括第二衬底、位于所述第二衬底上的第二介质层、嵌设于所述第二介质层中的第二金属层，所述第一晶圆与所述第二晶圆键合，所述第一金属层与所述第二金属层电连接。
进一步的，所述第二介质层暴露出所述第二金属层的表面，所述第二晶圆的所述第二金属层与所述第一晶圆的所述第二互连层接触且电连接，并形成键合界面。
进一步的，所述第二晶圆还包括第二开关孔和第三互连层；所述第二开关孔贯穿部分所述第二介质层并暴露出所述第二金属层；所述第三互连层填充所述第二开关孔并与所述第二金属层电连接。
进一步的，所述第二晶圆的所述第三互连层与所述第一晶圆的所述第二互连层接触且电连接，并形成键合界面。
进一步的，所述第二晶圆还包括第二绝缘层、第二接触孔和第四互连层，所述第二绝缘层位于所述第二介质层和所述第三互连层表面；所述第二接触孔贯穿所述第二绝缘层且暴露出所述第三互连层；所述第四互连层填充所述第二接触孔；所述第四互连层与所述第三互连层电连接；所述第二晶圆的所述第四互连层与所述第一晶圆的所述第二互连层接触且电连接，并形成键合界面。
进一步的，所述晶圆堆叠结构还包括：第三晶圆，所述第三晶圆包括第三衬底、位于所述第三衬底上的第三介质层、嵌设于所述第三介质层中的第三金属层；所述第二晶圆与所述第三晶圆键合；所述第二晶圆和所述第三晶圆中形成有暴露出所述第三金属层和所述第二金属层的开孔，所述开孔中填 充有第五互连层，所述第三金属层和所述第二金属层通过所述第五互连层电连接。
与现有技术相比，本发明具有如下有益效果：
本发明提供的第一晶圆及其形成方法、晶圆堆叠结构中，所述第一开关孔中填充有与所述第一金属层电连接的所述第一互连层；所述第一接触孔中填充有第二互连层；所述第二互连层与所述第一互连层电连接；通过第一接触孔中的第二互连层、第一开关孔中的第一互连层将所述第一晶圆中的第一金属层引出，即通过第一接触孔和第一开关孔分段填充各自的互连层，降低了在引出第一金属层的高深宽比的孔中采用电镀铜方式填充互连层的工艺难度，增大了工艺窗口。解决了待键合及互连的堆叠晶圆之间的互连孔较小尺寸时且深度较大，深孔填充难的问题。
附图说明
图1为本发明实施例的第一晶圆的剖面示意图；
图2为本发明实施例的第一晶圆的形成方法流程示意图；
图3至图8为本发明实施例的第一晶圆的形成方法各步骤示意图。
图9为本发明实施例的第一种晶圆堆叠结构的剖面示意图；
图10为本发明实施例的第二种晶圆堆叠结构的剖面示意图；
图11为本发明实施例的第三种晶圆堆叠结构的剖面示意图；
图12为本发明实施例的第四种晶圆堆叠结构的剖面示意图；
其中，附图标记如下：
10-第一晶圆；101-第一衬底；102-第一介质层；102a-第一介质层第一部分；102b-第一介质层第二部分；103-第一金属层；104-第一开关孔；
105-第一互连层；106-第一绝缘层；107-第一钝化层；108-第二互连层；
20-第二晶圆；201-第二衬底；202-第二介质层；203-第二金属层；205-第三互连层；206-第二绝缘层；207-第二钝化层；208-第四互连层；
30-第三晶圆；301-第三衬底；302-第三介质层；303-第三金属层；304-第五互连层；
A-键合界面；B-键合界面。
具体实施方式
以下结合附图和具体实施例对本发明提出的第一晶圆及其形成方法、晶圆堆叠结构作进一步详细说明。根据下面说明，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
本发明实施例提供一种第一晶圆，如图1所示，
第一晶圆10包括第一衬底101、位于所述第一衬底101上的第一介质层102、嵌设于所述第一介质层102中的第一金属层103、第一开关孔(第一互连层105填充的孔)、第一互连层105、第一绝缘层106、第一接触孔(第二互连层108填充的孔)和第二互连层108，所述第一开关孔贯穿其所在第一晶圆10的部分所述第一介质层102并暴露出部分所述第一金属层103；所述第一开关孔中填充有与所述金属层103电连接的所述第一互连层105；所述第一绝缘层106位于所述介质层102和所述第一互连层105表面；所述第一接触孔贯穿所述绝缘层106且暴露出所述第一互连层105；所述第一接触孔中填充有第二互连层108；所述第二互连层108与所述第一互连层105电连接；具体的，所述第一互连层105的材质包括：钨；所述第二互连层108的材质包括：铜。第一接触孔与所述第一开关孔对应设置，且所述第一开关孔和所述第一接触孔各自包括多个间隔分布的孔。
图2为本发明实施例的第一晶圆的形成方法流程示意图；如图2所示，本发明实施例提供一种第一晶圆的形成方法，包括：
提供第一衬底，所述第一衬底上形成有第一介质层，所述第一介质层中嵌设有第一金属层；
形成第一开关孔，所述第一开关孔贯穿部分所述第一介质层并暴露出所述第一金属层；
形成第一互连层，所述第一互连层填充所述第一开关孔并与所述第一金属层电连接；
形成第一绝缘层，所述第一绝缘层覆盖所述第一介质层和所述第一互连层表面；
形成第一接触孔，所述第一接触孔贯穿所述第一绝缘层，且暴露出所述第一互连层；以及，
形成第二互连层，所述第二互连层填充所述第一接触孔并与所述第一互连层电连接。
下面结合图3至图8详细介绍本发明实施例的第一晶圆10的形成方法。
如图3所示，提供第一衬底101，所述第一衬底101上形成有第一介质层第一部分102a、在所述第一介质层第一部分102a上形成若干第一金属层103。
如图4所示，在所述第一介质层第一部分102a上形成覆盖第一金属层103的第一介质层第二部分102b，第一介质层第一部分102a和第一介质层第二部分102b构成第一介质层102，并采用CMP平坦化所述第一介质层102表面。
如图5所示，形成第一开关孔104，所述第一开关孔104贯穿部分所述第一介质层102并暴露出部分所述第一金属层103。
如图6所示，在所述第一开关孔104中填充与第一金属层103电连接的第一互连层105；第一互连层105包括金属钨，钨具有高传导性和较高的填孔能力。可采用蒸发、溅射或化学气相沉积(CVD)工艺形成，优选CVD法进行钨沉积，CVD钨具有低电阻率、对电迁移的高抵抗力以及填充小通孔时的优异的平整性。CVD钨还可以在金属上进行选择性淀积。CVD方法的钨可以由氯化钨、氟化钨和羟基钨制备而成。主要反应气体有六氟化钨以及氢气或甲硅烷。通过改变以下参数可以提高钨的填孔能力：例如1、增加成核时WF 6/SiH 4比率，以及WF 6，SiH 4占的分压及反应室的总压力；2、增加快速沉积WF 6/H 2 比率及反应室压力；3、增加预热的压力；4、降低反应的温度。在填充过程中，第一互连层105还会覆盖第一介质层102的表面，可采用CMP或回刻蚀工艺将第一介质层102表面的第一互连层去除且平坦化表面，留下所述第一开关孔104中的第一互连层105。
如图7和图8所示，形成第一绝缘层106，所述第一绝缘层106覆盖所述第一介质层102和所述第一互连层105表面；所述第一绝缘层106可作为后续形成第一接触孔(第二互连层108填充的孔)的刻蚀停止层。进一步的，在第一绝缘层106表面还形成有钝化层107；所述钝化层107例如是氧化层起保护第一晶圆10表面的作用。
如图8所示，形成第一接触孔(第二互连层108填充的孔)，所述第一接触孔贯穿所述钝化层107和第一绝缘层106，且暴露出所述第一互连层105；在所述第一接触孔中填充第二互连层108；所述第二互连层108与所述第一互连层105电连接。
第一接触孔(第二互连层108填充的孔)与第一开关孔(第一互连层105填充的孔)对应设置。第二互连层108包括铜，可采用电镀形成，之后采用CMP工艺平坦化钝化层107和第二互连层108表面，以形成平坦的键合界面。
可选的，所述第一晶圆10还包括第一刻蚀停止层，所述第一刻蚀停止层位于所述第一金属层103与所述第一介质层第二部分102b之间。
本发明实施例还提供一种晶圆堆叠结构，包括：第一晶圆和第二晶圆。
所述第一晶圆包括第一衬底、位于所述第一衬底上的第一介质层、嵌设于所述第一介质层中的第一金属层、贯穿部分所述第一介质层并暴露出所述第一金属层的第一开关孔、填充所述第一开关孔并与所述第一金属层电连接的第一互连层、位于所述介质层和所述第一互连层表面的第一绝缘层、贯穿所述第一绝缘层且暴露出所述第一互连层的第一接触孔、填充所述第一接触孔并与所述第一互连层电连接的第二互连层。
所述第二晶圆包括第二衬底、位于所述第二衬底上的第二介质层、嵌设 于所述第二介质层中的第二金属层，所述第一晶圆与所述第二晶圆键合，所述第一金属层与所述第二金属层电连接。
本实施例中，所述第一开关孔中填充有与所述金属层电连接的所述第一互连层；所述第一接触孔中填充有第二互连层；所述第二互连层与所述第一互连层电连接；所述第一晶圆的所述第二互连层与所述第二晶圆的金属层电连接。通过第一接触孔中的第二互连层、第一开关孔中的第一互连层实现键合的两晶圆的互连，即通过第一接触孔和第一开关孔分布填充各自的互连层，降低了深宽比大的孔电镀铜的工艺难度，增大了工艺窗口。解决了待键合及互连的堆叠晶圆之间的互连孔较小尺寸时且深度较大，深孔填充难的问题。
如图9所示，本发明实施例提供的晶圆堆叠结构，包括：第一晶圆10和第二晶圆20。第一晶圆10包括第一衬底101、位于所述第一衬底101上的第一介质层102、嵌设于所述第一介质层102中的第一金属层103、第一开关孔(第一互连层105填充的孔)、第一互连层105、第一绝缘层106、第一接触孔(第二互连层108填充的孔)和第二互连层108，所述第一开关孔贯穿其所在第一晶圆10的部分所述第一介质层102并暴露出部分所述第一金属层103；所述第一开关孔中填充有与所述金属层103电连接的所述第一互连层105；所述第一绝缘层106位于所述介质层102和所述第一互连层105表面；所述第一接触孔贯穿所述绝缘层106且暴露出所述第一互连层105；所述第一接触孔中填充有第二互连层108；所述第二互连层108与所述第一互连层105电连接；所述第一互连层105的材质包括：钨；所述第二互连层108的材质包括：铜。第一接触孔与所述第一开关孔对应设置。
所述第二晶圆20包括第二衬底201、位于所述第二衬底201上的第二介质层202、嵌设于所述第二介质层202中的第二金属层203，所述第一晶圆10与所述第二晶圆20键合，所述第一金属层103与所述第二金属层203电连接。具体的，所述第二介质层202暴露出所述第二金属层203的表面，所述第二晶圆20的所述第二金属层203与所述第一晶圆10的所述第二互连层108接 触且电连接，并形成键合界面A。
本实施例适用于待键合的第一晶圆10的互连孔(从键合界面A到第一金属层103上表面的孔)尺寸较小且深度较深(即深宽比较大)，第二晶圆20的第二金属层203裸露(例如为工艺半成品状态)，第一晶圆10的互连孔的深度为键合界面A到第一金属层103上表面的距离。
进一步的，如图10所示，所述第二晶圆20还包括第二开关孔(第三互连层205填充的孔)和第三互连层205；所述第二开关孔贯穿部分所述第二介质层202并暴露出所述第二金属层203；所述第三互连层205填充所述第二开关孔并与所述第二金属层203电连接。所述第二晶圆20的所述第三互连层205与所述第一晶圆10的所述第二互连层108接触且电连接，并形成键合界面A。
本实施例适用于待键合的第一晶圆10的互连孔(从键合界面A到第一金属层103的孔)尺寸较小且深度较大(即深宽比较大)，第二晶圆20的互连孔(从键合界面A到第二金属层203的孔)深度较小的应用。具体的，第一晶圆10的互连孔的深度为键合界面A到第一金属层103的距离，第二晶圆20的互连孔的深度为键合界面A到第二金属层203的距离。
进一步的，如图11所示，所述第二晶圆20还包括第二绝缘层206、第二接触孔(第四互连层208填充的孔)和第四互连层208，所述第二绝缘层206位于所述第二介质层202和所述第三互连层205表面；所述第二接触孔(第四互连层208填充的孔)贯穿所述第二绝缘层206且暴露出所述第三互连层205；所述第四互连层208填充所述第二接触孔；所述第四互连层208与所述第三互连层205电连接；所述第二晶圆20的所述第四互连层208与所述第一晶圆10的所述第二互连层108接触且电连接，并形成键合界面A。本实施例中，第二晶圆20与第一晶圆10的结构相同或者相近。
本实施例适用于待键合且电连接的两晶圆的互连孔(从键合界面到金属层的孔)均尺寸较小且深度较深(即深宽比较大)的应用。具体的，第一晶圆的互连孔的深度为键合界面A到第一金属层103的距离，第二晶圆20的互 连孔的深度为键合界面A到第二金属层203的距离。
为了减少晶圆堆叠互连后的整体厚度，第一晶圆10和第二晶圆20相互键合后，可对所述第一晶圆10和/或所述第二晶圆20进行减薄。
可选的，如图11所示，第一接触孔(第二互连层108填充的孔)与所述第一开关孔(第一互连层105填充的孔)对应设置，每个第一开关孔和每个第一接触孔各自包括多个间隔分布的孔，即，每个第一开关孔和每个第一接触孔均是由多个孔组成的阵列孔组。同理，每个第二开关孔(第三互连层205填充的孔)和每个第二接触孔(第四互连层208填充的孔)均是由多个孔组成的阵列孔组。在多个间隔分布的孔中，第二互连层108与第四互连层208相接触，增加互连可靠性的同时间隔设置降低互连层工作中产生的热量。而且，多个间隔分布的孔可以做到尺寸更小、密度更大，从而还能满足某些特定用途的产品互连需求，例如需互连引出的信号为密度高且电流低的信号，相应的孔以及孔中的互连层均需尺寸更小、密度更大。
接着，如图12所示，本发明实施例还提供一种晶圆堆叠结构，包括：三个晶圆，分别为第一晶圆10、第二晶圆20和第三晶圆30。所述第一晶圆10和前面所述相同，不再赘述。所述第二晶圆20包括第二衬底201、位于所述第二衬底201上的第二介质层202、嵌设于所述第二介质层202中的第二金属层203，所述第二介质层202暴露出所述第二金属层203的表面，所述第二晶圆20的所述第二金属层203与所述第一晶圆10的所述第二互连层108接触且电连接，并形成键合界面A。
第三晶圆30包括第三衬底301、位于所述第三衬底301上的第三介质层302、嵌设于所述第三介质层302中的第三金属层303；所述第二晶圆20与所述第三晶圆30键合，并形成键合界面B。所述第二晶圆20和所述第三晶圆30中形成有暴露出所述第三金属层303和所述第二金属层203的开孔，所述开孔中填充有第五互连层304，所述第三金属层303和所述第二金属层203通过所述第五互连层304电连接。
第二互连层108与第二金属层203相接触且电连接，缩短晶圆间互连距离，进而降低寄生电容和功率损耗，提高了传输速度。采用金属对金属(第二互连层108对第二金属层203)和介质层对介质层(第二介质层202对钝化层107)的混合键合，(钝化层107通常采用和介质层相同材质，可理解为介质层)，形成第一键合界面A，再通过后续热处理工艺，使得金属离子扩散而增强键合力，实现金属互连的同时还增强了键合力，使第一晶圆10和第二晶圆20两晶圆结合强度更高，最终实现三个晶圆的互连。
为了减少晶圆堆叠互连后的整体厚度，第一晶圆10和第二晶圆20相互键合后，对所述第一晶圆10和/或所述第二晶圆20进行减薄；第二晶圆20和第三晶圆30进行键合后，对所述第三晶圆30进行减薄。
本发明根据实际需要可实现包括第一晶圆10的多晶圆堆叠结构，第二晶圆20可为多种结构，第三晶圆30也可为多种结构，相邻的晶圆键合，实现更高密度的多晶圆堆叠以及互连，使最终器件具有更强大功能。
本发明并不限定第一晶圆和第二晶圆哪个晶圆必须要放在上方/下方，而是可以互换上下晶圆的位置。在本文中，为了描述简单、方便，只示出了这两个晶圆的一种位置关系，而本领域技术人员均能理解，在本文中描述的所有技术内容也同样适用于“第一晶圆”与“第二晶圆”的位置上下颠倒的情况，此时堆叠式半导体装置的各层的位置关系也相应地上下颠倒。在一些情况下，优选地，在对两个晶圆进行键合处理期间，将晶圆弯曲度(bow)比较大的晶圆放在下面。但是，在这种情况下，在晶圆键合结束后，也可以根据实际需求来决定是否上下颠倒，从而确定最终哪个晶圆在上面哪个晶圆在下面。
请注意，在本文中，“第一”、“第二”、“第三”、“第四”等编号只是为了对具有相同名称的各个不同部件或工艺进行区分之用，并不意味着顺序或位置关系等。另外，对于具有相同名称的各个不同部件，例如“第一衬底”和“第二衬底”、“第一介质层”和“第二介质层”等等，并不意味着它们都具有相同的结构或部件。例如，尽管图中未示出，但是在绝大部分情况下，“第 一衬底”和“第二衬底”中形成的部件都不一样，衬底的结构也可能不一样。在一些实施方式中，衬底可以为半导体衬底，由适合于半导体装置的任何半导体材料(诸如Si、SiC、SiGe等)制成。在另一些实施方式中，衬底也可以为绝缘体上硅(SOI)、绝缘体上锗硅等各种复合衬底。本领域技术人员均理解衬底不受到任何限制，而是可以根据实际应用进行选择。衬底中可以形成有各种装置(不限于半导体装置)构件(图中未示出)。衬底还可以已经形成有其他层或构件，例如：栅极结构、接触孔、介质层、金属连线和通孔等等。
综上所述，本发明提供的第一晶圆及其形成方法、晶圆堆叠结构中，所述第一开关孔中填充有与所述第一金属层电连接的所述第一互连层；所述第一接触孔中填充有第二互连层；所述第二互连层与所述第一互连层电连接；通过第一接触孔中的第二互连层、第一开关孔中的第一互连层将所述第一晶圆中的第一金属层引出，即通过第一接触孔和第一开关孔分别填充各自的互连层，降低了在引出第一金属层的高深宽比的孔中采用电镀铜方式填充的工艺难度，增大了工艺窗口。解决了待键合及互连的堆叠晶圆之间的互连孔较小尺寸时且深度较大，深孔填充难的问题。实现晶圆互连的同时减少多晶圆堆叠厚度从而使多晶圆堆叠封装后的整体器件厚度减小，增加封装密度，使单位体积内容纳更多晶圆，满足半导体产品日益走向轻薄要求。提高了晶圆整合能力，将不同功能的晶圆整合在一个封装体上，因此在性能、功能和尺寸上，可提供极大的优势。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (17)

  1. 一种第一晶圆，其特征在于，包括：
    第一衬底、位于所述第一衬底上的第一介质层、嵌设于所述第一介质层中的第一金属层、贯穿部分所述第一介质层并暴露出所述第一金属层的第一开关孔、填充所述第一开关孔并与所述第一金属层电连接的第一互连层、位于所述第一介质层和所述第一互连层表面的第一绝缘层、贯穿所述第一绝缘层且暴露出所述第一互连层的第一接触孔、填充所述第一接触孔并与所述第一互连层电连接的第二互连层。
  2. 如权利要求1所述的第一晶圆，其特征在于，所述第一互连层由包括钨的材质制成；所述第二互连层由包括铜的材质制成。
  3. 如权利要求1所述的第一晶圆，其特征在于，所述第一接触孔与所述第一开关孔对应设置，且所述第一开关孔和所述第一接触孔各自包括多个间隔分布的孔。
  4. 如权利要求1所述的第一晶圆，其特征在于，还包括沉积在所述第一绝缘层上的钝化层，其中，所述钝化层为氧化层。
  5. 一种第一晶圆的形成方法，其特征在于，包括：
    提供第一衬底，所述第一衬底上形成有第一介质层，所述第一介质层中嵌设有第一金属层；
    形成第一开关孔，所述第一开关孔贯穿部分所述第一介质层并暴露出所述第一金属层；
    形成第一互连层，所述第一互连层填充所述第一开关孔并与所述第一金属层电连接；
    形成第一绝缘层，所述第一绝缘层覆盖所述第一介质层和所述第一互连层表面；
    形成第一接触孔，所述第一接触孔贯穿所述第一绝缘层，且暴露出所述 第一互连层；以及，
    形成第二互连层，所述第二互连层填充所述第一接触孔并与所述第一互连层电连接。
  6. 如权利要求5所述的方法，其特征在于，所述第一互连层由包括钨的材质制成；所述第二互连层由包括铜的材质制成。
  7. 如权利要求5所述的方法，其特征在于，所述第一接触孔与所述第一开关孔对应设置，且所述第一开关孔和所述第一接触孔各自包括多个间隔分布的孔。
  8. 如权利要求5所述的方法，其特征在于，还包括在所述第一绝缘层上沉积钝化层，其中，所述钝化层为氧化层。
  9. 一种晶圆堆叠结构，其特征在于，包括：
    第一晶圆和第二晶圆，所述第一晶圆包括第一衬底、位于所述第一衬底上的第一介质层、嵌设于所述第一介质层中的第一金属层、贯穿部分所述第一介质层并暴露出所述第一金属层的第一开关孔、填充所述第一开关孔并与所述第一金属层电连接的第一互连层、位于所述第一介质层和所述第一互连层表面的第一绝缘层、贯穿所述第一绝缘层且暴露出所述第一互连层的第一接触孔、填充所述第一接触孔并与所述第一互连层电连接的第二互连层；
    所述第二晶圆包括第二衬底、位于所述第二衬底上的第二介质层、嵌设于所述第二介质层中的第二金属层，所述第一晶圆与所述第二晶圆键合，所述第一金属层与所述第二金属层电连接。
  10. 如权利要求9所述的晶圆堆叠结构，其特征在于，所述第二介质层暴露出所述第二金属层的表面，所述第二晶圆的所述第二金属层与所述第一晶圆的所述第二互连层接触且电连接，并形成键合界面。
  11. 如权利要求9所述的晶圆堆叠结构，其特征在于，所述第二晶圆还包括第二开关孔和第三互连层；所述第二开关孔贯穿部分所述第二介质层并暴露出所述第二金属层；所述第三互连层填充所述第二开关孔并与所述第二 金属层电连接。
  12. 如权利要求11所述的晶圆堆叠结构，其特征在于，所述第二晶圆的所述第三互连层与所述第一晶圆的所述第二互连层接触且电连接，并形成键合界面。
  13. 如权利要求11所述的晶圆堆叠结构，其特征在于，所述第二晶圆还包括第二绝缘层、第二接触孔和第四互连层，所述第二绝缘层位于所述第二介质层和所述第三互连层表面；所述第二接触孔贯穿所述第二绝缘层且暴露出所述第三互连层；所述第四互连层填充所述第二接触孔；所述第四互连层与所述第三互连层电连接；所述第二晶圆的所述第四互连层与所述第一晶圆的所述第二互连层接触且电连接，并形成键合界面。
  14. 如权利要求10所述的晶圆堆叠结构，其特征在于，还包括：第三晶圆，所述第三晶圆包括第三衬底、位于所述第三衬底上的第三介质层、嵌设于所述第三介质层中的第三金属层；所述第二晶圆与所述第三晶圆键合。
  15. 如权利要求14所述的晶圆堆叠结构，其特征在于，所述第二晶圆和所述第三晶圆中形成有暴露出所述第三金属层和所述第二金属层的开孔，所述开孔中填充有第五互连层，所述第三金属层和所述第二金属层通过所述第五互连层电连接。
  16. 如权利要求9所述的晶圆堆叠结构，其特征在于，所述第一互连层由包括钨的材质制成；所述第二互连层由包括铜的材质制成。
  17. 如权利要求9所述的晶圆堆叠结构，其特征在于，还包括沉积在所述第一绝缘层上的钝化层，其中，所述钝化层为氧化层。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103378109A (zh) * 2012-04-27 2013-10-30 台湾积体电路制造股份有限公司 用于垂直集成的背照式图像传感器的装置
US20160247747A1 (en) * 2008-05-15 2016-08-25 Micron Technology, Inc. Disabling electrical connections using pass-through 3d interconnects and associated systems and methods
CN107994043A (zh) * 2017-12-11 2018-05-04 德淮半导体有限公司 晶圆、堆叠式半导体装置及其制造方法
CN109148415A (zh) * 2018-08-28 2019-01-04 武汉新芯集成电路制造有限公司 多晶圆堆叠结构及其形成方法
CN109411443A (zh) * 2017-08-16 2019-03-01 格芯公司 垂直堆叠晶圆及其形成方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109166840B (zh) * 2018-08-28 2019-07-23 武汉新芯集成电路制造有限公司 多晶圆堆叠结构及其形成方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160247747A1 (en) * 2008-05-15 2016-08-25 Micron Technology, Inc. Disabling electrical connections using pass-through 3d interconnects and associated systems and methods
CN103378109A (zh) * 2012-04-27 2013-10-30 台湾积体电路制造股份有限公司 用于垂直集成的背照式图像传感器的装置
CN109411443A (zh) * 2017-08-16 2019-03-01 格芯公司 垂直堆叠晶圆及其形成方法
CN107994043A (zh) * 2017-12-11 2018-05-04 德淮半导体有限公司 晶圆、堆叠式半导体装置及其制造方法
CN109148415A (zh) * 2018-08-28 2019-01-04 武汉新芯集成电路制造有限公司 多晶圆堆叠结构及其形成方法

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