JP2011527512A - 半導体素子の製造方法および半導体素子 - Google Patents
半導体素子の製造方法および半導体素子 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 55
- 239000002184 metal Substances 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims description 38
- 230000001681 protective effect Effects 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 9
- 238000005496 tempering Methods 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims 2
- 239000012212 insulator Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 67
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 235000012431 wafers Nutrition 0.000 description 9
- 239000013067 intermediate product Substances 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005755 formation reaction Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 238000000708 deep reactive-ion etching Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
- 230000014616 translation Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Abstract
【選択図】図8
Description
これらの成膜の、従って、異なる熱特性の層を有する実施形態においては、焼き戻し処理は保護膜13を成膜する前、あるいは完全に成膜し終える前に行われるのが好ましい。よって、いずれの場合も、焼き戻し処理は、保護膜13の最後の層が形成される前に行われる。
2 絶縁層
3 半導体層
4 金属間誘電体
5 金属層
6 ライナ
7 接続パッド
8 マスク
9 開口部
10 誘電体層
11 金属膜
12 頂部金属
13 保護膜
Claims (17)
- 半導体材料からなる基板(1)に、内蔵された絶縁層(2)と、絶縁層(2)に配置された導電材料からなる接続パッド(7)とを形成し、
前記接続パッド(7)の上部に、基板(1)の上面から絶縁層(2)に至る開口部(9)を形成し、
誘電体層(10)を成膜し、
誘電体層(10)及び絶縁層(2)を、接続パッド(7)の上面が露出する程度に、開口部(9)内から除去し、
接続パッド(7)と接触する金属膜(11)を成膜し、
そして、
ビアコンタクトを、開口部(9)の反対に位置する側の基板(1)の裏面から接続パッド(7)に至るまで形成することを特徴とする、半導体素子の製造方法。 - 前記開口部(9)を、異方性エッチングによって垂直側壁を有するように形成することを特徴とする、請求項1に記載の方法。
- 開口部(9)の外側の金属膜(11)を除去するとともに、
頂部金属(12)を、金属膜(11)の上縁に接触するように成膜することを特徴とする、請求項1あるいは2に記載の方法。 - 前記金属膜(11)を、まず表面全体に形成し、次いで、開口部(9)の底部及び側壁におけるエッチング率よりも上面におけるエッチング率の方が高くなるようにエッチバックして、金属膜(11)の一部分が開口部(9)の底部に残るようにすることを特徴とする、請求項1から3のいずれかに記載の方法。
- 基板(1)の上面は、エッチングによって開口部(9)を形成する前は、金属間誘電体(4)及び配線の金属層(5)を備え、
金属間誘電体(4)の上面は、ライナ6で覆われ、
ライナ(6)が誘電体層(10)の部分除去のためのエッチング停止層として機能するようにライナ6の材料が選択されることを特徴とする、請求項1から4のいずれかに記載の方法。 - 基板(1)を、第1半導体本体が、その上面に絶縁体層(2)を備えるようにして製造し、
第2半導体本体を前記絶縁層(2)上に載置し、
前記半導体本体の接続に先立ち、接続パッド(7)を、前記絶縁層(2)の上あるいは、前記絶縁層(2)に接続される第2半導体本体の上部に成膜することを特徴とする、請求項1から5のいずれかに記載の方法。 - 保護膜(13)を、前記金属膜(11)上に形成することを特徴とする、請求項1から6のいずれかに記載の方法。
- 前記保護膜(13)は、異なる材料からなる少なくとも2つの層から形成されることを特徴とする、請求項7に記載の方法。
- 前記保護膜(13)を、最初に酸化物層を成膜し、次に窒化物層を前記酸化物層の上に成膜して形成することを特徴とする、請求項7に記載の方法。
- 焼き戻し処理を、保護膜(13)が成膜される前にのみ行うことを特徴とする、請求項7から9のいずれかに記載の方法。
- 焼き戻し処理を、保護膜(13)の最後の層が成膜される前にのみ行うことを特徴とする、請求項8または9に記載の方法。
- 内蔵された絶縁層(2)と、絶縁層(2)に配置された導電性接続パッド(7)とを備えた基板(1)が設けられ、
前記接続パッド(7)に導電接続されるともに、前記基板に形成された開口部(9)の側壁を覆う金属膜(11)が設けられ、
接続パッド(7)まで延びるビアコンタクトが、開口部(9)の反対に位置する側の基板(1)の裏面に設けられていることを特徴とする、ビアコンタクトを備えた半導体素子。 - 前記金属膜(11)の一部分は接続パッド(7)の表面を覆っていることを特徴とする、請求項12に記載の半導体素子。
- 前記金属膜(11)は、前記素子の頂部において頂部金属(12)と導電的に接続されていることを特徴とする、請求項12または13に記載の半導体素子。
- 前記金属膜(11)は、開口部(9)を部分的にのみ充たす保護膜(13)で覆われていることを特徴とする、請求項12から14のいずれかに記載の半導体素子。
- 前記保護膜(13)は酸化物層及び窒化物層を有することを特徴とする、請求項15に記載の半導体素子。
- 接続パッド(7)は、絶縁層(2)の、開口部(9)と反対側に位置する集積部品構成部上に、絶縁層(2)内に配置された電気供給ライン(14)を備えることを特徴とする、請求項12から16のいずれかに記載の半導体素子。
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DE102008033395.6 | 2008-07-16 | ||
DE102008033395A DE102008033395B3 (de) | 2008-07-16 | 2008-07-16 | Verfahren zur Herstellung eines Halbleiterbauelementes und Halbleiterbauelement |
PCT/EP2009/058001 WO2010006916A1 (de) | 2008-07-16 | 2009-06-25 | Verfahren zur herstellung eines halbleiterbauelementes und halbleiterbauelement |
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Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102009004725A1 (de) | 2009-01-15 | 2010-07-29 | Austriamicrosystems Ag | Halbleiterschaltung mit Durchkontaktierung und Verfahren zur Herstellung vertikal integrierter Schaltungen |
DE102009049102B4 (de) | 2009-10-13 | 2012-10-04 | Austriamicrosystems Ag | Halbleiterbauelement mit Durchkontaktierung und Verfahren zur Herstellung einer Durchkontaktierung in einem Halbleiterbauelement |
US9559001B2 (en) * | 2010-02-09 | 2017-01-31 | Xintec Inc. | Chip package and method for forming the same |
JP6342033B2 (ja) * | 2010-06-30 | 2018-06-13 | キヤノン株式会社 | 固体撮像装置 |
JP2012033894A (ja) | 2010-06-30 | 2012-02-16 | Canon Inc | 固体撮像装置 |
US8697569B2 (en) * | 2010-07-23 | 2014-04-15 | Tessera, Inc. | Non-lithographic formation of three-dimensional conductive elements |
DE102010045055B4 (de) | 2010-09-10 | 2019-03-28 | Austriamicrosystems Ag | Verfahren zur Herstellung eines Halbleiterbauelementes mit einer Durchkontaktierung |
US8847233B2 (en) | 2011-05-12 | 2014-09-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a trenched insulating layer coated with an oxide semiconductor film |
DE102011104305A1 (de) * | 2011-06-16 | 2012-12-20 | Austriamicrosystems Ag | Herstellungsverfahren für ein Halbleiterbauelement mit einer Leiterschicht im Halbleiterkörper und Halbleiterbauelement |
DE102011080774B4 (de) * | 2011-08-10 | 2015-02-19 | Hahn-Schickard-Gesellschaft für angewandte Forschung e.V. | Verfahren zum herstellen einer halbleiterstruktur und halbleiterstruktur |
EP2693467B1 (en) | 2012-08-01 | 2015-11-18 | ams AG | A method of producing a semiconductor device having an interconnect through the substrate |
EP2741322B1 (en) | 2012-12-10 | 2016-04-27 | ams AG | Semiconductor device with integrated hot plate and recessed substrate and method of production |
EP2772939B1 (en) | 2013-03-01 | 2016-10-19 | Ams Ag | Semiconductor device for detection of radiation and method of producing a semiconductor device for detection of radiation |
EP2774891B1 (en) | 2013-03-05 | 2019-10-23 | ams AG | Semiconductor device with capacitive sensor and integrated circuit |
EP2775275B1 (en) | 2013-03-08 | 2015-12-16 | Ams Ag | Ultraviolet semiconductor sensor device and method of measuring ultraviolet radiation |
EP2790211B1 (en) | 2013-04-10 | 2018-06-20 | Ams Ag | Method of producing a through-substrate via in a semiconductor device and semiconductor device comprising a through-substrate via |
EP2899760B1 (en) | 2014-01-27 | 2018-08-29 | ams AG | Semiconductor device for optical applications and method of producing such a semiconductor device |
EP3312874A1 (en) | 2016-10-20 | 2018-04-25 | ams AG | Method of forming a through-substrate via and a semiconductor device comprising a through-substrate via |
EP3550600B1 (en) | 2018-04-04 | 2020-08-05 | ams AG | Method of forming a through-substrate via and semiconductor device comprising the through-substrate via |
WO2019226432A1 (en) * | 2018-05-21 | 2019-11-28 | Corning Incorporated | Liquid lenses and methods of manufacturing liquid lenses |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01128562A (ja) * | 1987-11-13 | 1989-05-22 | Nissan Motor Co Ltd | 半導体装置 |
JPH04304663A (ja) * | 1991-04-02 | 1992-10-28 | Nissan Motor Co Ltd | 半導体デバイス |
JPH07505982A (ja) * | 1993-01-19 | 1995-06-29 | ヒューズ・エアクラフト・カンパニー | 深い導電性フィードスルーの形成方法,および該方法に従って形成されたフィードスルーを含む配線層 |
JP2002508590A (ja) * | 1998-03-26 | 2002-03-19 | フラウンホッファー−ゲゼルシャフト ツァ フェルダールング デァ アンゲヴァンテン フォアシュンク エー.ファオ. | 垂直集積した回路構造を作製するための配線方法および垂直集積した回路構造 |
JP2004349513A (ja) * | 2003-05-22 | 2004-12-09 | Seiko Epson Corp | 薄膜回路装置及びその製造方法、並びに電気光学装置、電子機器 |
JP2005012180A (ja) * | 2003-05-28 | 2005-01-13 | Okutekku:Kk | 半導体装置およびその製造方法 |
JP2005116623A (ja) * | 2003-10-03 | 2005-04-28 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP2006128172A (ja) * | 2004-10-26 | 2006-05-18 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
WO2006131209A2 (de) * | 2005-06-07 | 2006-12-14 | Austriamicrosystems Ag | Photodiode mit integrierter halbleiterschaltung und verfahren zur herstellung |
JP2007242676A (ja) * | 2006-03-06 | 2007-09-20 | Sanyo Electric Co Ltd | 半導体装置製造方法 |
JP2007305960A (ja) * | 2006-04-14 | 2007-11-22 | Sharp Corp | 半導体装置およびその製造方法 |
JP2008085020A (ja) * | 2006-09-27 | 2008-04-10 | Nec Electronics Corp | 半導体装置 |
US20080157394A1 (en) * | 2006-12-29 | 2008-07-03 | Samsung Electronics Co., Ltd. | Semiconductor packages, stacked semiconductor packages, and methods of manufacturing the semiconductor packages and the stacked semiconductor packages |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3986196A (en) | 1975-06-30 | 1976-10-12 | Varian Associates | Through-substrate source contact for microwave FET |
DE3850855T2 (de) * | 1987-11-13 | 1994-11-10 | Nissan Motor | Halbleitervorrichtung. |
US5426072A (en) * | 1993-01-21 | 1995-06-20 | Hughes Aircraft Company | Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate |
DE4400985C1 (de) * | 1994-01-14 | 1995-05-11 | Siemens Ag | Verfahren zur Herstellung einer dreidimensionalen Schaltungsanordnung |
US5511428A (en) | 1994-06-10 | 1996-04-30 | Massachusetts Institute Of Technology | Backside contact of sensor microstructures |
DE4433846C2 (de) * | 1994-09-22 | 1999-06-02 | Fraunhofer Ges Forschung | Verfahren zur Herstellung einer vertikalen integrierten Schaltungsstruktur |
JP3177436B2 (ja) | 1996-03-21 | 2001-06-18 | 株式会社日立製作所 | 半導体集積回路装置 |
JP3056689B2 (ja) | 1996-07-09 | 2000-06-26 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
DE69737262T2 (de) | 1997-11-26 | 2007-11-08 | Stmicroelectronics S.R.L., Agrate Brianza | Herstellungsverfahren für einen Vorder-Hinterseiten-Durchkontakt in mikro-integrierten Schaltungen |
TW442873B (en) | 1999-01-14 | 2001-06-23 | United Microelectronics Corp | Three-dimension stack-type chip structure and its manufacturing method |
DE19904571C1 (de) | 1999-02-04 | 2000-04-20 | Siemens Ag | Verfahren zur Herstellung einer integrierten Schaltungsanordnung aus zwei Substraten, wobei die Schaltungsstrukturen des Substrate exakt gegeneinander ausgerichtet sind |
US6352923B1 (en) | 1999-03-01 | 2002-03-05 | United Microelectronics Corp. | Method of fabricating direct contact through hole type |
US6159833A (en) | 1999-09-08 | 2000-12-12 | United Microelectronics Corp. | Method of forming a contact hole in a semiconductor wafer |
JP2001116768A (ja) | 1999-10-20 | 2001-04-27 | Shin Etsu Polymer Co Ltd | 半導体ウェハーまたは半導体チップ用コンタクト |
US6483147B1 (en) | 1999-10-25 | 2002-11-19 | Advanced Micro Devices, Inc. | Through wafer backside contact to improve SOI heat dissipation |
US6818464B2 (en) | 2001-10-17 | 2004-11-16 | Hymite A/S | Double-sided etching technique for providing a semiconductor structure with through-holes, and a feed-through metalization process for sealing the through-holes |
DE10200399B4 (de) | 2002-01-08 | 2008-03-27 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung |
US6930040B2 (en) | 2003-10-22 | 2005-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a contact on a silicon-on-insulator wafer |
DE10351201B3 (de) * | 2003-11-03 | 2005-07-14 | Infineon Technologies Ag | Sensorvorrichtung mit Waferbondverbindungsaufbau und Herstellungsverfahren derselben |
US20050156330A1 (en) | 2004-01-21 | 2005-07-21 | Harris James M. | Through-wafer contact to bonding pad |
US7553695B2 (en) * | 2005-03-17 | 2009-06-30 | Hymite A/S | Method of fabricating a package for a micro component |
US7923840B2 (en) | 2007-01-10 | 2011-04-12 | International Business Machines Corporation | Electrically conductive path forming below barrier oxide layer and integrated circuit |
-
2008
- 2008-07-16 DE DE102008033395A patent/DE102008033395B3/de active Active
-
2009
- 2009-06-25 JP JP2011517083A patent/JP5497756B2/ja active Active
- 2009-06-25 WO PCT/EP2009/058001 patent/WO2010006916A1/de active Application Filing
- 2009-06-25 US US13/054,614 patent/US8658534B2/en active Active
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01128562A (ja) * | 1987-11-13 | 1989-05-22 | Nissan Motor Co Ltd | 半導体装置 |
JPH04304663A (ja) * | 1991-04-02 | 1992-10-28 | Nissan Motor Co Ltd | 半導体デバイス |
JPH07505982A (ja) * | 1993-01-19 | 1995-06-29 | ヒューズ・エアクラフト・カンパニー | 深い導電性フィードスルーの形成方法,および該方法に従って形成されたフィードスルーを含む配線層 |
JP2002508590A (ja) * | 1998-03-26 | 2002-03-19 | フラウンホッファー−ゲゼルシャフト ツァ フェルダールング デァ アンゲヴァンテン フォアシュンク エー.ファオ. | 垂直集積した回路構造を作製するための配線方法および垂直集積した回路構造 |
JP2004349513A (ja) * | 2003-05-22 | 2004-12-09 | Seiko Epson Corp | 薄膜回路装置及びその製造方法、並びに電気光学装置、電子機器 |
JP2005012180A (ja) * | 2003-05-28 | 2005-01-13 | Okutekku:Kk | 半導体装置およびその製造方法 |
JP2005116623A (ja) * | 2003-10-03 | 2005-04-28 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP2006128172A (ja) * | 2004-10-26 | 2006-05-18 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
WO2006131209A2 (de) * | 2005-06-07 | 2006-12-14 | Austriamicrosystems Ag | Photodiode mit integrierter halbleiterschaltung und verfahren zur herstellung |
JP2007242676A (ja) * | 2006-03-06 | 2007-09-20 | Sanyo Electric Co Ltd | 半導体装置製造方法 |
JP2007305960A (ja) * | 2006-04-14 | 2007-11-22 | Sharp Corp | 半導体装置およびその製造方法 |
JP2008085020A (ja) * | 2006-09-27 | 2008-04-10 | Nec Electronics Corp | 半導体装置 |
US20080157394A1 (en) * | 2006-12-29 | 2008-07-03 | Samsung Electronics Co., Ltd. | Semiconductor packages, stacked semiconductor packages, and methods of manufacturing the semiconductor packages and the stacked semiconductor packages |
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DE102008033395B3 (de) | 2010-02-04 |
JP5497756B2 (ja) | 2014-05-21 |
US20110260284A1 (en) | 2011-10-27 |
US8658534B2 (en) | 2014-02-25 |
WO2010006916A1 (de) | 2010-01-21 |
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