JP5377657B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5377657B2 JP5377657B2 JP2011532892A JP2011532892A JP5377657B2 JP 5377657 B2 JP5377657 B2 JP 5377657B2 JP 2011532892 A JP2011532892 A JP 2011532892A JP 2011532892 A JP2011532892 A JP 2011532892A JP 5377657 B2 JP5377657 B2 JP 5377657B2
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- substrate
- hole
- insulating layer
- semiconductor device
- etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/9202—Forming additional connectors after the connecting process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
Description
104、204…回路領域 106、206…トップメタル層
108、208…パッシベーション膜 110、210…穴
112、212、312…絶縁膜 114、214、314…バリア膜
116、218、318…貫通電極 216、316…貫通孔
400、500…絶縁層
Claims (8)
- 電極を有する第1の基板を用意する工程と、
貫通孔を有する第2の基板を用意する工程と、
前記第1の基板と前記第2の基板との間に絶縁層を介在させた状態で前記第1の基板上に前記第2の基板を積層する工程と、
前記第2の基板をマスクとして用いて前記絶縁層をエッチングして、前記貫通孔下の前記絶縁層に前記電極に達する開口を形成する工程と、
前記貫通孔及び前記開口を導電物で埋める工程と、
を備えたことを特徴とする半導体装置の製造方法。 - 前記貫通孔の内面には絶縁膜が形成されている
ことを特徴とする請求項1に記載の方法。 - 前記絶縁層をエッチングする際に用いるエッチャントに対して、前記絶縁層のエッチングレートは前記絶縁膜のエッチングレートよりも高い
ことを特徴とする請求項2に記載の方法。 - 前記絶縁膜上には導電性のバリア膜が形成されている
ことを特徴とする請求項2に記載の方法。 - 前記絶縁層をエッチングする際に用いるエッチャントに対して、前記絶縁層のエッチングレートは前記バリア膜のエッチングレートよりも高い
ことを特徴とする請求項4に記載の方法。 - 前記絶縁層の材料は、ベンゾシクロブテン、ポリイミド、シリコン酸化物及びシリコン窒化物から選択される
ことを特徴とする請求項1に記載の方法。 - 前記貫通孔を有する第2の基板を用意する工程は、前記貫通孔を形成するための予備的な穴にダミー材料を充填する工程と、前記予備的な穴に充填されたダミー材料を前記第2の基板の裏面側から露出させる工程と、前記ダミー材料を除去する工程と、を含む
ことを特徴とする請求項1に記載の方法。 - 前記貫通孔を有する第2の基板を用意する工程は、前記貫通孔を形成するための予備的な穴にダミー材料を充填する工程と、前記予備的な穴に充填されたダミー材料を前記第2の基板の裏面側から露出させる工程と、を含み、
前記第2の基板を積層した後に前記ダミー材料を除去する
ことを特徴とする請求項1に記載の方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2009/066831 WO2011036819A1 (ja) | 2009-09-28 | 2009-09-28 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
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JPWO2011036819A1 JPWO2011036819A1 (ja) | 2013-02-14 |
JP5377657B2 true JP5377657B2 (ja) | 2013-12-25 |
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Application Number | Title | Priority Date | Filing Date |
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JP2011532892A Active JP5377657B2 (ja) | 2009-09-28 | 2009-09-28 | 半導体装置の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8535977B2 (ja) |
JP (1) | JP5377657B2 (ja) |
WO (1) | WO2011036819A1 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013021001A (ja) * | 2011-07-07 | 2013-01-31 | Renesas Electronics Corp | 半導体装置及び半導体装置の製造方法 |
JP5981106B2 (ja) * | 2011-07-12 | 2016-08-31 | 東京エレクトロン株式会社 | プラズマエッチング方法 |
US20130154106A1 (en) * | 2011-12-14 | 2013-06-20 | Broadcom Corporation | Stacked Packaging Using Reconstituted Wafers |
JP5957926B2 (ja) * | 2012-02-09 | 2016-07-27 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
US9972534B1 (en) * | 2017-06-05 | 2018-05-15 | Vanguard International Semiconductor Corporation | Semiconductor devices, through-substrate via structures and methods for forming the same |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003197855A (ja) * | 2001-12-27 | 2003-07-11 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2004039667A (ja) * | 2002-06-28 | 2004-02-05 | Sekisui Chem Co Ltd | スルーホールが形成された半導体素子の製造方法、及び、半導体パッケージの製造方法 |
JP2006287211A (ja) * | 2005-03-08 | 2006-10-19 | Sharp Corp | 半導体装置、積層半導体装置およびそれらの製造方法 |
JP2009004722A (ja) * | 2007-06-20 | 2009-01-08 | Hynix Semiconductor Inc | 半導体パッケージの製造方法 |
JP2009004593A (ja) * | 2007-06-22 | 2009-01-08 | Panasonic Corp | 半導体積層構造体とそれを用いた半導体装置およびそれらの製造方法 |
JP2009141010A (ja) * | 2007-12-04 | 2009-06-25 | Hitachi Chem Co Ltd | 半導体装置及びその製造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005197339A (ja) | 2004-01-05 | 2005-07-21 | Seiko Epson Corp | 半導体装置の製造方法及び半導体装置 |
KR100919712B1 (ko) * | 2007-06-27 | 2009-10-06 | 삼성전자주식회사 | 반도체 집적 회로 장치 및 그 제조 방법 |
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2009
- 2009-09-28 WO PCT/JP2009/066831 patent/WO2011036819A1/ja active Application Filing
- 2009-09-28 JP JP2011532892A patent/JP5377657B2/ja active Active
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2012
- 2012-02-09 US US13/369,427 patent/US8535977B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003197855A (ja) * | 2001-12-27 | 2003-07-11 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2004039667A (ja) * | 2002-06-28 | 2004-02-05 | Sekisui Chem Co Ltd | スルーホールが形成された半導体素子の製造方法、及び、半導体パッケージの製造方法 |
JP2006287211A (ja) * | 2005-03-08 | 2006-10-19 | Sharp Corp | 半導体装置、積層半導体装置およびそれらの製造方法 |
JP2009004722A (ja) * | 2007-06-20 | 2009-01-08 | Hynix Semiconductor Inc | 半導体パッケージの製造方法 |
JP2009004593A (ja) * | 2007-06-22 | 2009-01-08 | Panasonic Corp | 半導体積層構造体とそれを用いた半導体装置およびそれらの製造方法 |
JP2009141010A (ja) * | 2007-12-04 | 2009-06-25 | Hitachi Chem Co Ltd | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JPWO2011036819A1 (ja) | 2013-02-14 |
US20120142145A1 (en) | 2012-06-07 |
US8535977B2 (en) | 2013-09-17 |
WO2011036819A1 (ja) | 2011-03-31 |
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