CN108666284A - 半导体装置的制造方法及半导体装置 - Google Patents

半导体装置的制造方法及半导体装置 Download PDF

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Publication number
CN108666284A
CN108666284A CN201710629300.XA CN201710629300A CN108666284A CN 108666284 A CN108666284 A CN 108666284A CN 201710629300 A CN201710629300 A CN 201710629300A CN 108666284 A CN108666284 A CN 108666284A
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China
Prior art keywords
face
semiconductor device
hole
semiconductor substrate
electrode
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CN201710629300.XA
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Inventor
野田有辉
久米平
久米一平
中村彦
中村一彦
佐藤兴
佐藤兴一
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Kioxia Corp
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Toshiba Memory Corp
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Publication of CN108666284A publication Critical patent/CN108666284A/zh
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Abstract

本发明的实施方式提供一种具有能抑制缺陷产生的TSV的半导体装置及半导体装置的制造方法。实施方式的半导体装置的制造方法包括如下步骤：在半导体衬底的与第1面呈相反侧的第2面上形成第1绝缘膜，所述半导体衬底在所述第1面形成有覆盖配线构造的绝缘层及贯通所述绝缘层的第1贯通电极；使用包含SF6、O2、SiF4、及CF4、Cl2、BCl3、CF3I、HBr的气体，从所述第2面侧对形成有所述第1绝缘膜的所述半导体衬底进行各向异性干式蚀刻，由此形成使所述器件层露出的贯通孔；及在所述贯通孔内形成第2贯通电极。

Description

半导体装置的制造方法及半导体装置
[相关申请]
本申请享有以日本专利申请2017-65619号(申请日：2017年3月29日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本实施方式涉及一种半导体装置的制造方法及半导体装置。
背景技术
半导体装置的制作方法中有使用波希工艺(Bosch process)形成贯通孔的方法。在使用波希工艺的情况下，加工速率(产能)与扇形弯曲量(贯通孔侧壁的平坦性)的关系是此消彼长的关系。因此，若提高加工速率则贯通孔侧壁的平坦性降低。
在贯通孔侧壁的平坦性降低的情况下，有难以在贯通孔内形成绝缘膜或形成晶种镀层的情况。虽然也有减小扇形弯曲来改善侧壁的平坦性的追加处理，但会导致步骤增加，从而产能降低。
发明内容
实施方式提供一种具有能抑制缺陷产生的TSV(Through-Substrate Via，贯穿衬底的通孔)的半导体装置及半导体装置的制造方法。
实施方式的半导体装置的制造方法包括如下步骤：在半导体衬底的与第1面呈相反侧的第2面上形成第1绝缘膜，所述半导体衬底在所述第1面形成有覆盖配线构造的绝缘层及贯通所述绝缘层的第1贯通电极；使用含有SF6、O2、SiF4、及包含CF4、Cl2、BCl3、CF3I、HBr中至少1种以上的气体的气体，从所述第2面侧对形成有所述第1绝缘膜的所述半导体衬底进行各向异性干式蚀刻，由此形成使所述器件层露出的贯通孔；及在所述贯通孔内形成第2贯通电极。
附图说明
图1是表示实施方式的半导体装置的概略构成例的剖视图。
图2～8是表示实施方式的半导体装置的制造方法的过程剖视图。
图9(a)～(d)是表示比较例的半导体装置的制造方法的过程剖视图。
图10(a)及(b)是将贯通孔侧壁的形状放大后的剖视图。
具体实施方式
(第1实施方式)
以下，参照附图对实施方式的半导体装置及半导体装置的制造方法进行详细说明。此外，本发明并非由该实施方式所限定。另外，在以下的说明中，将元件形成对象的半导体衬底的元件形成面设定为第1面，将与该第1面呈相反侧的面设定为第2面。
图1是表示实施方式的半导体装置的概略构成例的剖视图。如图1所示，半导体装置1具备半导体衬底10、绝缘层11、STI12、绝缘层13、第1贯通电极14、绝缘层17、第2贯通电极18、及接合材料(凸块)19。另外，在第2贯通电极18的侧壁上设置有保护膜10a。
半导体衬底10例如为硅衬底。该半导体衬底10可薄化至50μm(微米)以下例如30±5μm左右。
在半导体衬底10的第1面，具有形成半导体元件的工件区及将工件区之间电分离的STI(Shallow Trench Isolation，浅沟道隔离)12。在工件区，形成有存储单元阵列、晶体管、电阻元件、电容元件等半导体元件(未图示)。作为STI12，例如使用氧化硅膜等绝缘膜。在STI12上，设置有将半导体元件电连接于第2贯通电极18的第1贯通电极14及配线构造35。配线构造35设置于STI12上，且与设置于半导体衬底10的第1面上的半导体元件(例如，晶体管)电连接。半导体元件及配线构造35被绝缘层11、13覆盖。在半导体衬底10的第2面，设置有电连接于第2贯通电极18的接合材料19等。
绝缘层13是为了保护配线构造35而覆盖配线构造35。该绝缘层13中可包含覆盖配线构造35的钝化膜、及覆盖在钝化膜上的有机层。钝化膜可为氮化硅膜(SiN)、氧化硅膜(SiO2)、或氮氧化硅膜(SiON)的单层膜，或者也可为它们中两者以上的积层膜。作为有机层，可使用感光性聚酰亚胺等树脂材料。
第1贯通电极14与配线构造35接触。该第1贯通电极14可至少包含覆盖贯通孔内表面的障壁金属层141、障壁金属层141上的晶种金属层142、及晶种金属层142上的贯通电极143。障壁金属层141也可予以省略。在贯通电极143上，也可设置有在半导体装置1纵向集成化时发挥功能的材料膜144。
作为障壁金属层141，可使用钛(Ti)、钽(Ta)、钌(Ru)等。作为晶种金属层142，可使用铜(Cu)、或镍与铜的积层膜(Ni/Cu)等。作为贯通电极143，可使用镍(Ni)等。作为材料膜144，可使用金(Au)、锡(Sn)、铜(Cu)、锡-铜(SnCu)、锡-金(SnAu)、锡-银(SnAg)等。不过，第1贯通电极14的层构造及材料能视目的而适当变更。例如，障壁金属层141/晶种金属层142或材料膜144的层构造或材料可视贯通电极143中所用导电性材料或形成方法而适当变更。
第2贯通电极18通过与配线构造35接触，而将配线构造35电牵引至半导体衬底10的第2面上为止。在第2贯通电极的侧壁上设置有包含Si、O、及F、Cl、I、Br中至少1种以上元素的保护膜10a。
第2贯通电极18可至少包含覆盖贯通孔内表面的障壁金属层(第1金属层)181、障壁金属层181上的晶种金属层(第2金属层)182、及晶种金属层182上的贯通电极(第3金属层)183。它们各自所用的金属材料可与第1贯通电极14的障壁金属层141、晶种金属层142及贯通电极143相同。在贯通电极183的内部也可形成有空隙。另外，在贯通电极183上，也可设置有在将多个半导体装置1纵向(半导体衬底10的厚度方向)集成时用来将半导体装置1之间接合的接合材料19。作为该接合材料19，可使用锡(Sn)、铜(Cu)、锡-铜(SnCu)、锡-金(SnAu)、锡-银(SnAg)等焊料。
从形成于半导体衬底10的贯通孔内的内侧面到半导体衬底10的第2面，设置有用来防止第2贯通电极18与半导体衬底10短路的绝缘层17。绝缘层17例如包含氧化硅膜(SiO2)。此外，在本实施方式中，绝缘层17是氧化硅膜的单层膜，但也可是例如氧化硅膜与氮化硅膜的积层膜等。
接下来，以下参照附图对实施方式的半导体装置1的制造方法进行详细说明。图2～图8是表示实施方式的半导体装置的制造方法的过程剖视图。此外，在图2～图8中，使用与图1相同的剖面进行说明。不过，在图2中，为了便于说明，剖面的上下关系与图1及图3～图8中的上下关系相反。
首先，如图2所示，在半导体衬底10的第1面上形成STI12，而确定工件区。半导体衬底10例如为硅衬底。STI12例如为氧化硅膜。其次，在工件区形成半导体元件(未图示)。半导体元件例如可为存储单元阵列、晶体管、电阻元件、电容元件等。形成半导体元件时，在STI12上例如形成配线构造35。半导体元件及配线构造35被绝缘层11、13覆盖。此外，绝缘层13中可包含覆盖配线构造35的钝化膜、及覆盖在钝化膜上的有机层。作为有机层，使用感光性聚酰亚胺等，对该有机层转印用来形成第1贯通电极14的开口图案。开口图案的开口径例如可为10μm左右。
接着，例如将有机层作为掩模，对绝缘层13的钝化膜及绝缘层11进行蚀刻，由此使配线构造35露出。在钝化膜及绝缘层11的蚀刻中，可使用反应性离子蚀刻(RIE)等。接下来，在包含贯通孔内部的整个绝缘层13上依次积层使用钛(Ti)的障壁金属层及使用铜(Cu)的晶种金属层。在障壁金属层及晶种金属层的成膜中，分别可使用溅镀法或化学气相成长(CVD)法等。晶种金属层的膜厚例如可为500nm左右。
接着，例如使用PEP(Photo Engraving Process，光刻工艺)技术形成用来在晶种金属层上形成贯通电极143的掩模。在该掩模的与形成于绝缘层13的贯通孔对应的位置形成有开口。接下来，在从掩模的开口露出的晶种金属层上形成使用镍(Ni)的贯通电极143。在贯通电极143的形成中，可使用共形涂覆法等。
接着，将掩模去除后，将露出的晶种金属层及障壁金属层去除。由此，贯通电极143下的晶种金属层142及障壁金属层141得以图案化。此外，在晶种金属层142及障壁金属层141的图案化中，可使用湿式蚀刻。
接着，在所形成的贯通电极143的上表面上，形成使用金(Au)的材料膜144。在材料膜144的形成中，可使用剥离法等形成方法。结果，如图2所示，在半导体衬底10的元件形成面(第1面)侧，形成将配线构造35牵引至绝缘层13上为止的第1贯通电极14。
接着，如图3所示，在形成有第1贯通电极14的绝缘层13上涂布黏接剂，并使支撑衬底16贴合于该黏接剂，由此如图3所示，将支撑衬底16黏接于半导体装置1的元件形成面侧。接下来，在将支撑衬底16固定于平台的状态下，从与元件形成面(第1面)呈相反侧的第2面对半导体衬底10进行研磨，由此将半导体衬底10薄化至例如30±5μm左右。
接着，如图4所示，在半导体衬底10上涂布感光性光阻剂180M，并对该光阻剂180M转印用来形成第2贯通电极18的开口图案。此外，开口图案的开口径例如可为10μm左右。接下来，将转印有开口图案的光阻剂180M作为掩模，从第2面侧刻蚀半导体衬底10，由此形成到达配线构造35为止的贯通孔(TSV)180H。这时，在半导体衬底10的刻蚀中，使用能获得较高纵横比的各向异性等离子体蚀刻。等离子体蚀刻是使用RIE(Reactive Ion Etching，反应性例子离子蚀刻法)的各向异性蚀刻。各向异性等离子体蚀刻时，例如使用包含SF6、O2、SiF4、CF4、Cl2、BCl3、CF3I及HBr但不含CHx的混合气体。在混合气体中，O2、SiF4、CF4、Cl2、BCl3、CF3I及HBr具有形成保护膜10a的功能。另外，SF6气体及SiF4气体的F离子具有蚀刻功能。蚀刻时，混合气体是使用等离子体，电离成自由基或离子。进而，在衬底的深度方向施加偏压而将电离所得的自由基或离子撷取至贯通孔180H内。由此，提高了蚀刻的各向异性。在本混合气体中，包含SiF4、O2、及CF4、Cl2、BCl3、CF3I、HBr中至少1种以上的气体。由此，能在贯通孔180H的侧壁形成包含Si、O、及F、Cl、I、Br中至少1种以上元素的保护膜10a。通过形成保护膜10a，能抑制在贯通孔内沿着水平方向进行蚀刻的情况。通过抑制沿着水平方向进行蚀刻的情况，能提高半导体衬底10的深度方向的各向异性蚀刻的效果。
接着，如图5所示，在包含贯通孔(TSV)180H内部的半导体衬底10的整个第2面上成膜绝缘层17。在绝缘层17的成膜中，例如可使用CVD法等。
接着，通过回蚀STI12，而将形成于贯通孔(TSV)180H底部的STI12去除。该回蚀一直进行到STI12被去除而配线构造35露出为止。结果，如图6所示，在半导体衬底10的第2面上形成绝缘层17，贯通孔(TSV)180H的内侧面被绝缘层17覆盖，并且配线构造35露出于贯通孔(TSV)180H的底部。
接着，如图7所示，在包含贯通孔内部的整个绝缘层17上依次积层使用钛(Ti)的障壁金属层181A及使用铜(Cu)的晶种金属层182A。障壁金属层181A及晶种金属层182A有时简称为金属层。晶种金属层182A的膜厚可比晶种金属层142A厚。
接着，例如使用PEP技术形成用来在晶种金属层182A上形成贯通电极183的掩模183M。在该掩模183M的与形成于半导体衬底10的贯通孔(TSV)180H对应的位置形成有开口。接下来，如图8所示，在从掩模183M的开口露出的晶种金属层182A上形成镍(Ni)的贯通电极183。在贯通电极183的形成中，可使用共形涂覆等。
接着，将掩模183M去除后，将露出的晶种金属层182A及障壁金属层181A去除。在晶种金属层182A及障壁金属层181A的去除中，可使用湿式蚀刻。
接着，将接合材料19附着于从绝缘层17突出的贯通电极183的上表面上。在接合材料19的形成中，可使用电镀法或无电镀法等。通过经历以上步骤，于半导体衬底10的第2面侧形成将配线构造35牵引至绝缘层17上为止的第2贯通电极18，而制造具备图1所示的剖面构造的半导体装置1。
此处，对比较例的半导体装置的制造方法进行说明。
在比较例的半导体装置的制造方法中，使用波希法进行蚀刻。图10是表示比较例的半导体装置的制造方法的图。如图9(a)所示，使用以CF6为主成分的气体进行各向同性蚀刻，而刻蚀半导体衬底20。在半导体衬底上设置有绝缘膜21。其次，如图9(b)所示，使用C4F8气体在衬底20及绝缘膜21上形成保护膜22。其次，如图9(c)所示，与图9(a)同样地，使用以SF6为主成分的气体进行各向同性蚀刻，而刻蚀半导体衬底20。在此之后，利用与图9(b)及图9(c)相同的方法，反复进行半导体衬底的刻蚀及保护膜的形成。
图10是刻蚀半导体衬底10、20时的半导体衬底10的侧壁的放大图。图10(a)是表示本实施方式的半导体衬底10的侧壁的图。图10(b)是表示比较例的半导体衬底20的侧壁的图。如图10(a)及(b)所示，通过蚀刻来刻蚀半导体衬底10、20时，半导体衬底的水平方向也被蚀刻，因此形成凹凸(扇形弯曲)。但如图10(a)所示，通过进行各向异性较高的蚀刻，能将沿着水平方向刻蚀出的凹部的深度(r)抑制于贯通孔侧面的相邻凸部间的距离(5r)的1/5以下。此处，所谓相邻凸部间的距离是指例如相邻凸部的最高位置之间的距离。另外，凹部的深度与凸部的高度对应。另一方面，如图10(b)所示，在比较例的半导体装置的制造方法中，因为是通过各向同性蚀刻来刻蚀半导体衬底20，所以在水平方向也以与在深度方向进行刻蚀的深度实质上相同的深度受到蚀刻。因此，沿着水平方向刻蚀出的凹部的深度(r)与相邻凸部间的距离(2r)的比成为1/2。比较例的半导体衬底20相比于实施方式的半导体衬底来讲，贯通孔侧壁的平坦性较低。该情况下，在贯通孔内形成金属部时恐怕会产生未嵌入金属的区域(缺陷)。未嵌入金属的区域(缺陷)将成为器件不良的原因。
根据本实施方式的半导体装置的制造方法，通过使用包含SF6、O2、SiF4、及CF4、Cl2、BCl3、CF3I、HBr中至少1种以上的气体的混合气体进行蚀刻，而刻蚀半导体衬底10。由此，能提高蚀刻的各向异性。通过提高蚀刻的各向异性，能减少扇形弯曲(凹凸)。另外，本实施方式的半导体制造方法无需如比较例般，反复实施刻蚀半导体衬底时的蚀刻步骤及保护膜形成步骤。另外，也能防止如比较例的半导体制造方法般贯通孔侧壁的平坦性降低的情况。
对本发明的实施方式进行了说明，但该实施方式是作为例子而提出的，并非想要限定发明的范围。该新颖的实施方式能以其他各种方式加以实施，且能在不脱离发明主旨的范围内进行各种省略、替换、变更。该实施方式及其变形包含在发明的范围及主旨中，并且包含在权利要求书所记载的发明及其均等的范围内。
[符号的说明]
1 半导体装置
10 半导体衬底
11 绝缘层
12 STI
13 绝缘层
14 第2贯通电极
15 黏接剂
16 支撑衬底
17 绝缘层
18 第1贯通电极
19 接合材料
181 障壁金属层
182 晶种金属层
183 贯通电极

Claims (5)

1.一种半导体装置的制造方法，其特征在于包括如下步骤：
在半导体衬底的与第1面呈相反侧的第2面上形成第1绝缘膜，所述半导体衬底在所述第1面形成有覆盖配线构造的绝缘层及贯通所述绝缘层的第1贯通电极；
使用包含SF6、O2、SiF4、及CF4、Cl2、BCl3、CF3I与HBr中任1种以上的气体的气体，从所述第2面侧对形成有所述第1绝缘膜的所述半导体衬底进行各向异性干式蚀刻，由此形成使所述配线构造露出的贯通孔；及
在所述贯通孔内形成第2贯通电极。
2.根据权利要求1所述的半导体装置的制造方法，其特征在于：
所述贯通孔在侧壁具有多个凸部，且相邻所述凸部间的距离与所述凸部的高度的比为1/5以下。
3.根据权利要求1或2所述的半导体装置的制造方法，其特征在于：
所述各向异性干式蚀刻时，在所述贯通孔的侧壁上形成包含Si、O、及F、Cl、I、Br中至少1种以上元素的保护膜。
4.一种半导体装置，其特征在于包含：
半导体衬底；
器件层，位于所述半导体衬底的第1面，且包含配线；及
贯通电极，从所述第1面贯通至所述第1面的相反面的第2面，且形成于贯通孔内，所述贯通孔在侧壁具有相邻凸部间的距离与所述凸部的高度的比为1/5以下的多个凸部。
5.根据权利要求4所述的半导体装置，其特征在于：
在所述贯通孔的侧壁具有包含Si、O、及F、Cl、I、Br中至少1种以上元素的保护膜。
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