JP2018170363A - 半導体装置の製造方法及び半導体装置 - Google Patents

半導体装置の製造方法及び半導体装置 Download PDF

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Publication number
JP2018170363A
JP2018170363A JP2017065619A JP2017065619A JP2018170363A JP 2018170363 A JP2018170363 A JP 2018170363A JP 2017065619 A JP2017065619 A JP 2017065619A JP 2017065619 A JP2017065619 A JP 2017065619A JP 2018170363 A JP2018170363 A JP 2018170363A
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Prior art keywords
semiconductor device
semiconductor substrate
electrode
hole
manufacturing
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JP2017065619A
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Inventor
有輝 野田
Yuki Noda
有輝 野田
一平 久米
Ippei Kume
一平 久米
中村　一彦
Kazuhiko Nakamura
一彦 中村
佐藤　興一
Koichi Sato
興一 佐藤
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Kioxia Corp
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Toshiba Memory Corp
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Priority to JP2017065619A priority Critical patent/JP2018170363A/ja
Priority to TW106124852A priority patent/TWI684242B/zh
Priority to CN201710629300.XA priority patent/CN108666284A/zh
Priority to US15/694,978 priority patent/US10297531B2/en
Publication of JP2018170363A publication Critical patent/JP2018170363A/ja
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L24/11—Manufacturing methods

Abstract

【課題】欠陥の発生を抑制することが可能なＴＳＶを有する半導体装置及び半導体装置の製造方法を提供する。
【解決手段】実施形態にかかる半導体装置の製造方法は、第１面に配線構造を覆う絶縁層と前記絶縁層を貫通する第１貫通電極とが形成された半導体基板における前記第１面とは反対側の第２面上に、第１絶縁膜を形成する工程と、前記第１絶縁膜が形成された前記半導体基板を前記第２面側から、ＳＦ６、Ｏ２、ＳｉＦ４、及びＣＦ４、Ｃｌ２、ＢＣｌ３、ＣＦ３Ｉ及びＨＢｒを含むガスを用いて異方性ドライエッチングすることで前記デバイス層を露出させる貫通孔を形成する工程と、前記貫通孔内に第２貫通電極を形成する工程と、を有する。
【選択図】図１

Description

本実施形態は、半導体装置の製造方法及び半導体装置に関する。
半導体装置の作製方法においてBoschプロセスを用いて貫通孔を形成する方法がある。Boschプロセスを用いた場合、加工レート(スループット)とスキャロップ量（貫通孔の側壁の平坦性）との関係はトレードオフ関係にある。このため、加工レートを上げると貫通孔の側壁の平坦性は低下する。
貫通孔の側壁の平坦性は低下した場合、貫通孔内に絶縁膜の形成やめっきシード層の形成が困難となる場合がある。スキャロップを減らし側壁の平坦性を改善する追加処理もあるが、工程が増えることになり、スループットが低下する。
特開２０１４−１５２９６７号公報
実施形態は、欠陥の発生を抑制することが可能なＴＳＶを有する半導体装置及び半導体装置の製造方法を提供することを目的とする。
実施形態によれば、半導体装置の製造方法は、第１面に配線構造を覆う絶縁層と前記絶縁層を貫通する第１貫通電極とが形成された半導体基板における前記第１面とは反対側の第２面上に、第１絶縁膜を形成する工程と、前記第１絶縁膜が形成された前記半導体基板を前記第２面側から、ＳＦ６と、Ｏ２と、ＳｉＦ４と、ＣＦ４、Ｃｌ２、ＢＣｌ３、ＣＦ３Ｉ及びＨＢｒの少なくとも１種以上を含むガスとを含むガスを用いて異方性ドライエッチングすることで前記デバイス層を露出させる貫通孔を形成する工程と、前記貫通孔内に第２貫通電極を形成する工程と、を有する。
図１は、実施形態にかかる半導体装置の概略構成例を示す断面図である。 図２は、実施形態にかかる半導体装置の製造方法を示すプロセス断面図である。 図３は、実施形態にかかる半導体装置の製造方法を示すプロセス断面図である。 図４は、実施形態にかかる半導体装置の製造方法を示すプロセス断面図である。 図５は、実施形態にかかる半導体装置の製造方法を示すプロセス断面図である。 図６は、実施形態にかかる半導体装置の製造方法を示すプロセス断面図である。 図７は、実施形態にかかる半導体装置の製造方法を示すプロセス断面図である。 図８は、実施形態にかかる半導体装置の製造方法を示すプロセス断面図である。 図９は、比較例にかかる半導体装置の製造方法を示すプロセス断面図である。 図１０は、貫通孔の側壁の形状を拡大した断面図である。
（第１実施形態)
以下に添付図面を参照して、実施形態にかかる半導体装置および半導体装置の製造方法を詳細に説明する。なお、この実施形態により本発明が限定されるものではない。また、以下の説明では、素子形成対象の半導体基板における素子形成面を第１面とし、この第１面と反対側の面を第２面としている。
図１は、実施形態にかかる半導体装置の概略構成例を示す断面図である。図１に示すように、半導体装置１は、半導体基板１０と、絶縁層１１と、ＳＴＩ１２と、絶縁層１３と、第１貫通電極１４と、絶縁層１７と、第２貫通電極１８と、接合材（バンプ）１９とを備えている。また、第２貫通電極１８の側壁上には、保護膜１０ａを設けられる。
半導体基板１０は、たとえばシリコン基板である。この半導体基板１０は、５０μｍ（マイクロメートル）以下、たとえば３０±５μｍ程度まで薄厚化されていてもよい。
半導体基板１０の第１面には、半導体素子を形成するアクティブエリアとアクティブエリア間を電気的に分離するＳＴＩ（Shallow Trench Isolation）１２とを有する。アクティブエリアには、メモリセルアレイ、トランジスタ、抵抗素子、キャパシタ素子等の半導体素子（図示せず）が形成されている。ＳＴＩ１２には、例えば、シリコン酸化膜等の絶縁膜が用いられている。ＳＴＩ上１２には、半導体素子を第２貫通電極１８に電気的に接続する第１貫通電極１４や配線構造３５が設けられている。配線構造３５は、ＳＴＩ１２上に設けられており、半導体基板１０の第１面上に設けられた半導体素子（例えば、トランジスタ）に電気的に接続されている。半導体素子および配線構造３５は、絶縁層１１、１３によって被覆される。半導体基板１０の第２面には、第２貫通電極１８に電気的に接続される接合材１９等が設けられている。
絶縁層１３は、配線構造３５を保護する目的で、配線構造３５を覆っている。この絶縁層１３には、配線構造３５をカバーするパッシベーションと、パッシベーション上を覆う有機層とが含まれてもよい。パッシベーションは、シリコン窒化膜（ＳｉＮ）、シリコン酸化膜（ＳｉＯ２）または酸化窒化シリコン膜（ＳｉＯＮ）の単層膜、もしくは、それらのうち２つ以上の積層膜であってよい。有機層には、感光性ポリイミドなどの樹脂材料が用いられてもよい。
第１貫通電極１４は、配線構造３５と接触している。この第１貫通電極１４は、少なくとも貫通孔内表面を覆うバリアメタル層１４１と、バリアメタル層１４１上のシードメタル層１４２と、シードメタル層１４２上の貫通電極１４３とを含んでもよい。バリアメタル層１４１は省略されてもよい。貫通電極１４３上には、半導体装置１の縦方向への集積化の際に機能する材料膜１４４が設けられていてもよい。
バリアメタル層１４１には、チタン（Ｔｉ）、タンタル（Ｔａ）、ルテニウム（Ｒｕ）などが用いられてもよい。シードメタル層１４２には、銅（Ｃｕ）やニッケルと銅との積層膜（Ｎｉ／Ｃｕ）などが用いられてもよい。貫通電極１４３には、ニッケル（Ｎｉ）などが用いられてもよい。材料膜１４４には、金（Ａｕ）、錫（Ｓｎ）、銅（Ｃｕ）、錫−銅（ＳｎＣｕ）、錫−金（ＳｎＡｕ）、錫−銀（ＳｎＡｇ）などが用いられてもよい。ただし、第１貫通電極１４の層構造および材料は、目的に応じて適宜変更可能である。たとえば貫通電極１４３に用いる導電性材料や形成方法に応じてバリアメタル層１４１／シードメタル層１４２または材料膜１４４の層構造や材料が適宜変更されてよい。
第２貫通電極１８は、配線構造３５と接触することで、配線構造３５を半導体基板１０の第２面上まで電気的に引き出している。第２貫通電極の側壁上にはＳｉ、Ｏ、及び、Ｆ、Ｃｉ、Ｉ、Ｂｒのうち少なくとも１種以上の元素を含む保護膜１０ａが設けられる。
第２貫通電極１８は、少なくとも貫通孔内表面を覆うバリアメタル層（第１メタル層）１８１と、バリアメタル層１８１上のシードメタル層（第２メタル層）１８２と、シードメタル層１８２上の貫通電極（第３メタル層）１８３とを含んでもよい。それぞれに用いられる金属材料は、第１貫通電極１４のバリアメタル層１４１、シードメタル層１４２および貫通電極１４３と同様であってよい。貫通電極１８３の内部には、空隙が形成されていてもよい。また、貫通電極１８３上には、複数の半導体装置１を縦方向（半導体基板１０の厚さ方向）へ集積する際に半導体装置１間を接合するための接合材１９が設けられてもよい。この接合材１９には、錫（Ｓｎ）、銅（Ｃｕ）、錫−銅（ＳｎＣｕ）、錫−金（ＳｎＡｕ）、錫−銀（ＳｎＡｇ）などのはんだが用いられてもよい。
半導体基板１０に形成された貫通孔内の内側面から半導体基板１０の第２面には、第２貫通電極１８と半導体基板１０との短絡を防止するための絶縁層１７が設けられている。絶縁層１７は、例えばシリコン酸化膜（ＳｉＯ２）を含む。なお、本実施形態では、絶縁層１７はシリコン酸化膜の単層膜であるが、例えば、シリコン酸化膜とシリコン窒化膜の積層膜等でもよい。
つづいて、実施形態にかかる半導体装置１の製造方法について、以下に図面を参照して詳細に説明する。図２〜図８は、実施形態にかかる半導体装置の製造方法を示すプロセス断面図である。なお、図２〜図８では、図１と同様の断面を用いて説明する。ただし、図２では、説明の都合上、断面の上下関係が図１および図３〜図８までの上下関係とは反転している。
まず、図２に示すように、半導体基板１０の第１面上にＳＴＩ１２を形成し、アクティブエリアを決める。半導体基板１０は、例えば、シリコン基板である。ＳＴＩ１２は、例えば、シリコン酸化膜である。次に、アクティブエリアに半導体素子（図示せず）を形成する。半導体素子は、例えば、メモリセルアレイ、トランジスタ、抵抗素子、キャパシタ素子等でよい。半導体素子の形成の際に、ＳＴＩ１２上には、例えば、配線構造３５が形成される。半導体素子および配線構造３５は、絶縁層１１、１３によって被覆される。なお、絶縁層１３には、配線構造３５をカバーするパッシベーションと、パッシベーション上を覆う有機層とが含まれてもよい。有機層には、感光性ポリイミドなどが用いられ、この有機層に第１貫通電極１４を形成するための開口パターンが転写される。開口パターンの開口径は、たとえば１０μｍ程度であってもよい。
つぎに、たとえば有機層をマスクとして絶縁層１３のパッシベーションおよび絶縁層１１をエッチングすることで、配線構造３５を露出させる。パッシベーションおよび絶縁層１１のエッチングには、反応性イオンエッチング（ＲＩＥ）などが用いられてよい。つづいて、貫通孔内部を含む絶縁層１３上全体にチタン（Ｔｉ）を用いたバリアメタル層と銅（Ｃｕ）を用いたシードメタル層とを順次積層する。バリアメタル層とシードメタル層との成膜には、それぞれスパッタリング法や化学気相成長（ＣＶＤ）法などが用いられてもよい。シードメタル層の膜厚はたとえば５００ｎｍ程度であってよい。
つぎに、シードメタル層上に貫通電極１４３を形成するためのマスクをたとえばＰＥＰ（Photo Engraving Process）技術を用いて形成する。このマスクの絶縁層１３に形成された貫通孔に対応する位置には、開口が形成されている。つづいて、マスクの開口から露出するシードメタル層上にニッケル（Ｎｉ）を用いた貫通電極１４３を形成する。貫通電極１４３の形成にはコンフォーマルめっきなどが用いられてもよい。
つぎに、マスクを除去した後、露出したシードメタル層とバリアメタル層とが除去される。これにより、貫通電極１４３下のシードメタル層１４２とバリアメタル層１４１とがパターニングされる。なお、シードメタル層１４２とバリアメタル層１４１とのパターニングには、ウエットエッチングが用いられてよい。
つぎに、形成された貫通電極１４３の上面上に、金（Ａｕ）を用いた材料膜１４４を形成する。材料膜１４４の形成には、リフトオフなどの形成方法が用いられてもよい。その結果、図２に示すように、半導体基板１０の素子形成面（第１面）側に、配線構造３５を絶縁層１３上まで引き出す第１貫通電極１４が形成される。
つぎに、図３に示すように、第１貫通電極１４が形成された絶縁層１３上に接着剤を塗布し、この接着剤に支持基板１６を貼り合わせることで、図３に示すように、半導体装置１の素子形成面側に支持基板１６を接着する。つづいて、支持基板１６をステージに固定した状態で半導体基板１０を素子形成面（第１面）とは反対側の第２面からグラインドすることで、半導体基板１０をたとえば３０±５μｍ程度に薄厚化する。
つぎに、図４に示すように、半導体基板１０上に感光性フォトレジスト１８０Ｍを塗布し、このフォトレジスト１８０Ｍに第２貫通電極１８を形成するための開口パターンを転写する。なお、開口パターンの開口径は、たとえば１０μｍ程度であってもよい。つづいて、開口パターンが転写されたフォトレジスト１８０Ｍをマスクとして半導体基板１０を第２面側から彫り込むことで、配線構造３５まで達する貫通孔（ＴＳＶ）１８０Ｈを形成する。このとき半導体基板１０の彫り込みには、高いアスペクト比が得られる異方性プラズマエッチングを用いる。プラズマエッチングは、ＲＩＥ（Reactive Ion Etching）を用いた異方性エッチングである。異方性プラズマエッチングの際、例えば、ＳＦ６、Ｏ２、ＳｉＦ４、ＣＦ４、Ｃｌ２、ＢＣｌ３、ＣＦ３Ｉ及びＨＢｒを含み、ＣＨｘを含まない混合ガスである。混合ガスにおいて、Ｏ２、ＳｉＦ４、ＣＦ４、Ｃｌ２、ＢＣｌ３、ＣＦ３Ｉ及びＨＢｒは保護膜１０ａを形成する機能を有する。また、ＳＦ６ガス及びＳｉＦ４ガスのＦイオンはエッチングする機能を有する。エッチングの際、混合ガスはプラズマを用いて、ラジカルやイオンに電離させる。さらに、基板の深さ方向にバイアスを印加させて電離させたラジカルやイオンを貫通孔１８０Ｈ内に引き込む。これにより、エッチングの異方性を高めている。本混合ガスにおいて、ＳｉＦ４と、Ｏ２と、ＣＦ４、Ｃｌ２、ＢＣｌ３、ＣＦ３Ｉ及びＨＢｒのうち少なくとも１種以上のガスとを含んでいる。これにより、貫通孔１８０Ｈの側壁にＳｉ、Ｏ、及び、Ｆ、Ｃｌ、Ｉ、Ｂｒのうち少なくとも１種以上の元素を含む保護膜１０ａを形成することができる。保護膜１０ａを形成することにより、貫通孔内において水平方向にエッチングすることを抑制できる。水平方向にエッチングすることを抑制することにより、半導体基板１０の深さ方向の異方性エッチングの効果を高めることができる。
つぎに、図５に示すように、貫通孔（ＴＳＶ）１８０Ｈの内部を含む半導体基板１０の第２面上全体に絶縁層１７を成膜する。絶縁層１７の成膜には、例えば、ＣＶＤ法などが用いられる。
つぎに、ＳＴＩ１２をエッチバックすることで、貫通孔（ＴＳＶ）１８０Ｈの底部に形成されたＳＴＩ１２を除去する。このエッチバックは、ＳＴＩ１２が除去されて配線構造３５が露出されるまで行われる。その結果、図６に示すように、半導体基板１０の第２面上に絶縁層１７が形成され、貫通孔（ＴＳＶ）１８０Ｈの内側面が絶縁層１７により覆われるとともに、貫通孔（ＴＳＶ）１８０Ｈの底部に配線構造３５が露出される。
つぎに、図７に示すように、貫通孔内部を含む絶縁層１７上全体にチタン（Ｔｉ）を用いたバリアメタル層１８１Ａと銅（Ｃｕ）を用いたシードメタル層１８２Ａとを順次積層する。バリアメタル層１８１Ａおよびシードメタル層１８２Ａは、単にメタル層と称される場合がある。シードメタル層１８２Ａの膜厚は、シードメタル層１４２Ａより厚くてもよい。
つぎに、シードメタル層１８２Ａ上に貫通電極１８３を形成するためのマスク１８３Ｍを、たとえばＰＥＰ技術を用いて形成する。このマスク１８３Ｍの半導体基板１０に形成された貫通孔（ＴＳＶ）１８０Ｈに対応する位置には、開口が形成されている。つづいて、図８に示すように、マスク１８３Ｍの開口から露出するシードメタル層１８２Ａ上にニッケル（Ｎｉ）の貫通電極１８３を形成する。貫通電極１８３の形成には、コンフォーマルめっきなどが用いられてもよい。
つぎに、マスク１８３Ｍを除去した後、露出したシードメタル層１８２Ａとバリアメタル層１８１Ａとが除去される。シードメタル層１８２Ａとバリアメタル層１８１Ａとの除去には、ウエットエッチングが用いられてよい。
つぎに、絶縁層１７から突出する貫通電極１８３の上面上に、接合材１９を付着する。接合材１９の形成には、電解めっき法や無電解めっき法などが用いられてもよい。以上の工程を経ることで、半導体基板１０の第２面側に配線構造３５を絶縁層１７上まで引き出す第２貫通電極１８が形成され、図１に示す断面構造を備えた半導体装置１が製造される。
ここで、比較例における半導体装置の製造方法について説明する。
比較例における半導体装置の製造方法では、Bosch法によるエッチングを行う。図１０は比較例における半導体装置の製造方法を示す図である。図９（ａ）に示すように、ＣＦ６を主成分とするガスを用いて等方性エッチングを行い、半導体基板２０を掘り込む。半導体基板上には絶縁膜２１が設けられている。次に、図９（ｂ）に示すように、Ｃ４Ｆ８ガスを用いて基板２０及び絶縁膜２１上に保護膜２２を形成する。次に、図９（ｃ）に示すように、図９（ａ）と同様に、ＳＦ６を主成分とするガスを用いて等方性エッチングを行い、半導体基板２０を掘り込む。以降、図９（ｂ）及び図９（ｃ）と同様の手法で、半導体基板の掘り込みと保護膜の形成を繰り返し行う。
図１０は半導体基板１０、２０を掘り込んだ際の半導体基板１０の側壁の拡大図である。図１０（ａ）は、本実施形態の半導体基板１０の側壁を示す図である。図１０(ｂ）は、比較例における半導体基板２０の側壁を示す図である。図１０（ａ）及び（ｂ）に示すように、エッチングにより半導体基板１０、２０を掘り込んだ際、半導体基板の水平方向もエッチングされるため、凹凸（スキャロップ）が形成される。しかし、図１０（ａ）に示すように、異方性の高いエッチングを行うことにより、貫通孔の側面において、隣り合う凸部間距離（５ｒ）に対し、水平方向に掘り込まれた凹部の深さ（ｒ）を１／５以下に抑えることができる。ここで、隣り合う凸部間の距離とは、例えば、隣り合う凸部の最も高い位置の間の距離をいう。また、凹部の深さは、凸部の高さに対応するものとする。一方、図１０（ｂ）に示すように、比較例の半導体装置の製造方法において、等方性エッチングにより半導体基板２０を掘り込むため、水平方向にも深さ方向に掘り込む深さと実質的に同じ深さにエッチングされる。このため、隣り合う凸部間距離（２ｒ）に対し、水平方向に掘り込まれた凹部の深さ（ｒ）の比は１／２となる。比較例における半導体基板２０は、実施形態の半導体基板と比較すると、貫通孔の側壁の平坦性が低い。この場合、貫通孔内に金属部を形成した際、金属が埋め込まれていない領域（欠陥）が生じるおそれがある。金属が埋め込まれていない領域（欠陥）はデバイス不良の原因となる。
本実施形態の半導体装置の製造方法によれば、ＳＦ６と、Ｏ２と、ＳｉＦ４と、ＣＦ４、Ｃｌ２、ＢＣｌ３、ＣＦ３Ｉ及びＨＢｒのうち少なくとも１種以上のガスとを含む混合ガスを用いたエッチングにより、半導体基板１０を掘り込む。これにより、エッチングの異方性を高めることができる。エッチングの異方性を高めることにより、スキャロップ（凹凸）を低減できる。また、本実施形態の半導体製造方法は、比較例のように、半導体基板を掘り込む際にエッチングする工程と保護膜の形成する工程とを繰り返す必要もない。また、比較例の半導体製造方法のような、貫通孔の側壁の平坦性が低くなることを防ぐこともできる。
本発明の実施形態を説明したが、この実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。この新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。この実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。
１…半導体装置、１０…半導体基板、１１…絶縁層、１２…ＳＴＩ、１３…絶縁層、１４…第２貫通電極、１５…接着剤、１６…支持基板、１７…絶縁層、１８…第１貫通電極、１９…接合材、１８１…バリアメタル層、１８２…シードメタル層、１８３…貫通電極

Claims (5)

  1. 第１面に配線構造を覆う絶縁層と前記絶縁層を貫通する第１貫通電極とが形成された半導体基板における前記第１面とは反対側の第２面上に、第１絶縁膜を形成する工程と、
    前記第１絶縁膜が形成された前記半導体基板を前記第２面側から、ＳＦ６と、Ｏ２と、ＳｉＦ４と、ＣＦ４、Ｃｌ２、ＢＣｌ３、ＣＦ３Ｉ及びＨＢｒのいずれか１種以上のガスとを含むガスを用いて異方性ドライエッチングすることで前記配線構造を露出させる貫通孔を形成する工程と、
    前記貫通孔内に第２貫通電極を形成する工程と、
    を有する半導体装置の製造方法。
  2. 前記貫通孔は、側壁に複数の凸部を有し、隣り合う前記凸部間の距離と前記凸部の高さの比１／５以下である請求項１に記載の半導体装置の製造方法。
  3. 前記異方性ドライエッチングの際、前記貫通孔の側壁上にＳｉと、Ｏと、Ｆ、Ｃｌ、Ｉ及びＢｒのうち少なくとも１種以上の元素とを含む保護膜を形成する請求項１または２に記載の半導体装置の製造方法。
  4. 半導体基板と、
    前記半導体基板の第１面に位置し、配線を含むデバイス層と、
    前記第１面から前記第１面の反対面の第２面まで貫通し、側壁に隣り合う凸部間の距離と前記凸部の高さの比１／５以下である複数の凸部を有する前記貫通孔内に形成された貫通電極と、
    を有する半導体装置。
  5. 前記貫通孔の側壁にＳｉと、ＯとＦ、Ｃｌ、Ｉ及びＢｒのうち少なくとも１種以上の元素とを含む保護膜を有する請求項４に記載の半導体装置。
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