JP5917321B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP5917321B2 JP5917321B2 JP2012156561A JP2012156561A JP5917321B2 JP 5917321 B2 JP5917321 B2 JP 5917321B2 JP 2012156561 A JP2012156561 A JP 2012156561A JP 2012156561 A JP2012156561 A JP 2012156561A JP 5917321 B2 JP5917321 B2 JP 5917321B2
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13023—Disposition the whole bump connector protruding from the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
図1から図7を用いて、BSV(Back Side Via)プロセスを用いた、本実施形態にかかる半導体装置の製造方法を説明する。詳細には、図1から図7の(a)は半導体装置の製造方法の各工程における断面図であり、図1から図7の(b)は、各工程における半導体基板100の上面(第1の面)100aの上方から見た上面図であり、図1から図7の(c)は、各工程における半導体基板100の下面(第2の面)100bの上方から見た下面図である。ここでは、上面100aに各種膜や素子等を形成し、次いで下面100bからエッチングを行ってTSV11を形成するようなBSVプロセスに適用した例を説明するが、本発明はこれに限定されるものではなく、NAND型フラッシュメモリ等の不揮発性半導体記憶装置といった様々な半導体素子及び半導体記憶素子を有する半導体装置や様々なプロセスに適用することができる。
第2の実施形態は、上面100aに絶縁膜202とポリシリコン膜203とがさらに積層されている点で、第1の実施形態と異なる。すなわち、このような構造に対しても本実施形態を適用することができる。
第3の実施形態は、半導体基板100の上面100aに配線層303が設けられているような構造に適用した点で、第1及び第2の実施形態と異なっている。すなわち、このような構造に対しても本実施形態を適用することができる。
11 TSV
12 半導体装置
13 溝
14 STI
15 凹部
40 コンタクト
100 半導体基板
100a 上面
100b 下面
101、102、106、121、202、208、301、307 絶縁膜
103、203、209 ポリシリコン膜
104、107、108、302 金属膜
109 バンプ
111、131、211、311 サイドノッチ
303 配線層
305 電極膜
Claims (6)
- シリコンを含む半導体基板の第1の面に、前記第1の面の上方から見て環状の形状を持つ環状絶縁膜を形成し、
前記第1の面と前記環状絶縁膜との上に、第1の絶縁膜とシリコン膜と第1の金属膜とを順次積層し、
前記第1の金属膜をストッパーとして用いた第1のエッチングにより、前記第1の面の反対側にある前記半導体基板の第2の面から、前記半導体基板と前記第1の絶縁膜と前記シリコン膜とを貫き、前記環状絶縁膜の環内を通過し、前記第1の金属膜の表面に達する開口部を形成し、
前記第1のエッチング後の第2のエッチングにより、前記開口部内の前記シリコン膜に横方向の凹部を形成し、
前記開口部の内壁を覆うように第2の絶縁膜を形成し、
前記開口部に第2の金属膜を埋め込んで、前記第1の金属膜と接続する貫通電極を形成する、
ことを備える半導体装置の製造方法。 - 前記半導体基板の一部が前記開口部と前記環状絶縁膜との間に位置するように、前記開口部は形成される、請求項1に記載の半導体装置の製造方法。
- 第1の面とその反対側にある第2の面とを有する半導体基板と、
前記第1の面に形成され、前記第1の面の上方から見て環状の形状を持つ環状絶縁膜と、
前記第1の面と前記環状絶縁膜との上に形成された第1の絶縁膜と、
前記第1の絶縁膜の上に形成されたシリコン膜と、
前記シリコン膜の上に形成された第1の金属膜と、
前記第2の面から前記半導体基板と前記第1の絶縁膜と前記シリコン膜とを貫き、前記環状絶縁膜の環内を通過し、前記第1の金属膜の表面に達し、前記シリコン膜に横方向の凹部を有する開口部と、
前記開口部の内壁を覆うように形成された第2の絶縁膜と、
前記開口部に埋め込まれた第2の金属膜と、
を備える半導体装置。 - 前記第1の絶縁膜は20nm以下の膜厚を有する、請求項3に記載の半導体装置。
- 前記半導体基板の一部が前記開口部と前記環状絶縁膜との間に位置する、請求項3又は4に記載の半導体装置。
- 前記第2の絶縁膜は、前記凹部内に形成された部分を有する、請求項3から5のいずれか1項に記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2012156561A JP5917321B2 (ja) | 2012-07-12 | 2012-07-12 | 半導体装置及びその製造方法 |
US13/757,178 US8921224B2 (en) | 2012-07-12 | 2013-02-01 | Semiconductor device having through electrode and method for manufacturing the same |
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JP2012156561A JP5917321B2 (ja) | 2012-07-12 | 2012-07-12 | 半導体装置及びその製造方法 |
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JP2014022396A JP2014022396A (ja) | 2014-02-03 |
JP5917321B2 true JP5917321B2 (ja) | 2016-05-11 |
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Publication number | Priority date | Publication date | Assignee | Title |
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US9576881B2 (en) | 2013-02-18 | 2017-02-21 | Kabushiki Kaisha Toshiba | Semiconductor device |
JP6489942B2 (ja) | 2015-05-29 | 2019-03-27 | 東芝メモリ株式会社 | 半導体デバイスの製造方法 |
US10269683B2 (en) | 2016-02-24 | 2019-04-23 | Toshiba Memory Corporation | Semiconductor device having a through electrode and method of manufacturing the same |
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US6023041A (en) * | 1996-11-08 | 2000-02-08 | W.L. Gore & Associates, Inc. | Method for using photoabsorptive coatings and consumable copper to control exit via redeposit as well as diameter variance |
WO1998020528A1 (en) * | 1996-11-08 | 1998-05-14 | W.L. Gore & Associates, Inc. | METHOD FOR IMPROVING RELIABILITY OF THIN CIRCUIT SUBSTRATES BY INCREASING THE Tg OF THE SUBSTRATE |
JP2002289623A (ja) * | 2001-03-28 | 2002-10-04 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2004152967A (ja) | 2002-10-30 | 2004-05-27 | Fujikura Ltd | 反応性イオンエッチングによる貫通孔の形成方法及び反応性イオンエッチングにより形成された貫通孔を有する基板 |
JP2005276877A (ja) * | 2004-03-23 | 2005-10-06 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
JP4373866B2 (ja) * | 2004-07-16 | 2009-11-25 | 三洋電機株式会社 | 半導体装置の製造方法 |
JP2006210485A (ja) | 2005-01-26 | 2006-08-10 | Matsushita Electric Ind Co Ltd | ドライエッチング方法 |
KR100826979B1 (ko) * | 2006-09-30 | 2008-05-02 | 주식회사 하이닉스반도체 | 스택 패키지 및 그 제조방법 |
JP2008210952A (ja) | 2007-02-26 | 2008-09-11 | Sanyo Electric Co Ltd | 半導体装置の製造方法、シリコンインターポーザの製造方法および半導体モジュールの製造方法 |
JP5656341B2 (ja) * | 2007-10-29 | 2015-01-21 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置およびその製造方法 |
JP5259197B2 (ja) * | 2008-01-09 | 2013-08-07 | ソニー株式会社 | 半導体装置及びその製造方法 |
JP5462524B2 (ja) * | 2009-05-13 | 2014-04-02 | パナソニック株式会社 | 半導体装置 |
JP2011003645A (ja) * | 2009-06-17 | 2011-01-06 | Sharp Corp | 半導体装置およびその製造方法 |
JP2011009645A (ja) | 2009-06-29 | 2011-01-13 | Toshiba Corp | 半導体装置及びその製造方法 |
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JP2014022396A (ja) | 2014-02-03 |
US8921224B2 (en) | 2014-12-30 |
US20140015139A1 (en) | 2014-01-16 |
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