JP6674406B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 40
- 238000004519 manufacturing process Methods 0.000 title description 15
- 239000000758 substrate Substances 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 5
- 238000003475 lamination Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 description 20
- 230000002093 peripheral effect Effects 0.000 description 19
- 238000005530 etching Methods 0.000 description 15
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 9
- 238000003860 storage Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000005380 borophosphosilicate glass Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Description
なお、図面は模式的または概念的なものであり、各部分の厚みと幅との関係、部分間の大きさの比率などは、必ずしも現実のものと同一とは限らない。また、同じ部分を表す場合であっても、図面により互いの寸法や比率が異なって表される場合もある。
なお、本願明細書と各図において、既出の図に関して前述したものと同様の要素には同一の符号を付して詳細な説明は適宜省略する。
一例として、半導体装置が3次元構造の半導体記憶装置である場合について説明する。
図1は、半導体装置1を示す断面図である。
図1に示すように、半導体装置1には、基板10が設けられている。基板10は、半導体基板であって、単結晶シリコン等のシリコン(Si)を含む。
なお、本明細書において、基板10の上面10aに対して平行な方向であって、相互に直交する2方向をX方向及びY方向とする。X方向及びY方向の双方に対して直交する方向をZ方向とする。
トンネル絶縁膜21は、チャネル20の周囲に設けられている。トンネル絶縁膜21は、例えば、シリコン酸化物を含む。
電荷蓄積膜22は、トンネル絶縁膜21の周囲に設けられている。電荷蓄積膜22は、例えば、シリコン窒化物(SiN)を含む。チャネル20と電極膜40(ワード線)との交差部分に、電荷蓄積膜22を含むメモリセルが形成される。
ブロック絶縁膜23は、電荷蓄積膜22の周囲に設けられている。例えば、ブロック絶縁膜23は、シリコン酸化物を含むシリコン酸化膜、アルミニウム酸化物(AlO)を含むアルミニウム酸化膜、または、これらの積層膜である。
絶縁膜50は、絶縁膜44と異なる材料、例えば、シリコン窒化物を含む。例えば、絶縁膜50の厚さW2は、50ナノメートル以上100ナノメートル以下である。
図2〜図4は、半導体装置1を示す断面図である。図2〜図4は、図1に示された領域をX方向片側(−X方向)に広げた領域を示しており、絶縁膜50が形成される位置の例を示している。
図2に示すように、半導体装置1には、周辺領域Rpがさらに設けられている。図2の例では、周辺領域Rpは、X方向において階段領域Rcに隣り合うように位置する。つまり、図1及び図2に示すように、周辺領域Rp、階段領域Rc及びメモリセル領域Rmは、X方向に向かって順に配置されている。
回路部70及び絶縁膜71上には、絶縁膜44が位置している。
例えば、図3に示すように、絶縁膜50は、階段領域Rcにおいて、絶縁膜44の一部上に位置するように、周辺領域Rpにおいては形成されなくても良い。つまり、絶縁膜50は、階段状の端部15tの下部に相当する階段領域Rcの一部と、周辺領域Rpとには形成されない。
図5、図6(a)、図6(b)、図7〜図12は、半導体装置1の製造方法を示す断面図である。
図5及び図7〜図12に示された領域は、図2に示された領域に相当する。図6(a)及び図6(b)は、図5に示す工程の一部を説明する図である。図10及び図11は、図9に示す工程の一部を説明する図である。なお、以下において、階段領域Rc及び周辺領域Rpの製造工程について説明する。
次に、図8に示すように、階段領域Rcにおいて、例えばCMP(Chemical Mechanical Polishing)法により、絶縁膜45の一部を除去して上面を平坦化する。
また、メモリセル領域Rm及び階段領域Rcにおいては、積層体15aにX方向及びZ方向に延びる複数のスリットが形成され、スリットを介してウェットエッチング等のエッチング処理を施すことにより、犠牲膜80を除去する。犠牲膜80を除去することで空洞が形成され、スリットを介してタングステン等の金属を堆積させて空洞内を埋め込むことで電極膜40を形成する。これにより、絶縁膜41及び電極膜40が交互に積層された積層体15が形成される。
なお、犠牲膜80の除去において、絶縁膜50は除去されない。
このようにして、半導体装置1が製造される。
3次元構造の半導体記憶装置において、積層体の端部にコンタクトを形成する場合、電極膜の積層数が増加するにつれて、コンタクトホールのアスペクト比が高くなると共に各電極膜の厚さが薄くなる虞がある。また、積層体の端部の形状が階段状であるので、上層の電極膜と下層の電極膜との間ではコンタクトホールの高さが異なることになる。これにより、上層の電極膜から下層の電極膜まで複数のコンタクトホールを一度に形成する場合、電極膜の積層数が増加するにつれて、電極膜と、電極膜上の絶縁膜との間のエッチング選択比を確保し難くなる。電極膜及び絶縁膜の間のエッチング選択比が小さいと、電極膜のテラス上に形成するコンタクトホールが、電極膜と、その直下の絶縁膜とを突き抜けてしまうことで電極膜間の短絡が発生し易い。
本実施形態によれば、積層体の階段状の部分に、突き抜けが発生なく信頼性高くコンタクトを形成可能な半導体装置及びその製造方法を提供する。
Claims (5)
- 基板と、
前記基板上に設けられ、それぞれ離れて積層された複数の電極膜を有し、端部の形状が前記複数の電極膜のそれぞれにテラスが形成された階段状である積層体と、
前記端部上に設けられた第1絶縁膜と、
前記第1絶縁膜上に設けられ、前記端部に沿って位置し、少なくとも一部が傾斜して延びている第2絶縁膜と、
前記第2絶縁膜上に設けられた第3絶縁膜と、
前記第3絶縁膜上に設けられ、前記端部に沿って傾斜して延びている第4絶縁膜と、
前記第1絶縁膜及び前記第2絶縁膜内を前記複数の電極膜の積層方向に延び、前記複数の電極膜のテラス上に位置する複数のコンタクトと、
を備えた半導体装置。 - 前記第2絶縁膜は、前記端部に対して並行して位置する請求項1記載の半導体装置。
- 前記第2絶縁膜の傾斜方向は、前記基板の上面に沿った第1方向、及び、前記積層方向に対して傾斜した方向である請求項1または2に記載の半導体装置。
- 前記第1絶縁膜は、前記端部を覆っており、
前記第2絶縁膜は、前記第1絶縁膜の一部上に位置する請求項1〜3のいずれか1つに記載の半導体装置。 - 前記第2絶縁膜は、前記第1絶縁膜と異なる材料を含み、
前記第1絶縁膜は、シリコン酸化物を含み、
前記第2絶縁膜は、シリコン窒化物を含む請求項1〜4のいずれか1つに記載の半導体装置。
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