JP2012222141A - 半導体チップ - Google Patents

半導体チップ Download PDF

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Publication number
JP2012222141A
JP2012222141A JP2011086330A JP2011086330A JP2012222141A JP 2012222141 A JP2012222141 A JP 2012222141A JP 2011086330 A JP2011086330 A JP 2011086330A JP 2011086330 A JP2011086330 A JP 2011086330A JP 2012222141 A JP2012222141 A JP 2012222141A
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Japan
Prior art keywords
semiconductor substrate
alignment mark
semiconductor chip
electrode
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2011086330A
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English (en)
Inventor
Nobuyuki Nakamura
暢之 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
Elpida Memory Inc
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Publication date
Application filed by Elpida Memory Inc filed Critical Elpida Memory Inc
Priority to JP2011086330A priority Critical patent/JP2012222141A/ja
Priority to US13/427,960 priority patent/US8692384B2/en
Publication of JP2012222141A publication Critical patent/JP2012222141A/ja
Priority to US14/196,560 priority patent/US9006905B2/en
Priority to US14/676,934 priority patent/US9385067B2/en
Pending legal-status Critical Current

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Abstract

【課題】金属原子の拡散に起因する素子特性の劣化を抑制する。
【解決手段】半導体チップは、半導体基板１０と、半導体基板１０を貫通する貫通電極２０と、半導体基板１０を貫通する金属柱４０と、アライメントマーク４７と、絶縁性を有する筒状の絶縁膜５０とを有する。アライメントマーク４０は、半導体基板１０の外部に露出した金属柱４０の端部によって形成されている。筒状の絶縁膜５０は、半導体基板１０に形成されており、金属柱４０を取り囲んでいる。
【選択図】図３

Description

本発明は、位置決めを行う際に利用されるアライメントマークを有する半導体チップに関する。
近年、電子機器の小型化や高機能化に伴って、互いに積層された複数の半導体チップから構成されるチップ積層体を備えたＣｏＣ（Chip on Chip）型の半導体装置が開発されている。ＣｏＣ型の半導体装置では、半導体チップを互いに積層する際に、半導体チップ同士の位置決め、即ちアライメントが行われる。
特許文献１の図２（ｂ）および図３には、半導体チップを位置決めする際に利用されるアライメントマークが開示されている。特許文献１に記載の半導体チップは、二以上の導電性の貫通プラグを有するマルチチップ半導体装置用のチップである。複数の貫通プラグのうちの一以上のプラグはアライメントマークとして用いられる。つまり、アライメントマークは、貫通プラグと同じ金属材料から構成されている。アライメントマークは、チップの表面および裏面で識別できるように構成されている。これにより、アライメントマークが、貫通プラグと同一の工程で製作できる。
特開２００５−２１７０７１号公報
特許文献１に記載のアライメントマークは、貫通プラグと同一の工程で製造される。したがって、アライメントマークは、貫通プラグと同一の金属材料、例えば銅からなる。本願発明者は、アライメントマークを構成する金属原子が半導体基板に拡散すると、半導体基板に形成されている機能素子の特性が低下することがあるということを見出した。
例えば、半導体チップがＤＲＡＭのようなメモリチップである場合、半導体基板中の金属不純物に起因して、機能素子としてのキャパシタに蓄えられている電荷がリークし易くなる。これにより、ＤＲＡＭのデータの保持時間（ホールドタイム）が低下してしまう。
したがって、貫通プラグ（貫通電極）と同様の金属材料から成るアライメントマークを備えた半導体チップにおいて、金属原子の拡散に起因する素子特性の劣化を抑制することが望まれる。
本発明の一態様における半導体チップは、半導体基板と、半導体基板を貫通する貫通電極と、半導体基板を貫通する金属柱と、アライメントマークと、絶縁性を有する筒状の絶縁膜とを有する。アライメントマークは、半導体基板の外部に露出した金属柱の端部によって形成されている。筒状の絶縁膜は、半導体基板に形成されており、金属柱を取り囲んでいる。
上記構成の半導体装置によれば、アライメントマークとして利用される金属柱を取り囲む筒状の絶縁膜が、半導体基板中への金属原子の拡散を防止する。そのため、金属原子の拡散に起因する素子特性の劣化を抑制することができる。
第１の実施形態の半導体チップの概略平面図である。 第１の実施形態の半導体チップにおける、貫通電極およびアライメントマーク部周辺の構成を示す概略図である。 図２の３Ａ−３Ａ線に沿った半導体チップの断面図である。 （ａ）〜（ｃ）は、第１の実施形態の半導体チップの製造工程を示す図である。 （ａ）および（ｂ）は、図４に続いて行われるステップを示す図である。 （ａ）および（ｂ）は、図５に続いて行われるステップを示す図である。 （ａ）および（ｂ）は、図６に続いて行われるステップを示す図である。 図７に続いて行われるステップを示す図である。 第２の実施形態の半導体チップにおける、貫通電極およびアライメントマーク部周辺の構成を示す概略図である。 第３の実施形態の半導体チップにおける、貫通電極およびアライメントマーク部周辺の構成を示す概略図である。 第３の実施形態の半導体チップの製造工程の一ステップを示す図である。 （ａ）および（ｂ）は、図１１に続いて行われるステップを示す図である。 （ａ）および（ｂ）は、図１２に続いて行われるステップを示す図である。
以下、本発明について図面を用いて説明する。
図１は第１の実施形態の半導体チップの概略平面図である。図２は、図１に示す領域Ａの概略拡大図である。図３は、図２の３Ａ−３Ａ線に沿った半導体チップの断面図である。
半導体チップは、半導体基板１０と、半導体基板１０を貫通する貫通電極２０と、アライメントマーク部４０と、絶縁性の筒状の絶縁膜３０，５０を有する。半導体基板１０の材料は、例えばシリコンのような半導体（Silicon substrate）を用いることができる。半導体基板１０には、半導体チップの機能に応じた機能素子８０が形成されている。機能素子８０は、貫通電極２０から電力を供給される。
機能素子８０は、図１に示す半導体基板の一面とは反対側の面における素子領域Ｂに配置されている。機能素子８０は、例えば半導体チップがＤＲＡＭ用のチップである場合、トランジスタおよびこれと直列配置されたキャパシタから成る。
貫通電極２０およびアライメントマーク部（金属柱）４０は、半導体チップの少なくとも一方の面に露出している。図３に示す例では、貫通電極２０およびアライメントマーク部４０が露出している、半導体チップの一面に絶縁層６２が形成されている。絶縁層６２は、たとえば窒化シリコンを用いることができる。なお、図１および図２では、図の簡略化のため、この絶縁層６２は図示されていない。
アライメントマーク部４０は、半導体基板１０を貫通しており、貫通電極２０と同一の金属材料を含む金属柱である。これにより、アライメントマーク部４０を貫通電極２０と同一の製造工程によって形成することができ、その結果、半導体チップの製造が容易になる。アライメントマーク部４０を構成する金属柱の端部は、半導体チップの表面に露出しており、位置決め用のアライメントマーク４７として利用される。
第１の筒状の絶縁膜３０は、半導体基板１０に形成されており、貫通電極２０を取り囲んでいる。第２の筒状の絶縁膜５０は、半導体基板１０に形成されており、アライメントマーク部４０を取り囲んでいる。より具体的には、筒状の絶縁膜３０または５０は、半導体チップの表面に平行な面内において、貫通電極２０またはアライメントマーク部４０を取り囲んでいる。第１の実施形態では、筒状の絶縁膜３０，５０は、貫通電極２０またはアライメントマーク部４０から離れて配置されている。
両方の筒状の絶縁膜３０，５０は、同じ材料から構成されていることが好ましい。これにより、両方の筒状の絶縁膜を同一の製造工程によって製造することができる。
筒状の絶縁膜５０は、アライメントマーク部４０を構成する金属原子が、半導体基板１０、特に半導体基板の素子領域Ｂに拡散することを防止する。したがって、金属原子の拡散に起因する機能素子８０の特性の劣化を抑制することができる。金属原子の拡散の防止の観点から、筒状の絶縁膜５０は、半導体基板１０を貫通していることが好ましい。
金属材料の拡散防止のため、筒状の絶縁膜３０，５０は窒化シリコン膜３２，５２を含んでいることが好ましい。筒状の絶縁膜３０，５０は、この窒化シリコン膜３２，５２で表面が覆われた酸化シリコン膜３４，５４を含んでいることがより好ましい。また、筒状の絶縁膜５０は、多結晶シリコン膜（ポリシリコン膜）を含んでいても良い。この場合、アライメントマーク部４０からの金属原子の拡散をより抑制することができる。
半導体チップは、半導体基板上に形成された層間絶縁層６１や配線層７８やバンプ電極７０やプラグ７７等を有していても良い。バンプ電極７０は、半導体チップの、貫通電極２０が露出している一面とは反対側の一面に露出している。
配線層７８は、複数の階層に形成されていて良い。ある階層の配線層７８とそれに隣接する配線層７８との間に、層間絶縁層６１が形成されている。プラグ７７は、層間絶縁層６１中を延びており、貫通電極２０、バンプ電極７０および配線層７８を導通している。
配線層７８の材料は、アルミニウムやタングステン等を用いることが出来る。ここでは、一例として、貫通電極２０と接する配線層７８をタングステンによって形成し、その他の配線層７８をアルミニウムによって形成した。また、貫通電極２０に接する配線層７８と同じ階層に、アライメントマーク部４０と接するエッチングストッパ層４８が形成されていることが好ましい。
半導体チップのバンプ電極７０が形成されている一面に、カバー層６６および例えばポリイミドからなる絶縁層６７が形成されていても良い。
この半導体チップは、当該チップが互いに積層されて成る半導体装置に好適に用いられる。アライメントマーク部４０を構成する金属柱の端部は、半導体チップを互いに積層する際の位置決めに利用される。複数の半導体チップは、同種のチップであっても良く、異種のチップであっても良い。アライメントマーク４７は、半導体チップを任意の部材に対して位置決めするために使用することができる。
上記実施形態では、アライメントマーク４７は、半導体チップの一方の面のみに露出している。これに限らず、アライメントマーク４７は半導体チップの両面に存在していても良い。この場合、バンプ電極７０が形成されている一面に露出するアライメントマーク部は、当該一面と最も近くに位置する配線層７８と同一の金属材料から成ることが好ましい。半導体チップの両面のアライメントマーク部は、位置決めされるべき部材がチップの両側にある場合、例えば３層以上のチップが積層される場合に有効である。
アライメントマーク４７は、例えばカメラのような撮像装置によって認識可能である。撮像装置によって取り込んだ画像を画像処理することで、コンピュータによって正確に位置決めすることが出来る。アライメントマーク部４０の形状は貫通電極２０の形状とは異なっている。これにより、アライメントマーク部４０と貫通電極２０の違いを検知することができる。アライメントマーク部４０は、貫通電極２０との違いが検知できれば、どのような形状であっても良い。
次に、半導体チップの製造工程の一例について説明する。本例では、シリコンから成る半導体基板（Silicon substrate）１０を準備する。図４（ａ）に示すように、半導体基板１０の第１の面１０ａに筒状の絶縁膜を形成するための枠状の穴部（トレンチ）１２を形成する。
次に、トレンチ１２の内部に筒状の絶縁膜３０，５０を形成する。具体的には、図４（ｂ）に示すように、トレンチ１２の側壁および半導体基板の第１の面１０ａ上に窒化シリコン膜３２，５２を形成し、それからトレンチ１２の内部を埋めるように、窒化シリコン膜３２，５２上に酸化シリコン膜３４，５４を形成する。酸化シリコン膜３４，５４は、例えばＬＰ−ＴＥＯＳ（Low Pressure Si(OC2H5)4）膜を用いることができる。
その後、図４（ｃ）に示すように、半導体基板１０の第１の面１０ａ上の窒化シリコン膜３２，５２および酸化シリコン膜３４，５４を除去して半導体基板１０を露出させる。酸化シリコン膜および窒化シリコン膜の除去は、例えばエッチバック法または化学的機械研磨（ＣＭＰ）によって行われる。これにより、トレンチ１２内に筒状の絶縁膜３０，５０が形成される。貫通電極付近の筒状の絶縁膜３０と、アライメントマーク部付近の筒状の絶縁膜５０とは、同一の工程によって一括して形成できる。
次に、半導体基板１０の第１の面１０ａに、半導体チップの機能に応じた機能素子８０、層間絶縁層６１、配線層７８、プラグ７７、カバー層６６、絶縁層６７等を形成する（図５（ａ）参照）。配線層７８は、複数の階層に形成されているが、単一の層であっても良い。層間絶縁層６１は、各階層の配線層７８同士の間に形成されている。絶縁層は、例えばポリイミドからなり、バンプ電極が形成される位置、つまりプラグ７７が形成されている位置に対応してパターニングされている。なお、アライメントマーク部が形成されるべき領域には、プラグやバンプ電極は不要である。
半導体チップがＤＲＡＭ用のチップである場合には、機能素子８０として、トランジスタおよびキャパシタが形成される。また、層間絶縁層６１の、アライメントマーク部４０が形成される領域にエッチングストッパ層４８を形成しておくことが好ましい。
エッチングストッパ層４８は、プラグ７７の、半導体基板の第１の面１０ａに最も近くに位置する配線層７８の位置に形成されることが好ましく、当該配線層７８を構成する材料と同一の金属材料からなることがより好ましい。本例では、エッチングストッパ層４８として、タングステンを用いた。
図５（ａ）に示すように、プラグ７７および絶縁層６７上に、めっきを析出させるためのシード層７１をスパッタ法により形成する。シード層７１としては、例えばＣｕ／Ｔｉ層を用いることができる。
それから、シード層７１上に電極を形成する。例えばフォトリソグラフィ法により、シード層７１上に所定の形状のポジ型レジスト９０を形成し、プラグ７７上のシード層７１がレジストから露出するようにレジスト９０をパターニングする。それから、電気めっき法によって、レジスト９０から露出したシード層７１上に電極を形成する。
電極は、例えば、レジスト９０の開口内に例えば銅からなる金属柱７２を形成した後に当該金属柱７２の表面に例えばＳｎＡｇから成る金属膜７３を形成することで作成できる。このようにして、シード層７１、金属柱７２および金属膜７３からなるバンプ電極７０が作成できる。なお、バンプ電極７０を構成する材料は、上記例に限定されるものではない。
バンプ電極７０の形成後、レジスト９０を除去し、チップ表面に露出したシード層７１を除去する。その後、バンプ電極７０を一旦高温にしてＳｎＡｇ２２のみを溶融させた後に降温することで、図５（ｂ）に示すように、バンプ電極７０の先端を凸条にすることができる。
次に、半導体基板１０の第１の面１０ａとは反対側の第２の面１０ｂを処理するため、図６（ａ）に示すように、バンプ電極７０および絶縁層６７上に介在層６８を介して支持体６９を貼り付ける。介在層６８は、例えばＬＴＨＣ（Light to Heat Conversion）や液状の紫外線硬化剤（UV-Cure Liquid Adhesive）のような着脱可能な接着材が用いられる。支持体６９は、例えばガラスからなるウエハサポートシステム（Wafer Support System）が用いられる。
次に、図６（ｂ）に示すように、半導体基板１０の第２の面１０ｂに筒状の絶縁膜３０，５０が露出するまで、半導体基板の第２の面１０ｂを研削する。半導体基板１０の研削後、例えばＣＭＰ法によって、半導体基板の第２の面１０ｂを平坦化する。
次に、図７（ａ）に示すように、半導体基板１０の第２の面１０ｂに、貫通電極およびアライメントマーク部用の穴部９２を形成する。このとき、半導体基板の第２の面１０ｂに例えば窒化シリコンからなる絶縁層６２を形成した後、穴部９２を形成するためのレジスト９１を塗布し、それから、半導体基板１０に穴部９２を形成することが好ましい。絶縁層６２としての窒化シリコンは、半導体基板の第２の面から金属材料、例えば銅が拡散することを防止する。
穴部９２は、例えばドライエッチングにより形成することができる。穴部９２は、筒状の絶縁膜３０，５０の内側に形成され、半導体基板１０を貫通することが好ましい。このとき、前述したエッチングストッパ層４８によって、穴部９２の深さが決定される。エッチングストッパ層４８は、エッチングに耐性を有する材料であればよい。貫通電極の形状とアライメントマーク部の形状とを相違させるため、貫通電極用の穴部の形状とアライメントマーク部用の穴部の形状とは相違させておく。
次に、図７（ｂ）に示すように、レジスト９１を除去し、穴部９２の底面および側面にシード層２１，４１を形成する。シード層２１，４１は、例えばＣｕ／Ｔｉ層から構成することができる。シード層２１，４１は、例えばスパッタ法により形成することができる。
次に、図８に示すように、穴部９２に貫通電極２０およびアライメントマーク部４０を形成する。具体的には、まず、半導体基板１０の第２の面１０ｂの上に貫通電極およびアライメントマーク部を所定の形状にするためのレジスト９３を形成する。それから、穴部９２を、例えば電気めっき法により金属材料２２，４２で埋める。金属材料２２，４２は、例えば銅を用いることが出来る。ここでは、穴部を埋める金属材料２２，４２の表面に別の金属膜２３，４３を形成した。金属膜２３，４３は、例えば電気めっき法によってＡｕ／Ｎｉから形成することができる。このようにして、シード層２１，４１、金属材料２２，４２および金属膜２３，４３からなる貫通電極２０やアライメントマーク部（金属柱）４０が作成される。
貫通電極２０は、半導体基板１０としてのシリコンを貫通するシリコン貫通ビア（Through Silicon Via：ＴＳＶ）である。アライメントマーク部４０は、この貫通電極２０とはことなる形状ではあるが、同様の構造を有している。
貫通電極２０とアライメントマーク部４０とは、上記のように、同一の金属材料から形成されることが好ましい。この場合、同一の工程によって貫通電極２０とアライメントマーク部４０とを同時に形成することができる。
この後、レジスト９３を除去し、絶縁層６２上の不要なシード層２１を除去する。それから、介在層６８および支持体６９を除去することで、図１〜図３に示した半導体チップを製造することができる。
以下、図９を参照して第２の実施形態における半導体チップについて説明する。図９は、第２の実施形態の半導体チップの、貫通電極およびアライメントマーク部周辺の構成を示す平面図である。
第２の実施形態の半導体チップにおいて、貫通電極２０と、アライメントマーク４７を形成するアライメントマーク部との構成は、第１の実施形態の半導体チップと同様である。筒状の絶縁膜３０，５０は、貫通電極２０またはアライメントマーク部を取り囲んでいる。ただし、筒状の絶縁膜５０は、半導体基板１０の表面に平行な面内で、角部のない滑らかな閉曲線により構成されている。クラックが発生し易い角部を排除することで、筒状の絶縁膜５０による金属原子の拡散防止の効果が低下することを防止することができる。
以下、図１０を参照して第３の実施形態における半導体チップについて説明する。図１０は、第３の実施形態の半導体チップの、貫通電極およびアライメントマーク部周辺の構成を示す平面図である。ただし、図１０では、チップの構成を明らかにするため、半導体基板１０の表面に形成される絶縁層は描かれていない。
第３の実施形態において、貫通電極２０およびアライメントマーク４７を形成するアライメントマーク部の構成は、第１の実施形態の半導体チップと同様である。筒状の絶縁膜３０，５０は、貫通電極２０またはアライメントマーク部４０を取り囲んでいる。本実施形態では、筒状の絶縁膜３０，５０は、貫通電極２０またはアライメントマーク部４０と接するサイドウォールである（図１３（ｂ）も参照。）。この場合においても、筒状の絶縁膜５０は、アライメントマーク部４０を構成する金属材料からの金属原子の拡散を防止することができる。
次に、第３の実施形態の半導体チップの製造方法について説明する。まず、第１の実施形態と同様に、半導体基板を準備する。ここでは、図４（ａ）〜（ｃ）に示す処理、つまり半導体基板の第１の面１０ａに筒状の絶縁膜を形成する処理は行わない。そして、図５（ａ），図５（ｂ）に示すように、機能素子８０、プラグ７７、バンプ電極７０等を形成する（図１１も参照）。それから、半導体基板１０の第２の面１０ｂを処理するために、バンプ電極７０および絶縁層６７の表面に介在層６８を介して支持体６９を貼り付ける。このとき、第１の実施形態と同様に、層間絶縁層中にエッチングストッパ層４８を形成しておく。これにより、図１１に示す状態のチップが得られる。
次に、図１２（ａ）に示すように、半導体基板１０の第２の面１０ｂに、貫通電極およびアライメントマーク部用の穴部９２を形成し、穴部９２の底面および側壁に筒状の絶縁膜３０，５０を形成する。このとき、半導体基板１０の第２の面１０ｂに例えば窒化シリコンからなる絶縁層を形成した後に穴部９２を形成しても良い。穴部９２は、半導体基板１０を貫通する深さであることが好ましい。このとき、エッチングストッパ層４８によって、穴部９２の深さが決定される。
次に、穴部９２の底面および側面に窒化シリコン膜３２，５２および酸化シリコン膜３４，５４を形成する。このようにして、窒化シリコン膜３２，５２および酸化シリコン膜３４，５４からなる筒状の絶縁膜３０，５０が形成される。次に、必要であれば、エッチバック法により、半導体基板１０の第２の表面１０ｂに形成されている余分な酸化シリコン膜３４，５４および／または窒化シリコン膜３２，５２を除去する（図１２（ｂ）参照）。このとき、半導体基板１０の第２の面１０ｂに所定の厚みの窒化シリコン膜を残しておくことが好ましい。
次に、図１３（ａ）に示すように、穴部９２内の酸化シリコン膜３４，５４の表面に、貫通電極およびアライメントマーク部の一部を構成するシード層２１，４１を形成する。シード層２１，４１は、例えばＣｕ／Ｔｉ層から構成することができる。シード層２１，４１は、例えばスパッタ法により形成することができる。
次に、図１３（ｂ）に示すように、穴部９２を金属材料２２，４２で埋めて貫通電極２０およびアライメントマーク部４０を形成する。具体的には、まず、半導体基板１０上に、貫通電極およびアライメントマーク部を所定の形状にするためのレジスト９３を形成する。それから、穴部９２内に、例えば電気めっき法により金属材料２２，４２を形成する。金属材料２２，４２は、例えば銅を用いることが出来る。ここでは、穴部９２内を銅で埋めて、この銅の表面に金属膜２３，４３を形成した。金属膜２３，４３は、例えばＡｕ／Ｎｉを用いることができ、電気めっき法によって形成できる。このようにして、シード層２１，４１、金属材料２２，４２および金属膜２３，４３からなる貫通電極２０またはアライメントマーク部４０が形成される。
貫通電極２０とアライメントマーク部４０とは、上記のように、同一の金属材料から形成されることが好ましい。この場合、同一の工程によって貫通電極２０とアライメントマーク部４０とを同時に形成することができる。
それから、レジスト９３および不要なシード層２１，４１を除去し、介在層６８および支持体６９を除去することで、第３の実施形態の半導体チップを製造することができる。
以上、本発明者によってなされた発明を実施例に基づき説明したが、本発明は上記実施例に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。
１０ 半導体基板
１２ トレンチ
２０ 貫通電極
３０，５０ 筒状の絶縁膜
３２，５２ 窒化シリコン膜
３４，５４ 酸化シリコン膜
４０ アライメントマーク部（金属柱）
４８ エッチングストッパ層
６１ 層間絶縁層
６２，６７ 絶縁層
６６ カバー層
７０ バンプ電極
７７ プラグ
７８ 介在層
７９ 支持体
８０ 機能素子
９２ 穴部

Claims (9)

  1. 半導体基板と、
    前記半導体基板を貫通する貫通電極と、
    前記半導体基板を貫通する金属柱と、
    前記半導体基板の外部に露出した前記金属柱の端部によって形成されたアライメントマークと、
    前記半導体基板に形成され、前記金属柱を取り囲む、絶縁性を有する筒状の絶縁膜と、を有する半導体チップ。
  2. 前記金属柱は前記貫通電極と同一の金属材料を有する、請求項１に記載の半導体チップ。
  3. 前記筒状の絶縁膜は前記金属柱から離れて配置されている、請求項１または２に記載の半導体チップ。
  4. 前記筒状の絶縁膜は、前記半導体基板の表面に平行な面内で滑らかな閉曲線を構成している、請求項３に記載の半導体チップ。
  5. 前記筒状の絶縁膜は前記金属柱と接している、請求項１または２に記載の半導体チップ。
  6. 前記筒状の絶縁膜は窒化シリコン膜を含んでいる、請求項１から５のいずれか１項に記載の半導体チップ。
  7. 前記筒状の絶縁膜は、前記窒化シリコン膜で覆われた酸化シリコン膜を含んでいる、請求項６に記載の半導体チップ。
  8. 前記筒状の絶縁膜はポリシリコンを含んでいる、請求項１から７のいずれか１項に記載の半導体チップ。
  9. 半導体基板と、
    前記半導体基板に形成された機能素子と、
    前記半導体基板を貫通し、前記機能素子に電力を供給する貫通電極と、
    前記半導体基板を貫通する金属柱と、
    前記半導体基板の外部に露出した前記金属柱の端部によって形成されたアライメントマークと、
    前記貫通電極を取り囲む第１の筒状の絶縁膜と、
    前記金属柱を取り囲み、前記第１の筒状の絶縁膜と同じ材料を有する第２の筒状の絶縁膜と、を有する半導体チップ。
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