TWI431750B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI431750B
TWI431750B TW100128163A TW100128163A TWI431750B TW I431750 B TWI431750 B TW I431750B TW 100128163 A TW100128163 A TW 100128163A TW 100128163 A TW100128163 A TW 100128163A TW I431750 B TWI431750 B TW I431750B
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Taiwan
Prior art keywords
insulating layer
semiconductor device
semiconductor substrate
electrode pad
disposed
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TW100128163A
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English (en)
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TW201222761A (en
Inventor
Mitsuyoshi Endo
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Toshiba Kk
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Publication of TW201222761A publication Critical patent/TW201222761A/zh
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Publication of TWI431750B publication Critical patent/TWI431750B/zh

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Description

半導體裝置及其製造方法 [相關申請案之交互參照]
此申請案基於於2010年8月10日申請之先前日本專利申請案2010-179564之優先權並主張其之專利權。
在此所述之發明主要有關於半導體裝置及製造其之方法。
因應可攜式資訊終端機或儲存裝置之微型化及高性能之需求，已執行半導體晶片的高密度安裝。作為實現半導體晶片的高密度安裝之技術，有堆疊半導體晶片的技術。在堆疊半導體晶片的情況中，歸功於對於堆疊層之數量或晶片的大小無限制的優點，有使用形成在半導體基板中之通孔來電連接半導體晶片之技術。
本發明之實施例實現生產效率經改善的半導體裝置。
一般而言，根據一實施例，半導體裝置包括半導體基板、第一絕緣層、電極墊、通孔、第二絕緣層、及導電材料。在包括表面及其之相對表面的半導體基板中，設置互連層並形成從該表面通過互連層至該相對表面的通槽。以第一絕緣層填充該通槽。電極墊與包括在互連層中之互連電連接。第二絕緣層設置在電極墊與第一絕緣層之間。通孔配置成與電極墊的下表面連通並通過第一絕緣層及第二絕緣層。導電材料設置在通孔中並與電極墊連接。
根據本發明之實施例，可改善半導體裝置之生產效率。
參照附圖於下詳細解釋半導體裝置及製造其之方法的示範實施例。本發明不限於下列實施例。
首先敘述根據第一實施例的半導體裝置之示意性組態。第1圖為繪示根據第一實施例的半導體裝置之剖面結構的部分剖面圖。第2圖為沿第1圖之線A-A的半導體裝置之部分底剖面圖。半導體裝置1包括半導體基板11、樹脂層(第一絕緣層)20、電極墊14、第二絕緣層(支撐絕緣層)12、第三絕緣層(支撐絕緣層)22、鈍化膜(第四絕緣層)17、及黏接層23。
半導體基板11設有以垂直方向通過半導體基板11通槽11a，亦即，從表面通至相對表面之通槽。形成樹脂層20使得合成樹脂填充通槽11a。配置複數電極墊14於樹脂層20上方。設置開口部15於形成在樹脂層20上方的複數電極墊14之每一者中。設置第二絕緣層12在電極墊14及樹脂層20之間，並覆蓋半導體基板11的第一表面11b。第二絕緣層12較佳具有高於樹脂層20的剛性。
設置第三絕緣層22在樹脂層20及第二絕緣層12之間，並且亦在樹脂層20及半導體基板11之間。第三絕緣層22覆蓋半導體基板11的第二表面11c，其為第一表面11b的背側。第三絕緣層22較佳具有高於樹脂層20的剛性。設置鈍化膜17在半導體基板11的第一表面11b並覆蓋第二絕緣層12及電極墊14。
設置黏接層23在半導體基板11的第二表面11c並覆蓋樹脂層20及半導體基板11。在半導體裝置1中，形成通孔21以通過電極墊14的開口部15。形成通孔21以通過黏接層23、樹脂層20、第三絕緣層22、第二絕緣層12、及鈍化膜17。通孔21的直徑大於電極墊14之開口部15的直徑並小於半導體基板11的厚度。藉由此組態，配置通孔21成與電極墊14的下表面連通。
如第2圖中所示，通槽11a具有在橫方向中為拉長的形狀並且具有垂直方向為短邊方向。互連13從電極墊14在與通槽11a的短邊方向平行的方向(與縱向垂直之方向)中延伸。
在一通槽11a中設置複數電極墊14。在第2圖中，設置四個電極墊14。在通槽11a的縱向中以規律間隔配置電極墊14。
接下來，將敘述製造半導體裝置1的程序。第3圖為解釋製造半導體裝置1之程序的流程圖。第4至15圖為解釋製造半導體裝置1之程序的圖。
參照第4及5圖，在步驟S1中，在半導體基板11上設置第二絕緣層12，並且在第二絕緣層12與電極墊14一體成形的設置互連13。在此，在電極墊14中設置開口部15。
與電極墊14一體成形設置的互連13不一定得藉由相同製程形成並可由不同製程形成。第二絕緣層12較佳與電極墊14電連接。互連13較佳與電極墊14類似地設置在第二絕緣層12。
在晶圓形式中組態並針對每一晶片區域標定半導體基板11。在此，可在第二絕緣層12中設置變成互連13的下層之互連層(大型積體電路(LSI)之多層互連層)。此外，可在半導體基板11上針對每一晶片區域設置場效電晶體。此外，可設置快閃記憶體、動態隨機存取記憶體(DRAM)、微電腦、邏輯電路、或影像感測器。可以無機絕緣膜(如氧化矽膜或氮化矽膜)形成第二絕緣層12。替代地，可使用堆疊結構，其中氮化矽膜堆疊於氧化矽層上。例如，第二絕緣層12及互連13的總厚度可設定至1至10μm的範圍。
在此，半導體基板11不單指矽基板，還有包括半導體裝置及設置在半導體裝置的絕緣膜中之多層互連的矽基板。
接下來，如第6及7圖中所示，在步驟S2中，使用化學蒸氣沉積(CVD)技術在互連13及電極墊14上設置鈍化膜17。可以無機絕緣膜(如氧化矽膜或氮化矽膜)形成鈍化膜17。在鈍化膜17中形成包括在通孔21的一部分中之開口。
設置鈍化膜17使得電極墊14之上表面的一部分不被鈍化膜17覆蓋。在電極墊14上之鈍化膜17的開口17a大於電極墊14的開口部15。透過在電極墊14上之鈍化膜17的開口17a暴露出第二絕緣層12、電極墊14的上表面、及電極墊14的內側表面。
接下來，如第8圖中所示，在步驟S3中，在鈍化膜17上設置暫時黏接層19a及支撐基板19b，其在當研磨半導體基板11的第二表面11c支撐半導體基板11。作為暫時黏接層19a，可使用在黏接至半導體基板11之後可自半導體基板11剝除的黏性樹脂片。替代地，為了方便在黏接至半導體基板11之後可自半導體基板11剝除，可使用紫外線可硬化樹脂片。可以有機材料或矽或玻璃晶圓來製造支撐基板19b。
接下來，如第9圖中所示，在步驟S4中，藉由研磨半導體基板11的背表面(在第9圖中之下表面)來薄化半導體基板11。例如，經薄化的半導體基板11之厚度約為20μm。在使半導體基板11變薄的情況中，在執行機械研磨後，較佳拋光半導體基板11的背表面，例如，使用化學機械拋光(CMP)技術。
接下來，如第10圖中所示，在步驟S5中，使用光微影技術及乾蝕刻技術移除其上設有電極墊14的半導體基板11之一區域。移除設有電極墊14之區域的正下方之半導體基板11的部份。在大多數之情況中，其上形成有電極墊14的半導體基板11之區域不作為晶片區域內之裝置(不設有功能元件)，且即使移除其上形成有電極墊14的區域，對於半導體裝置1之性能的影響很小。藉由移除其上形成有電極墊14的半導體基板11之區域，形成垂直通過半導體基板11之通槽11a。當形成通槽11a時，暴露出第二絕緣層12的下側表面之一部分及半導體基板11的側表面。
例如，通槽11a的槽寬度X約為40μm。代表通槽11a之槽寬度X與經薄化的半導體基板11之厚度之間的寬高比為0.5。因此，由於通槽11a的側表面之垂直性中的惡化難以造成問題，乾蝕刻速度可增加，並且可以高速執行形成通槽11a的程序。
在此，可藉由使用化學之濕蝕刻來形成通槽11a。在藉由濕蝕刻形成通槽11a的情況中，可同時處理複數半導體基板11，並因此可改善生產效率。
接下來，如第11圖中所示，在步驟S6中，設置覆蓋第二絕緣層12之暴露部分、半導體基板11側表面、及半導體基板11之第二表面11c的第三絕緣層22，例如，藉由使用CVD技術。可以無機絕緣膜(如氧化矽膜或氮化矽膜)形成第三絕緣層22。
接下來，如第12圖中所示，在步驟S7中，以樹脂層20填充半導體基板11的通槽11a。例如，可以聚酰亞胺、苯並環丁烷(BCB)、聚苯並噁唑(PBO)、環氧樹脂、或苯酚之有機材料形成樹脂層20。樹脂層20較佳具有熱塑性。此外，樹脂層20具有光敏性。例如，可使用印刷技術或塗佈技術來形成供填充之樹脂層20。
接下來，如第13圖中所示，在步驟S8中，在樹脂層20中形成通孔21。通孔21的直徑大於電極墊14之開口部15的直徑並且例如約為10μm。寬高比(其為與半導體基板11之厚度的比例)為2。如上述，即使寬高比相對大，若以光敏樹脂形成樹脂層20，可使用執行典型曝光及顯影的方法，所以可改善生產效率，並可輕易形成通孔21。當樹脂層20不具有光敏性時，可使用光微影技術及乾蝕刻技術。
接下來，如第14圖中所示，在步驟S9中，在半導體基板11之第二表面11c側，在除了通孔21外之區域上設置黏接層23。可例如使用光敏樹脂來設置黏接層23。若使光敏樹脂曝光，則可將光敏樹脂暫時硬化至半硬化狀態中，並且可使用半硬化狀態的光敏樹脂作為熱固黏劑。例如，在堆疊諸半導體基板11的情況中，黏接層23作用為將半導體基板11互相黏接，並可使用非光敏樹脂之各種材料作為黏接材料。
接下來，如第15圖中所示，在步驟S10中，藉由使用黏接層23作為遮罩之乾蝕刻來移除第二絕緣層12及第三絕緣層22。在半導體基板11之第二表面11c側執行用於移除第二絕緣層12及第三絕緣層22的程序。藉由使用黏接層23作為遮罩來執行乾蝕刻，移除覆蓋電極墊14的第二絕緣層12及第三絕緣層22的部份，並且第二絕緣層12及第三絕緣層22延伸至通孔21的側壁。此外，當移除了第二絕緣層12及第三絕緣層22時，甚至在半導體基板11之第二表面11c側暴露出電極墊14。
接下來，在步驟S11中，例如，藉由剝除藉由暫時黏接層19a所附接的支撐基板19b，並藉由分切來分割晶片區域，可獲得具有第1圖中所示之結構的半導體裝置1。使用具有上述組態的半導體裝置1作為例如堆疊在第16圖中所示之安裝基板25上之堆疊型半導體裝置。在第16圖中，在安裝基板25上堆疊複數半導體裝置1，並接著以點膠技術或鍍覆技術使用導電材料26來填充通孔21。藉由以導電材料26填充通孔21的內部，可獲得其中在堆疊方向中為互相通孔連接的半導體裝置1之堆疊型半導體裝置。
如上所述，在本實施例中，由於通孔21是形成在填充通槽11a的樹脂層20中，相較於當在半導體基板11中形成通孔的情況，可輕易且有效地形成通孔。
此外，由於在半導體基板11中所形成之通槽11a在寬高比上來說比通孔21更小並且不需通槽11a之側表面的垂直性的高度準確性，可使用乾蝕刻或濕蝕刻來輕易及有效地形成通槽11a。尤其，當使用濕蝕刻時，藉由同時處理複數半導體基板，可進一步改善生產效率。
如上述，形成通槽11a的程序並且以樹脂層20填充通槽11a的程序為形成通孔21所必需者，但藉由將程序變得更簡單及更有效率，相較於在半導體基板11中直接形成通孔的情況，可改善半導體裝置1的生產效率。
此外，在本實施例中，第二絕緣層12及第三絕緣層22延伸至通孔21的側表面並設置在電極墊14與樹脂層20之間，所以將第二絕緣層12及第三絕緣層22組態成支撐電極墊14。由於藉由在剛性上比樹脂層20更高的第二絕緣層12及第三絕緣層22支撐電極墊14，改善電極墊14的位置準確性的程度。因此，即使通孔21之間的間隔很小，可抑制與相鄰通孔21之短路的發生。如上所述，將第二絕緣層12及第三絕緣層22作用為支撐電極墊14的支撐絕緣層。
此外，由於第二絕緣層12及第三絕緣層22延伸至通孔21的側表面，可改善電極墊14與半導體基板11之間的絕緣可靠度。此外，由於以第三絕緣層22覆蓋半導體基板11的第二表面11c及通槽11a的側表面，可防止雜質擴散至半導體基板11中，所以可改善半導體裝置1的可靠度。
第17圖為繪示根據第一實施例的修改例之半導體裝置1的剖面結構之部分剖面圖。在本修改例中，在堆疊半導體裝置1之前，藉由鍍覆技術在電極墊14上形成焊接凸塊30。因此，在電極墊14中不設置開口部15，並且形成通孔21以通過樹脂層20、第三絕緣層22、及第二絕緣層12並與電極墊14連通。形成導電材料26以藉由諸如鍍覆技術之技術填充通孔21。由於當堆疊半導體裝置1時凸塊30與導電材料26電連接，可使用具有上述組態之半導體裝置1作為其中半導體裝置1在堆疊方向中互相連接之堆疊型半導體裝置。
雖已敘述某些實施例，這些實施例僅為示範性呈現，並且意圖限制本發明之範疇。確實，可以各種其他形式體現在此所述的新穎裝置及方法；此外，可做出在此所述之裝置及方法形式中的各種省略、替換、及改變而不背離本發明之精神。所附之申請專利範圍及其等效者意圖覆蓋會落入本發明之範疇及精神內的這種形式或修改。
1．．．半導體裝置
11．．．半導體基板
11a．．．通槽
11b．．．第一表面
11c．．．第二表面
12．．．第二絕緣層
13．．．互連
14．．．電極墊
15．．．開口部
17．．．鈍化膜
17a．．．開口
19a．．．暫時黏接層
19b．．．支撐基板
20．．．樹脂層
21．．．通孔
22．．．第三絕緣層
23．．．黏接層
25．．．安裝基板
26．．．導電材料
30．．．焊接凸塊
第1圖為繪示根據第一實施例的半導體裝置之剖面結構的部分剖面圖；
第2圖為沿第1圖之線A-A的半導體裝置之部分底剖面圖；
第3圖為解釋製造半導體裝置之程序的流程圖；
第4至15圖為解釋製造半導體裝置之程序的圖；
第16圖為繪示其中堆疊第1圖所示之半導體裝置的堆疊型半導體裝置之剖面結構的剖面圖；以及
第17圖為繪示根據第一實施例的修改例之半導體裝置的剖面結構之部分剖面圖。
1．．．半導體裝置
11．．．半導體基板
11a．．．通槽
11b．．．第一表面
11c．．．第二表面
12．．．第二絕緣層
14．．．電極墊
15．．．開口部
17．．．鈍化膜
17a．．．開口
20．．．樹脂層
21．．．通孔
22．．．第三絕緣層
23．．．黏接層

Claims (20)

  1. 一種半導體裝置，包含：半導體基板，包括表面及其之相對表面，該半導體基板上設置互連層並且一通槽從該表面通過該半導體基板至該相對表面；第一絕緣層，其設置成填充該半導體基板的該通槽；電極墊，其配置在該第一絕緣層上並與包括在該互連層中之互連電連接；第二絕緣層，其係設置在該電極墊與該第一絕緣層之間；通孔，其配置成與該電極墊的下表面連通並通過該第一絕緣層及該第二絕緣層；以及導電材料，其設置在該通孔中並與該電極墊電連接。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該第二絕緣層具有比第一絕緣層更高的剛性。
  3. 如申請專利範圍第1項所述之半導體裝置，其中在該電極墊中形成小於該通孔的開口的開口。
  4. 如申請專利範圍第1項所述之半導體裝置，其中該第一絕緣層以光敏樹脂所製成。
  5. 如申請專利範圍第1項所述之半導體裝置，其中該第一絕緣層以樹脂材料所製成。
  6. 如申請專利範圍第1項所述之半導體裝置，其中該第二絕緣層覆蓋第一表面，其上設有該半導體基板的該電極墊並支撐該電極墊。
  7. 如申請專利範圍第6項所述之半導體裝置，其中該第二絕緣層為無機絕緣膜。
  8. 如申請專利範圍第1項所述之半導體裝置，其中該通槽具有比該半導體基板之厚度更大之寬度。
  9. 如申請專利範圍第1項所述之半導體裝置，進一步包含：第三絕緣層，其設置在該第一絕緣層與該第二絕緣層之間。
  10. 如申請專利範圍第9項所述之半導體裝置，其中該第三絕緣層亦設置在該第一絕緣層與該半導體基板之間。
  11. 如申請專利範圍第9項所述之半導體裝置，其中該第三絕緣層覆蓋與其上設置該半導體基板的該電極墊之該第一表面相對的第二表面。
  12. 如申請專利範圍第9項所述之半導體裝置，其中該第三絕緣層係設置在該半導體基板的該通槽之內壁及該第二絕緣層之底表面上。
  13. 如申請專利範圍第1項所述之半導體裝置，進一步包含：鈍化膜，其覆蓋該電極墊並設置在與該第二絕緣層相對之該半導體基板的表面上。
  14. 如申請專利範圍第13項所述之半導體裝置，其中在該鈍化膜中形成在平面視野中重疊該通孔之開口。
  15. 如申請專利範圍第1項所述之半導體裝置，其中設置該導電材料以填充該通孔。
  16. 如申請專利範圍第15項所述之半導體裝置，進一步包含：形成在該導電材料上之凸塊。
  17. 一種製造半導體裝置的方法，包含：在半導體基板之第一表面上形成第二絕緣層，其上形成互連層，該半導體基板包括表面及其之相對表面，在該第二絕緣層上設置與包括在該互連層中之互連一體成形的電極墊；形成通過該半導體基板的通槽，從該表面至設有該電極墊的該半導體基板之區域中的該相對表面；以第一絕緣層填充該通槽；形成通過該第一絕緣層及該第二絕緣層之通孔，以與該電極墊之下表面連通；以及以導電材料填充該通孔。
  18. 如申請專利範圍第17項所述之方法，其中在設置覆蓋該通槽的側表面部之第三絕緣層後設置該第一絕緣層以填充該通槽。
  19. 如申請專利範圍第17項所述之方法，進一步包含：設置覆蓋該電極墊之鈍化膜。
  20. 如申請專利範圍第19項所述之方法，其中在該鈍化膜中形成在平面視野中重疊該通孔之開 口。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012221998A (ja) 2011-04-04 2012-11-12 Toshiba Corp 半導体装置ならびにその製造方法
JP5548173B2 (ja) 2011-08-31 2014-07-16 株式会社東芝 半導体基板及びその製造方法
JP6544807B2 (ja) * 2014-06-03 2019-07-17 株式会社日本製鋼所 ゲッタリング層を持つ半導体の製造方法、半導体装置の製造方法および半導体装置

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02257643A (ja) * 1989-03-29 1990-10-18 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5380681A (en) * 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US6452117B2 (en) * 1999-08-26 2002-09-17 International Business Machines Corporation Method for filling high aspect ratio via holes in electronic substrates and the resulting holes
JP3606785B2 (ja) * 2000-05-26 2005-01-05 日本特殊陶業株式会社 配線基板の製造方法
TWI232560B (en) * 2002-04-23 2005-05-11 Sanyo Electric Co Semiconductor device and its manufacture
TWI229435B (en) * 2002-06-18 2005-03-11 Sanyo Electric Co Manufacture of semiconductor device
TWI239607B (en) * 2002-12-13 2005-09-11 Sanyo Electric Co Method for making a semiconductor device
TWI239581B (en) * 2003-01-16 2005-09-11 Casio Computer Co Ltd Semiconductor device and method of manufacturing the same
TWI229890B (en) * 2003-04-24 2005-03-21 Sanyo Electric Co Semiconductor device and method of manufacturing same
JP2005026405A (ja) 2003-07-01 2005-01-27 Sharp Corp 貫通電極構造およびその製造方法、半導体チップならびにマルチチップ半導体装置
KR100537892B1 (ko) * 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
JP3990347B2 (ja) * 2003-12-04 2007-10-10 ローム株式会社 半導体チップおよびその製造方法、ならびに半導体装置
JP4361826B2 (ja) * 2004-04-20 2009-11-11 新光電気工業株式会社 半導体装置
US7232754B2 (en) * 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
JP4271625B2 (ja) * 2004-06-30 2009-06-03 株式会社フジクラ 半導体パッケージ及びその製造方法
JP2006041512A (ja) 2004-07-27 2006-02-09 Samsung Electronics Co Ltd マルチチップパッケージ用集積回路チップの製造方法及びその方法により形成されたウエハ及びチップ
US7491582B2 (en) * 2004-08-31 2009-02-17 Seiko Epson Corporation Method for manufacturing semiconductor device and semiconductor device
JP2006080399A (ja) 2004-09-10 2006-03-23 Toshiba Corp 半導体装置および半導体装置の製造方法
TWI288448B (en) * 2004-09-10 2007-10-11 Toshiba Corp Semiconductor device and method of manufacturing the same
JP2006080400A (ja) 2004-09-10 2006-03-23 Toshiba Corp 半導体素子とその製造方法
JP4003780B2 (ja) * 2004-09-17 2007-11-07 カシオ計算機株式会社 半導体装置及びその製造方法
KR100676493B1 (ko) * 2004-10-08 2007-02-01 디엔제이 클럽 인코 재배선 기판을 이용한 웨이퍼 레벨 칩 스케일 패키지의제조 방법
JP4694305B2 (ja) 2005-08-16 2011-06-08 ルネサスエレクトロニクス株式会社 半導体ウエハの製造方法
US20100065318A1 (en) * 2006-11-28 2010-03-18 Kyocera Corporation Circuit board and semiconductor element mounted structure using the same
JP5301108B2 (ja) * 2007-04-20 2013-09-25 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置
TW200845339A (en) * 2007-05-07 2008-11-16 Sanyo Electric Co Semiconductor device and manufacturing method thereof
JP5361156B2 (ja) 2007-08-06 2013-12-04 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法
US8072079B2 (en) * 2008-03-27 2011-12-06 Stats Chippac, Ltd. Through hole vias at saw streets including protrusions or recesses for interconnection
JP2010212297A (ja) 2009-03-06 2010-09-24 Toshiba Corp 半導体装置および半導体装置の製造方法
JP2010232514A (ja) * 2009-03-27 2010-10-14 Kyocera Corp 樹脂基板の製造方法

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