JP2006032556A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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Abstract
【解決手段】 ウェハ21に接着剤25を介して配置された第1の半導体素子24と、ウェハ21上に形成され半導体素子24を収納する第1の素子収納部23が形成された第1の樹脂層22と、この第1の樹脂層22と半導体素子24とに渡って形成された第1の有機絶縁層27と、この第1の有機絶縁層27上に形成されると共に半導体素子24と接続される再配線層28とを有する構造体を少なくとも一つ以上積層してなる構成の半導体装置であって、第1の樹脂層22に間隙40を形成することにより、第1の樹脂層22を分割した構成とする。
【選択図】 図16
Description
この為、一つの半導体素子(チップ)に多くの機能を持たせる一方で、一つの支持基板上或いは容器(パッケージ)内に機能の異なる半導体チップを搭載し、当該半導体素子を組み合わせて多機能化を図ることが行われている。
一つは、近接して配置されて且つ互いに異なる機能を有する複数個の半導体チップ上に、当該複数個の半導体チップを共通に覆い且つ当該半導体チップ間を相互に接続する再配線層が配設され、当該再配線層上に電極ポスト(銅製)を形成されてなる半導体装置と、その製造方法を提供するものである。(特許文献1参照)。
この第1の樹脂層2は枠状にハターニングされて配設され、第1の素子収納部3が画定される。当該第1の素子収納部3には、図2に示されるように、第1の半導体素子4が各々収容される。当該第1の半導体素子4は、接着剤5を用いてウェハ1に固定される。
基板上に、半導体素子収納領域を画定して配設された枠体と、
前記半導体素子収納領域内に配設された半導体素子と、
前記半導体素子及び枠体を被覆して配設された有機絶縁層と、
前記有機絶縁層上に配設された配線層と
を具備し、
前記枠体は、その長さ方向において、間隙が配設されてなることを特徴とするものである。
請求項1記載の半導体装置において、
前記間隙部は、少なくとも前記半導体素子収納部の隅部に於ける枠体に設けられていることを特徴とするものである。
請求項1記載の半導体装置において、
前記枠体は、感光性樹脂材料よりなることを特徴とするものである。
基板上に、第1の半導体素子収納領域を画定して配設された第1の枠体と、
前記第1の半導体素子収納領域内に配設された第1の半導体素子と、
前記第1の半導体素子及び第1の枠体を被覆して配設された第1の有機絶縁層と、
前記第1の有機絶縁層上に配設された第1の配線層と、
前記第1の有機絶縁層上及び前記第1の配線層上に、第2の半導体素子収納領域を画定して配設された第2の枠体と、
前記第2の半導体素子収納領域内に配設された第2の半導体素子と、
前記第2の半導体素子及び前記第2の枠体を被覆して配設された第2の有機絶縁層と、
前記第2の有機絶縁層上に配設された第2の配線層と
を具備し、
前記第1の枠体及び前記第2の枠体は、その長さ方向において、間隙が配設されてなることを特徴とするものである。
請求項4項記載の半導体装置において、
前記第2の枠体(上方)の最大外形寸法が、前記第1の枠体(下方)の最大外形寸法よりも小であることを特徴とするものである。
請求項1及び請求項4に記載の半導体装置において、
前記有機絶縁層の幅方向の中央部に開口が形成されることを特徴とするものである。
請求項1及び請求項至4に記載の半導体装置において、
前記有機絶縁層には複数個の開口が並設され、その両端にはダミービアが配設されてなることを特徴とするものである。
請求項1及び請求項4に記載の半導体装置において、
前記半導体素子収納部の隅部に位置する枠体の外側角部は、面取りされてなることを特徴とするものである。
基板上に、半導体素子収納領域を画定する枠体を、その長さ方向において間隙を置いて配設する工程と、
前記枠体により画定された半導体素子収納領域内の前記基板上に半導体素子を配設する工程、
前記半導体素子及び前記枠体を覆って、有機絶縁層を形成する工程と、
前記有機絶縁層上に配線層を形成する工程とを具備することを特徴とするものである。
請求項9記載の半導体装置の製造方法において、
前記枠体を配設する際、少なくとも前記半導体素子収納部の隅部において間隙を設けることを特徴とするものである。
本実施例に於ける半導体装置20は、一つの基板上に、複数個の半導体素子(チップ)が積層されて搭載された構成を有する。本実施例にあっては、下層に配置される半導体素子が2個、上層に配置される半導体素子が1個である構成を例示する。勿論、かかる構成に限定されるものではない。
このように、第1の有機絶縁層27を、第1の枠体22を完全に覆うよう被着することにより、第1の有機絶縁層27を形成した際、第1の枠体22に形成された間隙40に起因して、第1の有機絶縁層27の上面に凹凸が発生することが防止される。
続いて、層間接続部(ビア)が形成された第1の有機絶縁層27上に、第1の再配線28を形成する。当該第1の再配線28は、銅(Cu)めっき法を用いて形成する。
かかる層間接続部(ビア)孔30及びダミービア孔41は、フォトプロセスにより、第2の枠体29の形成と同時に形成される。
かかるダミービア孔41aの配設によって、配列の両端部に在る層間接続部(ビア)孔30への応力も他の(内側に在る)層間接続部(ビア)孔30と同等なものとなり、当該配列の両端部に位置する層間接続部(ビア)孔30の変形が抑制・防止される。
当該第2の半導体素子32は、接着剤25により第1の有機絶縁層27上に固着される。
このような製造方法に於いて、第2の枠体29は、図21に示されるように、絶縁層が被着された状態にあっても、絶縁層が被着された第1の枠体22より小なる最大外形寸法をもって、第1の枠体22上に配設される。
更に、本発明にあっては、少なくとも前記第1の枠体22がその上面並びに側面を含めて、第1の有機絶縁層27により被覆されることにより、間隙40の設置に起因して当該第1の有機絶縁層27上面に凹凸が発生することが防止される。
このため、矢印Eにて示す如く、間隙40部に於いて、第1の有機絶縁層27の上面に窪み(凹部)が生じてしまう場合がある。
このように、枠体の外側のコーナーエッジ部を湾曲面とすることにより、被着される有機絶縁層の枠体に対する濡れ性(接合性)が向上し、よってコーナー部において枠体が有機絶縁層から露出することを防止することができる。かかる構成は、第1の枠体、第2の枠体それぞれに於いて適用することができる。
従って、接続信頼性の高い層間接続部(ビア)36を形成することが可能となり、もって半導体装置20の信頼性を高めることができる。
また、上記実施例にあっては、半導体素子を2層に積層した構成を掲げた。しかしながら、半導体素子の積層数は勿論これに限定されるものではない。
21 ウェハ
21A 基板
22 第1の樹脂層
23 第1の素子収納部
24 第1の半導体素子
27 第1の有機絶縁層
28 第1の再配線
29 第2の樹脂層
30 ビア孔
31 第2の素子収納部
32 第2の半導体素子
34 第2の有機絶縁層
35 第2の再配線
36 ビア
39 ボイド
40 間隙
41 ダミービア孔
42 感光性樹脂
45 スリット
51 薄層
Claims (10)
- 基板上に、半導体素子収納領域を画定して配設された枠体と、
前記半導体素子収納領域内に配設された半導体素子と、
前記半導体素子及び枠体を被覆して配設された有機絶縁層と、
前記有機絶縁層上に配設された配線層と
を具備し、
前記枠体は、その長さ方向において、間隙が配設されてなることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記間隙部は、少なくとも前記半導体素子収納部の隅部に於ける枠体に設けられていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記枠体は、感光性樹脂材料よりなることを特徴とする半導体装置。 - 基板上に、第1の半導体素子収納領域を画定して配設された第1の枠体と、
前記第1の半導体素子収納領域内に配設された第1の半導体素子と、
前記第1の半導体素子及び第1の枠体を被覆して配設された第1の有機絶縁層と、
前記第1の有機絶縁層上に配設された第1の配線層と、
前記第1の有機絶縁層上及び前記第1の配線層上に、第2の半導体素子収納領域を画定して配設された第2の枠体と、
前記第2の半導体素子収納領域内に配設された第2の半導体素子と、
前記第2の半導体素子及び前記第2の枠体を被覆して配設された第2の有機絶縁層と、
前記第2の有機絶縁層上に配設された第2の配線層と
を具備し、
前記第1の枠体及び前記第2の枠体は、その長さ方向において、間隙が配設されてなることを特徴とする半導体装置。 - 請求項4項記載の半導体装置において、
前記第2の枠体の最大外形寸法が、前記第1の枠体の最大外形寸法よりも小であることを特徴とする半導体装置。 - 請求項1及び請求項4に記載の半導体装置において、
前記有機絶縁層の幅方向の中央部に開口が形成されることを特徴とする半導体装置。 - 請求項1及び請求項至4に記載の半導体装置において、
前記有機絶縁層には複数個の開口が並設され、その両端にはダミービアが配設されてなることを特徴とする半導体装置。 - 請求項1及び請求項4に記載の半導体装置において、
前記半導体素子収納部の隅部に位置する枠体の外側角部は、面取りされてなることを特徴とする半導体装置。 - 基板上に、半導体素子収納領域を画定する枠体を、その長さ方向において間隙を置いて配設する工程と、
前記枠体により画定された半導体素子収納領域内の前記基板上に半導体素子を配設する工程、
前記半導体素子及び前記枠体を覆って、有機絶縁層を形成する工程と、
前記有機絶縁層上に配線層を形成する工程と
を具備することを特徴とする半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、
前記枠体を配設する際、少なくとも前記半導体素子収納部の隅部において間隙を設けることを特徴とする半導体装置の製造方法。
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TW093133994A TWI244747B (en) | 2004-07-14 | 2004-11-08 | Semiconductor device and method of manufacturing the same |
KR1020040091715A KR100605349B1 (ko) | 2004-07-14 | 2004-11-11 | 반도체 장치 및 그 제조 방법 |
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JP2012099648A (ja) * | 2010-11-02 | 2012-05-24 | Fujitsu Semiconductor Ltd | 半導体装置とその製造方法 |
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- 2004-11-05 US US10/981,557 patent/US7247950B2/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
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JP4265997B2 (ja) | 2009-05-20 |
TW200603374A (en) | 2006-01-16 |
KR100605349B1 (ko) | 2006-07-28 |
KR20060005969A (ko) | 2006-01-18 |
CN100375273C (zh) | 2008-03-12 |
TWI244747B (en) | 2005-12-01 |
US20060012017A1 (en) | 2006-01-19 |
US7247950B2 (en) | 2007-07-24 |
CN1722414A (zh) | 2006-01-18 |
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