JP6808460B2 - 半導体装置及びその製造方法 - Google Patents
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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Description
本発明の第一実施形態による半導体装置及びその製造方法について図1乃至図4を用いて説明する。
本発明の第2実施形態による半導体装置及びその製造方法について図5を用いて説明する。図5は、本実施形態による半導体装置の製造方法における貫通孔の内側面及びその周辺を拡大して示す概略断面図である。なお、上記第一実施形態による半導体装置及びその製造方法と同一の構成要素については同一の符号を付し説明を省略し又は簡略にする。
本発明は、上記実施形態に限らず、種々の変形が可能である。
例えば、上記実施形態では、絶縁部材40を構成する絶縁膜として第一の絶縁膜41及び第二の絶縁膜42の2層を形成する場合を例に説明したが、これに限定されるものではない。絶縁部材40を構成する絶縁膜として、2層のみならず3層以上の複数層の絶縁膜を形成してもよい。また、複数層の絶縁膜は、互いに同種の絶縁材料からなる絶縁膜であってもよいし、互いに異種の絶縁材料からなる絶縁膜であってもよい。
TR:半導体素子
CPL:コンタクトプラグ
10:素子分離部
20:層間絶縁層
30:配線層
PAD:電極部
40:絶縁部材
41:第一の絶縁膜
42:第二の絶縁膜
50:貫通電極
60:貫通孔
Claims (15)
- 互いに対向する第一面及び第二面を有し、前記第一面と前記第二面とを結ぶ内側面により囲まれた貫通孔が設けられた半導体基板と、
前記半導体基板の前記第一面の側に形成された半導体素子と、
前記半導体基板の前記第一面の側に形成された配線層と、
前記半導体基板の前記貫通孔の中に配され、前記半導体基板を貫通して前記配線層に接続された貫通電極と、
前記半導体基板の前記内側面と前記貫通電極との間に配された絶縁部材と、を有し、
前記絶縁部材は、前記半導体基板の前記内側面と前記貫通電極との間に配された第一の絶縁膜と、前記第一の絶縁膜と前記貫通電極との間に配された第二の絶縁膜と、を含み、
前記絶縁部材が有するクラックが前記第一の絶縁膜にあり、前記クラックは前記第二の絶縁膜と前記内側面の間に位置し、
前記内側面は、前記貫通孔の深さ方向において凸部と凹部とが交互に繰り返された形状を有し、
前記第二の絶縁膜は前記第一の絶縁膜の側に、前記内側面の前記凸部に対応した凹部を有することを特徴とする半導体装置。 - 前記クラックは、前記内側面の前記凸部と前記第二の絶縁膜の前記凹部との間に位置することを特徴とする請求項1記載の半導体装置。
- 前記第一の絶縁膜は前記第二の絶縁膜の側に、前記内側面の前記凹部に対応した凹部を有することを特徴とする請求項2記載の半導体装置。
- 前記絶縁部材が有する別のクラックが前記第二の絶縁膜にあり、前記別のクラックは、前記貫通電極と前記第一の絶縁膜の前記凹部との間に位置することを特徴とする請求項3記載の半導体装置。
- 前記第二の絶縁膜は前記第一の絶縁膜よりも厚いことを特徴とする請求項4記載の半導体装置。
- 前記内側面の前記凸部の位置と、前記第一の絶縁膜の前記第二の絶縁膜の側の前記凹部の位置とが、前記貫通孔の深さ方向において互いに異なっていることを特徴とする請求項3乃至5のいずれか1項に記載の半導体装置。
- 前記絶縁部材が有する別のクラックが前記第二の絶縁膜にあり、前記第一の絶縁膜の前記クラックの位置と、前記第二の絶縁膜の前記別のクラックの位置とが、前記貫通孔の深さ方向において互いに異なっていることを特徴とする請求項6記載の半導体装置。
- 前記第一の絶縁膜が、酸化シリコン、窒化シリコン及び酸窒化シリコンのうちのいずれかからなり、
前記第二の絶縁膜が、酸化シリコン、窒化シリコン及び酸窒化シリコンのうちのいずれかからなることを特徴とする請求項1乃至7のいずれか1項に記載の半導体装置。 - 前記半導体基板の前記第一面の側に設けられた支持基板をさらに有する請求項1乃至8のいずれか1項に記載の半導体装置。
- 前記半導体装置は固体撮像装置であることを特徴とする請求項1乃至9のいずれか1項に記載の半導体装置。
- 半導体基板の第一面の側に半導体素子を形成する工程と、
前記半導体基板の前記第一面の側に、層間絶縁層を介して配線層を形成する工程と、
前記半導体基板の前記第一面に対向する第二面の側から前記半導体基板及び前記層間絶縁層を開口して、前記半導体基板及び前記層間絶縁層に、前記配線層に達する貫通孔を形成する工程と、
前記貫通孔の内側面に、第一の絶縁膜及び第二の絶縁膜を順に積層する工程と、
前記第一の絶縁膜及び前記第二の絶縁膜が積層された前記貫通孔の内部に導電材料を埋め込んで、前記導電材料からなる貫通電極を形成する工程とを有し、
前記第一の絶縁膜及び前記第二の絶縁膜を順に積層する工程が、前記第一の絶縁膜を形成した後、前記第二の絶縁膜を形成する前に、前記半導体基板を加熱する工程を含み、
前記半導体基板を加熱する工程における加熱速度が、前記第一の絶縁膜及び前記第二の絶縁膜の成膜時における加熱速度よりも大きいことを特徴とする半導体装置の製造方法。 - 前記半導体基板を加熱する工程における熱処理の温度が、前記第一の絶縁膜及び前記第二の絶縁膜の成膜温度よりも高いことを特徴とする請求項11記載の半導体装置の製造方法。
- 前記貫通孔を形成する工程が、
前記半導体基板を前記貫通孔が貫通するように前記半導体基板を開口する工程と、
前記第一の絶縁膜及び前記第二の絶縁膜を形成する工程の後に、前記半導体基板を貫通した前記貫通孔が前記配線層に達するように前記層間絶縁層を開口する工程とを含むことを特徴とする請求項11又は12に記載の半導体装置の製造方法。 - 前記第一の絶縁膜及び前記第二の絶縁膜を形成する工程が、CVD法によりそれぞれ前記第一の絶縁膜及び前記第二の絶縁膜を形成することを特徴とする請求項11乃至13のいずれか1項に記載の半導体装置の製造方法。
- 前記CVD法が、プラズマCVD法であることを特徴とする請求項14記載の半導体装置の製造方法。
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