TWI389277B - 藉由一附有凹槽之環狀孔的晶粒堆疊 - Google Patents

藉由一附有凹槽之環狀孔的晶粒堆疊 Download PDF

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Publication number
TWI389277B
TWI389277B TW098113334A TW98113334A TWI389277B TW I389277 B TWI389277 B TW I389277B TW 098113334 A TW098113334 A TW 098113334A TW 98113334 A TW98113334 A TW 98113334A TW I389277 B TWI389277 B TW I389277B
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Taiwan
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conductive
die
substrate
annular
forming
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TW098113334A
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English (en)
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TW201001647A (en
Inventor
Dave Pratt
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Micron Technology Inc
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Description

藉由一附有凹槽之環狀孔的晶粒堆疊
實例實施例大體而言係關於電子裝置及系統之積體電路製造的技術領域。
隨著微電子學中之焦點正逐漸改變以包括對封裝之更多強調，可藉由使用系統級封裝(SiP)方法而在封裝中獲得附加價值。對於功能整合中之發展趨勢而言，SiP方法可被認為係主要可行的解決方案。SiP方法包括將若干晶粒置放至一封裝中，該等晶粒被並排置放或置放於彼此之頂部。然而，小型化趨勢可或多或少地減小對並排之晶粒的使用。因此，額外方法可增強該趨勢以最小化晶粒面積，同時提供高速度及可靠之介面。
在隨附圖式之諸圖中借助於實例且並未限制地說明了一些實施例。
將描述用於借助於具有凹導電槽之環狀孔及所形成之導電柱來進行晶粒堆疊之實例結構及方法的實施例。在以下描述中，出於解釋之目的而陳述了大量具有實例特定細節之實例以提供對實例實施例之透徹理解。然而，熟習此項技術者將明白，可在無此等實例特定細節之情況下實踐本實例。
實例實施例可包括將一導電環狀TSV(在此項技術中，TSV係直通矽孔之縮寫字，下文中將使用其來表示直通基板孔)形成於基板之底表面上，該導電環狀TSV經組態以具有一由環狀孔之內壁包圍的凹部分。該方法可包括形成一用以覆蓋環狀孔並與環狀孔排齊之凹部分的導電層以形成凹導電槽。該方法可進一步包括形成一伸出環狀孔之平坦末端部分的導電圓柱形柱(例如，在位於鄰近堆疊晶粒之前側上的結合襯墊結構的頂部)。
圖1係截面圖，其說明晶粒堆疊100之一部分的一實例實施例，該等晶粒藉由使用具有凹導電槽之環狀孔及導電柱而連接。堆疊100可包括：底部晶粒110，其包括導電凹槽115；一或多個中間晶粒120，其包括導電凹槽115以及導電柱125；及頂部晶粒130，其包括一形成於結合襯墊135上之導電柱125。導電柱125及導電凹槽115可經組態以大小匹配且能夠配合在一起而在鄰近晶粒之間(例如，底部晶粒110與中間晶粒120之間、中間晶粒120彼此之間或中間晶粒120與頂部晶粒130之間)形成穩定之導電耦接。在一實例實施例中，堆疊可由底部晶粒110與頂部晶粒130組成。
在一些實例實施例中，晶粒110、120或130可包括半導體晶圓。該等半導體晶圓可包括(但不限於)矽。該等晶粒亦可包括電子裝置(例如，DRAM、SDRAM、PCRAM、快閃記憶體、成像器等)。導電柱可由銅製造而成且導電凹槽可由凸塊下材料(UBM)(例如，鎳/鈀/金合金)製成。亦可將其他導電材料用於製造導電柱或導電凹槽。
本申請案中所呈現之晶粒堆疊方法提供優於現有技術之若干優勢。舉例而言，導電凹槽115及導電柱125可提供聯鎖特徵，當將堆疊晶粒自晶粒堆疊製程移至隨後之製程(例如，回焊、下部填充等)時，該聯鎖特徵可提高對準穩定性。該方法之另一優勢可包括達成由凹槽115及導電柱125可能實現之接近零結合線晶粒堆疊。
圖2係截面圖，其說明一底部晶粒之一部分200的一實例實施例，該底部晶粒包括一具有凹導電槽210之環狀孔。部分200可為圖1之底部晶粒110之一部分。部分200可包括：基板206(例如，矽晶圓)；導電環狀TSV 230；及凹導電(例如，UBM)層210，其形成UBM槽。在實例實施例中，部分200亦可包括背側鈍化部204及結合襯墊208。UBM槽可藉由環狀孔之內壁而形成於基板206之底表面上。環狀TSV 230可包括平坦末端部分235。環狀TSV 230及平坦末端部分235可包括銅。基板之頂表面可為底部晶粒110之作用表面(包括積體電子裝置)。
圖3係截面圖，其說明一中間晶粒之一部分300的一實例實施例，該中間晶粒包括一具有凹導電槽210的環狀孔及導電柱310。部分300可為圖1之中間晶粒120的一部分。部分300可包括基板206、導電環狀TSV 230、UBM槽、背側鈍化部204及結合襯墊208。另外，部分300可包括一形成於平坦末端部分235上之導電(例如，銅)圓柱形柱310(下文中亦稱作導電柱)。在實例實施例中，導電柱310可相對於基板之平面而為垂直的。導電柱310可經設定大小以配合至UBM槽中，因此當藉由將導電柱定位於UBM槽中來堆疊時致能底部晶粒110與中間晶粒120之間的導電耦接。在一實例實施例中，導電柱310可與凹導電槽210對準。
圖4係截面圖，其說明在形成環狀開口420之後一處理中晶粒400之一實例實施例。在實例實施例中，可藉由自基板之環形區域移除(例如，蝕刻、使用乾式蝕刻、濕式蝕刻等)基板材料(例如，矽)來形成環狀開口420。可使用塗佈於基板410之頂表面(包括結合襯墊層440)上之光阻層430來圖案化環形區域(見圖5中之環形區域520)。可使用微影來圖案化光阻而具有環形開口。光阻可在TSV蝕刻製程期間充當臨時蝕刻光罩。結合襯墊層440可已藉由將導電材料(例如，銅)電鍍於基板410上而形成。基板之TSV蝕刻可形成具有大約50-150微米之典型深度的環狀開口420。
圖5中描繪圖4之處理中晶粒的俯視圖，在圖5中，展示了覆蓋基板410之頂表面的光阻層430。圖5中亦展示了除去光阻層430之環形區域520。
圖6係圖4之處理中晶粒在將鈍化層610形成於環狀開口420之側壁上之後的截面圖。根據實例實施例，可藉由使用(例如)脈衝沈積層(PDL)製程而將鈍化材料(例如，氧化鋁)沈積於環狀開口之表面(側壁及底部區域620)上而形成鈍化層610。在下一步驟中，可自所有水平表面移除鈍化層610。可藉由(例如)間隔物蝕刻來執行自底部區域620及頂表面移除鈍化層610，該間隔物蝕刻可優先自水平表面移除沈積物。
可如圖7中所示用導電材料來填充環狀開口以形成垂直部分730及平坦末端部分720。側壁鈍化層610可防止在建構之封裝或裝置的操作期間電流經由側壁而自金屬孔洩漏至基板410。在一實例實施例中，環狀開口之填充可以沈積導電材料(例如，銅)之薄種子層開始，其可促進形成金屬孔之下一步驟。
可藉由將導電材料(例如，銅)沈積(例如，電鍍)於所要區域上而執行金屬孔之形成。所要區域可包括結合襯墊及環狀開口之表面區域。可經由光微影圖案化製程來界定所要區域。電鍍銅可形成實心金屬孔。在形成實心金屬孔之後，可自基板表面移除(例如，剝離)種子層及光阻層750(在光微影圖案化製程中被沈積)。在一實例實施例中，可在形成種子層之前沈積障壁層。障壁層可防止電鍍銅擴散至基板中。亦可自未藉由電鍍製程覆蓋之區域移除障壁層。
圖8係圖7之處理中晶粒在形成凹導電槽840之後的截面圖。在將金屬孔形成於基板之頂表面上之後，將凹導電槽840形成於背側表面上。達成凹導電槽840可涉及使用(例如)背側研磨製程而自背表面(與平坦末端部分720相反)使基板變薄。為在背側研磨製程期間使基板免於任何損壞，可使用黏接層820而將臨時載體810(例如，玻璃或矽晶圓)黏接至基板之頂表面。
背側研磨可使基板410具有通常50-150微米之厚度。背側研磨可繼續直至基板材料大體上與金屬孔之底部分齊平。然而，為形成凹導電槽840，必須暴露具有環狀金屬孔之高度的一些部分(例如，10-15微米)。此可藉由(例如)使用整體濕式蝕刻或乾式蝕刻來選擇性地移除基板材料以相對於金屬孔而產生基板材料凹區並形成由環狀金屬孔之內側壁包圍之開口而達成。
在形成凹導電槽之前的下一步驟可為將背側鈍化層830形成於整個凹表面上(除將形成凹導電槽之區域之外)。此區域由數字參考850描繪，在該區域中需要暴露金屬孔(藉由移除環狀TSV之側壁鈍化部)以便使凹導電槽840與金屬孔成導電接觸。在一實例實施例中，可藉由使用(例如)可經由微影製程來圖案化之光敏性旋塗式介電聚合物層來執行將背側鈍化層830沈積於所選區域上。
可藉由將導電材料(例如，UBM)選擇性地沈積於未由背側鈍化層830覆蓋之區域上而執行凹導電槽840之形成。在此階段所處理之晶粒可包括由導電金屬孔及UBM槽(亦即，凹導電槽840)形成之TSV且其可用作底部晶粒。
圖9係圖7之處理中晶粒在形成一伸出孔之平坦末端部分的圓柱形導電柱920之後的截面圖。如圖1中所示之中間晶粒120可包括圖9中所示之具有參考數字920的導電柱。在一實例實施例中，可在形成金屬孔之後達成導電柱920之形成。形成導電柱920之過程可先將厚光罩層910首先形成於基板之頂表面(包括環狀孔之平坦末端部分)上，且接著自其上將形成有導電柱920之區域選擇性地移除厚光罩層910。光罩層910之厚度可等於導電柱920之高度。可選擇導電柱920之高度使得導電柱可配合至UBM槽840中。在一實例實施例中，導電柱920可與金屬孔對準。
在自被考慮用於形成導電柱920之區域(例如，小於環狀孔內部之中心部分區域的區域)選擇性地移除光罩層910之後，可藉由將導電層(例如，銅、焊接材料等)選擇性地沈積(例如，電鍍)於藉由選擇性地移除光罩層910所形成之洞的內部來形成導電柱920。在下一步驟中，可選擇性地移除光罩層910以暴露導電柱920。自圖9之處理中晶粒形成中間晶粒可能需要在圖8之論述下所明白表示之過程。
圖10係高階流程圖，其說明在一實例實施例中用於形成具有凹導電槽之環狀孔的方法1000。該方法1000在操作1010處開始，在操作1010中可將一導電環狀孔形成於基板410之底表面上，該導電環狀孔經組態以形成由環狀孔730之內壁包圍之凹部分。該方法亦可包括在操作1020處形成一用以覆蓋凹部分之導電層以組態凹導電槽840(如圖8中所示)。
圖11係高階流程圖，其說明在一實例實施例中用於使用具有凹導電槽之環狀孔及導電柱來堆疊晶粒的方法1100。該方法1100可在操作1102處開始，在操作1102中可組態第一晶粒110(見圖1)。該組態可包括形成結構組件，其包括：A.形成一環狀直通基板孔(TSV)，其包括形成一覆蓋基板206之第一表面之一部分的平坦末端部分235，其中環狀TSV之部分自基板206之第二表面延伸；B.形成一非導電層(例如，背側鈍化層204)，其用以覆蓋基板之第二表面之包圍環狀TSV的部分及使一在環狀TSV內部之凹部分未覆蓋；及C.將一凸塊下層210沈積於凹部分上以將UBM槽組態於第一晶粒110之底表面上，其中第一晶粒110之底表面與基板206之第二表面相同。
在操作1104處，可組態第二晶粒(例如，圖1之中間晶粒120)。第二晶粒之組態可包括形成大體上與上文關於第一晶粒所論述之結構組件相同的結構組件(除進一步將伸出平坦末端部分235之導電圓柱形柱310安置於第二晶粒之頂表面上之外)。在一實例實施例中，導電柱310可經設定大小以配合至由第一晶粒之UBM層210所形成的凹導電槽中。
圖12係流程圖，其說明在一實例實施例中用於形成具有凹導電槽之環狀孔的方法1200。該方法在操作1210處開始，在操作1210中自基板410之第一表面來蝕刻基板410以形成環狀開口420。在操作1220處，可將第一鈍化層610沈積於環狀開口420之側壁上。在操作1230處，可用第一導電材料(例如，銅)來填充環狀開口420使得形成金屬孔730。該金屬孔730可包括平坦末端部分720，該平坦末端部分720覆蓋基板410之第一表面(例如，頂面)之一部分且在第一表面上自環狀開口420之外邊緣向外延伸。
在操作1240處，可藉由自基板410之第二表面(包括由環狀孔730包圍之區域)將基板材料移除(例如，背側研磨及蝕刻)達到金屬孔730之一部分自基板410之第二表面伸出的程度而使基板410變薄。可自金屬孔暴露端之內壁及內部分850移除(例如，蝕刻掉)第一鈍化層610(操作1250)。在操作1260處，可將第二鈍化層830沈積於基板410之第二表面之包圍金屬孔730暴露端之內部分的一部分上使得可形成由金屬孔730之內壁包圍之凹區域。在操作1270處，可將一層第二導電材料(例如，UBM)塗佈於凹區域之表面上以形成導電UBM槽。
圖13係截面圖，其說明一形成晶粒之一部分的結構1300的一實例實施例，該晶粒包括一具有凹導電槽1350及圓柱形柱1330之孔1310。可將孔1310形成為實心圓柱形孔1310，其包括與結合襯墊1360及柱1330成導電接觸之平坦末端部分1320。孔1310可包括一由形成UBM槽1340之UBM層1350覆蓋的凹部分。背側鈍化層1370可經圖案化並用以充當用於進入至實心圓柱形孔1310中之凹部分的蝕刻光罩。亦可將背側鈍化層1370用作絕緣層。在一實例實施例中，柱1330可經設定大小以配合至一大體上類似於UBM槽1340之UBM槽中。在實例實施例中，基板410可為一包括電子電路之晶粒的部分。該等電子電路可包括DRAM、SDRAM、PCRAM、快閃記憶體、成像器等。
圖14係方塊圖，其說明系統1400之一實例實施例，該系統1400包括藉由圖11之方法所形成之電子封裝。根據實例實施例，系統1400可表示大型(main-frame)電腦、桌上型或膝上型電腦、個人數位助理(PDA)、蜂巢式電話等。系統1400可包括耦接至匯流排1450的一或多個處理器1410、一或多個RAM 1420、若干輸入/輸出裝置1430及一或多個儲存裝置1440。在一實例實施例中，RAM 1420可包括SRAM、DRAM、PCRAM或快閃記憶體。儲存裝置1440可包括硬碟、光碟(CD)或數位影音光碟(DVD)。在實例實施例中，處理器1410或RAM 1420可包括由晶粒組成之電子封裝，該等晶粒借助於如圖1中所示之具有凹導電槽的環狀孔而堆疊。
已描述了用於借助於具有凹導電槽之環狀孔及導電柱進行晶粒堆疊的晶粒槽結構及方法。儘管已描述了特定實施例，但將為明顯的係，可對此等實施例進行各種修改及改變。因此，將以說明意義而非限制意義來看待說明書及圖式。
提供揭示案之摘要以遵守需要允許讀者快速確定技術揭示案之性質之摘要的37 C.F.R.§1.72(b)。提交其而理解其將不用以解釋或限制申請專利範圍。另外，在上述實施方式中，可見，出於簡化揭示案之目的而在單個實施例中將各種特徵聚集在一起。此揭示案方法將不解釋為限制申請專利範圍。因此，以下申請專利範圍藉此併入實施方式中，其中每一請求項作為獨立實施例而具獨立性。
100．．．堆疊
110．．．底部晶粒
115．．．導電凹槽
120．．．中間晶粒
125．．．導電柱
130．．．頂部晶粒
135．．．結合襯墊
200．．．底部晶粒之部分
204．．．背側鈍化部
206．．．基板
208．．．結合襯墊
210．．．凹導電槽
230．．．導電環狀TSV
235．．．平坦末端部分
300．．．中間晶粒之部分
310．．．導電柱
400．．．處理中晶粒
410．．．基板
420．．．環狀開口
430．．．光阻層
440．．．結合襯墊層
520．．．環形區域
610．．．鈍化層
620．．．底部區域
720．．．平坦末端部分
730．．．環狀孔
750．．．光阻層
810．．．臨時載體
820．．．黏接層
830．．．背側鈍化層
840．．．凹導電槽
850．．．內部分
910．．．厚光罩層
920．．．導電柱
1310．．．孔
1320．．．平坦末端部分
1330．．．圓柱形柱
1340．．．UBM槽
1350．．．凹導電槽
1360．．．結合襯墊
1370．．．背側鈍化層
1400．．．系統
1410．．．處理器
1420．．．RAM
1430．．．輸入/輸出裝置
1440．．．儲存裝置
1450．．．匯流排
圖1係截面圖，其說明一晶粒堆疊之一部分的一實例實施例，該等晶粒藉由使用具有凹導電槽之環狀孔及導電柱而連接；圖2係截面圖，其說明一底部晶粒之一部分的一實例實施例，該底部晶粒包括一具有凹導電槽之環狀孔；圖3係截面圖，其說明一中間晶粒之一部分的一實例實施例，該中間晶粒包括一具有凹導電槽之環狀孔及導電柱；圖4係截面圖，其說明一處理中晶粒在形成環狀開口之後的一實例實施例；圖5係圖4之處理中晶粒的俯視圖；圖6係圖4之處理中晶粒在將鈍化層形成於環狀開口之側壁上之後的截面圖；圖7係圖6之處理中晶粒在形成導電孔及平坦末端部分之後的截面圖；圖8係圖7之處理中晶粒在形成凹導電槽之後的截面圖；圖9係圖8之處理中晶粒在將圓柱形導電柱形成於孔之平坦末端部分上之後的截面圖；圖10係高階流程圖，其說明在一實例實施例中用於形成具有凹導電槽之環狀孔的方法；圖11係高階流程圖，其說明在一實例實施例中用於使用具有凹導電槽之環狀孔及導電柱來堆疊晶粒的方法；圖12係流程圖，其說明在一實例實施例中用於形成具有凹導電槽之環狀孔的方法；及圖13係截面圖，其說明一形成晶粒之一部分的結構的一實例實施例，該晶粒包括一具有凹導電槽及圓柱形柱之孔；及圖14係方塊圖，其說明一系統之一實例實施例，該系統包括藉由圖11之方法而形成之電子封裝。
100．．．堆疊
110．．．底部晶粒
115．．．導電凹槽
120．．．中間晶粒
125．．．導電柱
130．．．頂部晶粒
135．．．結合襯墊

Claims (33)

  1. 一種用在晶粒堆疊之設備，其包含：一基板，其包括一在該基板之一底表面上的導電環狀孔，該導電環狀孔具有一由該環狀孔之內壁包圍之凹部分；一導電層，其覆蓋該凹部分而經組態為一導電槽。
  2. 如請求項1之設備，其中該基板包括矽，該導電環狀孔包括銅，且該導電層包括凸塊下材料。
  3. 如請求項1之設備，其中該環狀孔包括一覆蓋該基板之一頂表面之一部分的平坦末端部分。
  4. 如請求項3之設備，其進一步包括一自該環狀孔之該平坦末端部分伸出的導電圓柱形柱。
  5. 如請求項4之設備，其中該導電圓柱形柱相對於該基板之一平面而為垂直的。
  6. 如請求項1之設備，其中該基板係一晶粒之一部分且該基板之該頂表面係該晶粒之一作用表面。
  7. 如請求項6之設備，其中該晶粒之該作用表面包括積體電子裝置。
  8. 一種用在晶粒堆疊之方法，其包含：將一導電環狀孔形成於一基板之一底表面上，該導電環狀孔具有一由該環狀孔之內壁包圍之凹部分；及形成一覆蓋該凹部分之導電層以形成一導電槽。
  9. 如請求項8之方法，其中該導電環狀孔之該形成包括形成一覆蓋該基板之一頂表面之一部分的平坦末端部分。
  10. 如請求項9之方法，其進一步包括將一自該基板伸出之導電圓柱形柱形成於該環狀孔之該平坦末端部分上。
  11. 一種電子封裝，其包含：一第一晶粒，其包括：一基板，其具有一環狀直通基板孔(TSV)，該環狀TSV包括一覆蓋該基板之一第一表面之一部分的平坦末端部分；一非導電層，其覆蓋該基板之一第二表面之包圍該環狀TSV的部分；及一在該第二表面處安置於該環狀TSV中之一凹部分中的凸塊下層，該凸塊下層被組態為一在該第一晶粒之一底表面上的導電槽，其中該第一晶粒之該底表面為該基板之該第二表面；及一在該電子封裝中相對於該第一晶粒配置之第二晶粒，該第二晶粒具有一形成於該第二晶粒之一頂表面上的導電圓柱形柱，其中該導電圓柱形柱經設定大小以配合至該第一晶粒之該導電槽中。
  12. 如請求項11之電子封裝，其進一步包括一安置於該基板與該環狀TSV之該平坦末端部分之間的導電襯墊。
  13. 如請求項11之電子封裝，其中該基板包括矽。
  14. 如請求項11之電子封裝，其中該第一晶粒或該第二晶粒中之至少一者包括積體電子裝置。
  15. 如請求項11之電子封裝，其中該環狀TSV包括銅。
  16. 如請求項11之電子封裝，其中該非導電層包括一背側鈍 化層。
  17. 如請求項11之電子封裝，其中該第一晶粒及該第二晶粒經堆疊使得該第二晶粒之該導電圓柱形柱配合至該第一晶粒之該導電槽中，從而在該第二晶粒之該導電圓柱形柱與該第一晶粒之該導電槽之間形成一導電連接。
  18. 如請求項17之電子封裝，其進一步包括一頂部晶粒，其中該頂部晶粒包括一金屬柱，該金屬柱經設定大小以配合至該第二晶粒之一環狀孔中的一導電槽中使得該金屬柱安置於該第二晶粒之該導電槽中以在該金屬柱與該第二晶粒之該導電槽之間形成一導電連接。
  19. 如請求項17之電子封裝，該電子封裝包括一或多個額外晶粒，該一或多個額外晶粒藉由該等額外晶粒中之一者的一安置於該第二晶粒之一環狀孔中之一導電槽中的導電圓柱形柱而連接至該堆疊。
  20. 一種用於製造一電子封裝之方法，其包含：組態一第一晶粒，其包括：形成一環狀直通基板孔(TSV)，該環狀TSV具有一覆蓋一基板之一第一表面的一部分的平坦末端部分且具有該環狀TSV之暴露於該基板之一第二表面處的部分；形成一非導電層，該非導電層覆蓋該基板之該第二表面之包圍該環狀TSV的部分且在該第二表面處使一在該環狀TSV內部之凹部分未覆蓋；及將一凸塊下層沈積於該凹部分上，從而將一導電槽 形成於該第一晶粒之一底表面上，該第一晶粒之該底表面為該基板之該第二表面；及在該電子封裝中相對於該第一晶粒而組態一第二晶粒，其包括將一導電圓柱形柱形成於該第二晶粒之一頂表面上使得該導電圓柱形柱經設定大小以配合至該第一晶粒之該導電槽中。
  21. 如請求項20之方法，其進一步包括將該第一晶粒及該第二晶粒組態於一堆疊中使得該第二晶粒之該導電圓柱形柱配合至該第一晶粒之該導電槽中，以在該第二晶粒之該導電圓柱形柱與該第一晶粒之該導電槽之間形成一導電連接。
  22. 如請求項21之方法，其進一步包括將一頂部晶粒安置於該第一晶粒與該第二晶粒之該堆疊上，使得該頂部晶粒之一金屬柱安置於該第二晶粒之一環狀孔中的一導電槽中以在該金屬柱與該第二晶粒之該導電槽之間形成一導電連接。
  23. 如請求項21之方法，其中該方法包括將一或多個額外晶粒連接至該堆疊，此係藉由將該等額外晶粒中之一者之一導電圓柱形柱安置於該第二晶粒之一環狀孔中之一導電槽中。
  24. 一種用於製造一電子封裝之方法，該方法包含：自一基板之一第一表面蝕刻該基板以形成一環狀開口；將一第一鈍化層形成於該環狀開口之側壁上； 用一第一導電材料填充該環狀開口使得形成一金屬孔，該金屬孔包括一平坦末端部分，該平坦末端部分覆蓋該基板之該第一表面之一部分且在該第一表面上自該環狀開口之外邊緣向外延伸；使該基板變薄，此係藉由自該基板之一包括一由該金屬孔包圍之區域的第二表面將一基板材料移除達到該金屬孔之一部分自該變薄之基板之該第二表面伸出的一程度；在該變薄之基板之該第二表面處自該金屬孔之暴露端之內壁及一內部分移除該第一鈍化層；將一第二鈍化層形成於該基板之該第二表面之包圍該金屬孔之該等暴露端之該內部分的一部分上使得形成一由該金屬孔之內壁包圍之凹區域；及將一層第二導電材料塗佈於該凹區域上以形成一導電槽。
  25. 如請求項24之方法，其進一步包括形成一導電圓柱形柱，該導電圓柱形柱自該基板之該第一表面垂直伸出且經設定大小以配合至該導電槽中。
  26. 如請求項25之方法，其中該導電圓柱形柱之該形成包括將該柱形成於該金屬孔之該平坦末端部分上。
  27. 如請求項24之方法，其中該基板之蝕刻係在該基板之該第一表面之一用一導電襯墊塗佈的區域上執行，其中該環狀開口與該導電襯墊同心。
  28. 如請求項24之方法，其中將該第一鈍化層形成於該環狀 開口之側壁上包括將該第一鈍化層形成於該環狀開口之全部表面上且接著自該環狀開口之一底表面移除該第一鈍化層。
  29. 如請求項24之方法，其中該第一導電材料包括銅，該第二導電材料包括一凸塊下材料，且該基板材料包括矽。
  30. 一種用在晶粒堆疊之系統，其包含：一處理器，其包括一藉由堆疊複數個晶粒而形成之電子封裝，其中該複數個晶粒中之至少一個晶粒包括一形成於一環狀孔上之凹導電槽；及一記憶體，其包括至少一個隨機存取記憶體封裝。
  31. 如請求項30之系統，其中該複數個晶粒中之至少一個晶粒包括一經設定大小以配合至該凹導電槽中之導電圓柱形柱。
  32. 如請求項30之系統，其中該至少一個隨機存取記憶體封裝係藉由堆疊複數個晶粒而形成的，其中該複數個晶粒中之至少一個晶粒包括一形成於一環狀孔上之凹導電槽。
  33. 如請求項30之系統，其中該複數個晶粒中之至少一個晶粒包括一經設定大小以配合至該凹導電槽中之導電圓柱形柱。
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