TWI447850B - 直通基材穿孔結構及其製造方法 - Google Patents
直通基材穿孔結構及其製造方法 Download PDFInfo
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Description
本發明係關於一種半導體技術,尤其是關於一種用於堆疊封裝的直通基材穿孔結構及其製造方法。
積體電路封裝技術持續的發展以達到微型化及設置可靠度的需求。習知中堆疊封裝係為一具有至少二晶片或二封裝體的垂直立式結構,其中晶片或封裝體是以一者堆疊於另一者之上而設置。以一記憶體裝置為例,藉著使用一堆疊結構,即可經由半導體整合製程製造出具有兩倍以上的記憶體容量。
堆疊封裝不僅可增加記憶體的容量,還可增加設置積集度以及設置面積的利用效率。目前已有使用直通矽晶穿孔的堆疊封裝結構,其直通矽晶穿孔形成於晶片中,因此晶片可經由直通矽晶穿孔彼此物理和電性連接。
直通矽晶穿孔的製造,一般以一導電材料填入通孔中,且導電材料穿過矽基底,以連接其他的直通矽晶穿孔及接合層的導體。
舉例而言,垂直孔洞係定義於晶圓級的各個晶片的一預定部分。絕緣層接著形成於垂直孔洞的表面上。藉著形成一晶種金屬層於絕緣層上,金屬可藉由電鍍製程填入垂直孔洞中,並形成一直通矽晶穿孔。其後,利用晶背研磨暴露直通矽晶穿孔。在切割晶圓並將其分成多個晶片之後,以一個或一個以上的直通矽晶穿孔,將至少兩個晶片垂直堆疊於其中之一基底上,其中晶片係以一個堆疊於另一個上方設置。最後,將堆疊晶片及基底的上表面模封,並且設置錫球於基底的下表面。
然而,當以傳統化學氣相沉積製程填入10微米以下之通孔時,直通矽晶穿孔製程面臨挑戰。此外,當沉積材料層於通孔時,大尺寸通孔亦面臨低產出的問題。因此,產業上需要一改良的直通矽晶穿孔結構及製程,以解決上述問題。
本發明係提供一種直通基材穿孔及其製造方法,其可改善利用直通矽晶穿孔製造堆疊封時的重疊精度。
本發明提出一種直通基材穿孔結構的製造方法,包含:提供一基底,其上設有一層間介電層;蝕刻一第一通孔,於層間介電層以及半導體基底中;形成一側壁子,於第一通孔的側壁;經由第一通孔蝕刻半導體基底,以形成一第二通孔;拓寬第二通孔,以形成一瓶狀通孔;形成一絕緣層,於瓶狀通孔底部的內壁;沉積一第一導電層於瓶狀通孔中,其中第一導電層定義瓶狀通孔底部的一腔體;形成一連接墊於半導體基底的正側,其中連接墊與第一導電層電連接;研磨半導體基底的背側以暴露出腔體;以及由半導體基底的背側填入一第二導電層於腔體中。
本發明亦提出一種直通基材穿孔結構的製造方法,包含:提供一基底,其上設有一層間介電層;蝕刻多個第一通孔於層間介電層以及半導體基底中,其中第一通孔彼此緊鄰設置;形成一側壁子,於第一通孔的側壁上;經由第一通孔蝕刻半導體基底,以形成多個第二通孔;拓寬連通第二通孔,以形成一瓶狀通孔;形成一絕緣層於基底上的瓶狀通孔中;沉積一第一導電層於瓶狀通孔中,其中第一導電層定義瓶狀通孔底部的一腔體;形成一連接墊於基底的正側,其中連接墊與第一導電層電連接;研磨基底的背側以暴露出腔體;以及由基底的後側填入一第二導電層於腔體中。
雖然本發明以實施例揭露如下,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準,且為了不致使本發明之精神晦澀難懂,一些習知結構與製程步驟的細節將不再於此揭露。同樣地,圖示所表示為實施例中的裝置示意圖但並非用以限定裝置的尺寸,特別是,為使本發明可更清晰地呈現,部分元件的尺寸係可能放大呈現於圖中。
第1-8圖為根據本發明之較佳實施例所繪示的用於堆疊封裝的直通基材穿孔結構的製造方法的剖面圖。如第1圖所示,提供一基底10,該基底具有一正側及一背側,其中基底10可例如為矽基底,或基底10可包含其他基底,例如一具有磊晶層的矽基底、一包含埋入式絕緣層的絕緣層上覆矽基底、一砷化鎵(GaAs)基底、一磷砷化鎵基底(GaAsP)、一磷化銦(InP)基底、一砷鋁鎵(GaAlAs)基底、或是一磷鎵銦基底(InGaP),本發明並不限於此。多個電路元件(未繪示),例如電晶體或電容,可製造於基底10的主要表面10a上。基底10具有厚度t,以一300釐米的晶圓來說,基底10的厚度t約為760微米。一層間介電層12設於基底10的主要表面10a上,其中層間介電層12可為一單一材料層或是多層材料層的結構。接著,形成一金屬內連線結構(未繪示)於層間介電層12中。一硬遮罩層14形成於層間介電層12上,其中硬遮罩層14例如為碳、底部抗反射層材料、金屬或其組合。
如第2圖所示,一光阻圖案16形成於硬遮罩層14上。本實施例中,光阻圖案16包含一孔洞圖案組,其具有一主要孔洞圖案16a以及多個次要孔洞圖案16b,其中次要孔洞圖案16b圍繞主要孔洞圖案16a。光阻圖案16的孔洞圖案組的上視圖繪示於第9圖中。根據一較佳實施例,孔洞圖案組可約50微米×50微米或者更小。在一實施例中,如第10圖所示,光阻圖案16包含一主要孔洞圖案16a以及一環狀孔洞圖案16b,其環繞主要孔洞圖案16a。根據其他實施例,如第11圖所示,光阻圖案16可包含一矩型主要孔洞圖案16a以及一矩型環狀孔洞圖案16b,其環繞主要孔洞圖案16a。
如第3圖所示,使用光阻圖案16為蝕刻遮罩,進行一乾蝕刻製程以形成多個通孔20,其包含一主要通孔20a以及多個次要通孔20b,其穿過層間介電層12並延伸至基底10的一預定深度d1。隨後,剝除圖案化的光阻圖案16。根據本發明之較佳實施例,於基底10主要表面下的預定深度d1小於5微米。接續,一側壁子材料層22順應地沉積於基底10上,以在通孔20的側壁及底部形成一層。本實施例中,側壁子材料層22由相對於基底10具有高蝕刻選擇比的介電材料構成。較佳情形下,側壁子材料層22可由氮化矽所構成。側壁子材料層22可覆蓋硬遮罩層14的頂面。
如第4圖所示,在沉積側壁子材料層22之後,進行一非等向性的乾蝕刻製程以經由通孔20蝕刻側壁子材料層22以及基底10,以於各別通孔20下形成深通孔30,其包含主要深通孔30a以及多個次要深通孔30b。如此,形成側壁子22a於各個通孔20的側壁。根據一較佳實施例,蝕刻基底10的主要表面下的預定深度d2小於53微米。
如第5圖所示,進行一蝕刻製程,經由深通孔30蝕刻位於側壁子22a下方的基底10的側壁。由於主要深通孔30a以及多個次要深通孔30b彼此緊鄰設置,加寬的主要深通孔30a以及加寬的多個次要深通孔30b將合併形成一連通的瓶狀通孔40,其包含主要通孔20a以及次要通孔20b位於底部連通腔室40a之上。在一較佳實施例中,可以稀釋的氨水溶液進行上述蝕刻製程,其中氨水溶液與水的濃度比較佳為1:5至1:50。接著,進行一氧化製程以於瓶狀通孔40的底部連通腔室40a的內表面形成一絕緣層42,在一較佳實施例中,該絕緣層為氧化矽,但本發明並不限於此。
如第6圖所示,在形成絕緣層42後,進行一化學氣相沉積製程(CVD)以順應地沉積一第一導電層44,例如鎢,於瓶狀通孔底部的內壁上。在一實施例中,第一導電層44可由複合金屬材料組成,例如氮化鈦/鎢、氮化鉭/鎢、氮化鈦/氮化鉭或氮化鎢/鎢等,其可由化學氣相沉積製程(CVD)、物理氣相沉積製程(PVD)或原子層沉積製程(ALD)形成,但本發明不以此為限。在一實施例中,第一導電層44可由多晶矽組成。第一導電層44可封蓋通孔20以在通孔20中形成導電插拴44a。在本實施例中,第一導電層44定義瓶狀通孔40底部的腔體46。接著,以蝕刻或拋光的方式,例如化學機械拋光(CMP),移除硬遮罩層14以及覆蓋層間介電層12部分的第一導電層44。
如第7圖所示,一連接墊50可形成於導電插拴44a上。在其他實施例中,連接墊50可藉由其他金屬層電連接導電插拴44a。連接墊50可包含一可接合的金屬層52以及一黏著層54。在一較佳的實施情形下,可接合的金屬層52可直接連結導電插拴44a。繼之,進行一晶背研磨製程,以研磨拋光基底10的背側。如先前所提及,在研磨前的基底10,以300釐米的晶圓而言,其厚度t一般約為760微米。而研磨後的晶圓,其基底10所剩下的厚度約為50微米甚至更薄。如此,在完成晶圓背側研磨後,移除導電層44的底部以及於瓶狀通孔40底部的絕緣層42,而暴露出腔體46。
如第8圖所示,接著,一晶種層62,例如銅晶種層,沉積於腔體46的內壁上,更進一步來說,係沉積於第一導電層44的表面上。接著,形成一第二導電層64,其中第二導電層64可為一銅層,其進行一銅電鍍製程以將銅沉積於晶種層62上。在一較佳實施例中,銅層64填入腔體46中且覆蓋晶圓背側,其中銅層64可由電鍍、無電極電鍍、化學電鍍或其他合適的方法形成,而於腔體46外的銅層64可藉由化學機械研磨製程(CMP)移除。在移除晶圓背側的銅後,即完成直通矽晶穿孔80製造。
本發明的優點在於:第一導電層44,例如鎢等,具有與矽相吻合或相類似的熱膨脹係數(CTE),以形成一具有較低應力的直通基材穿孔。在本實施例中,直通基材穿孔80包含一第一半部82及一第二半部84。第一半部82包含導電插拴44a,而第二半部84包含第一導電層44、銅晶種層62以及銅層64,其中第一半部82連結第二半部84,第二半部84由第一半部82的底部延伸至晶圓背側。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
10...基底
10a...主要表面
12...層間介電層
14...硬遮罩層
16...光阻圖案
16a...主要孔洞圖案
16b...次要孔洞圖案
20...通孔
20a...主要通孔
20b...次要通孔
22...側壁子材料層
22a...側壁子
30...深通孔
30a...主要深通孔
30b...次要深通孔
40...瓶狀通孔
40a、46...腔體
42...絕緣層
44...第一導電層
44a...導電插拴
50...連接墊
52...可接合的金屬層
54...黏著層
62...晶種層
64...第二導電層
80...直通基材穿孔
82...第一半部
84...第二半部
第1-8圖為根據本發明之較佳實施例所繪示的用於連結堆疊晶片的直通基材穿孔結構的製造方法的截面圖。
第9圖為根據本發明之較佳實施例所繪示的定義直通基材穿孔的光阻的孔洞圖案組的上視圖。
第10圖為根據本發明之又一較佳實施例所繪示的定義直通基材穿孔的光阻圖案的上視圖。
第11圖為根據本發明之另一較佳實施例所繪示的定義直通基材穿孔的光阻圖案的上視圖。
10...半導體基底
10a...主要表面
12...層間介電層
22a...側壁子
40...瓶狀通孔
42...絕緣層
44...第一導電層
44a...導電插拴
50...連接墊
52...可接合的金屬層
54...黏著層
62...晶種層
64...第二導電層
80...直通基材穿孔
82...第一半部
84...第二半部
Claims (25)
- 一種直通基材穿孔結構的製造方法,包含:提供一基底,該基底具有一正側及一背側,於該正側上設有一層間介電層;蝕刻一第一通孔,於該層間介電層及該基底中;形成一側壁子,於該第一通孔的側壁;經由該第一通孔蝕刻該基底,以形成一第二通孔;拓寬該第二通孔,以形成一瓶狀通孔;形成一絕緣層,於該瓶狀通孔底部的內壁;沉積一第一導電層於該瓶狀通孔中,其中該第一導電層定義該瓶狀通孔底部的一腔體;形成一連接墊於該基底的正側,其中該連接墊與該第一導電層電性連接;研磨該基底的背側以暴露出該腔體;以及由該基底的該背側填入一第二導電層於該腔體中。
- 如申請專利範圍第1項所述之直通基材穿孔結構的製造方法,其中該側壁子係由相較於該半導體基底具有較高蝕刻選擇比的材料所組成。
- 如申請專利範圍第1項所述之直通基材穿孔結構的製造方法,其中該絕緣層包含一氧化矽層。
- 如申請專利範圍第3項所述之直通基材穿孔結構的製造方法,其中該氧化矽層由熱氧化製程、化學氣相沉積製程(化學氣相沉積製程)或是原子層沉積製程(原子層沉積製程)所形成。
- 如申請專利範圍第3項所述之直通基材穿孔結構的製造方法,其中該氧化矽層形成於該基底所暴露出的表面,其中該表面未被該第二通孔中的該側壁子所覆蓋。
- 如申請專利範圍第1項所述之直通基材穿孔結構的製造方法,其中該絕緣層未填滿該瓶狀通孔。
- 如申請專利範圍第1項所述之直通基材穿孔結構的製造方法,其中該第一導電層包含鎢、氮化鎢、氮化鈦、氮化鉭或多晶矽。
- 如申請專利範圍第1項所述之直通基材穿孔結構的製造方法,其中該第一導電層封蓋該第一通孔。
- 如申請專利範圍第8項所述之直通基材穿孔結構的製造方法,其中該第一導電層順著該瓶狀通孔底部的內壁沉積。
- 如申請專利範圍第1項所述之直通矽晶穿孔結構的製造方法,其中該第二導電層包含銅。
- 一種直通基材穿孔結構的製造方法,包含:提供一基底,該基底具有一正側及一背側,於該正側設有一層間介電層;蝕刻多個第一通孔於該層間介電層以及該基底中,其中該些第一通孔彼此緊鄰設置;形成一側壁子,於該些第一通孔的側壁上;經由該些第一通孔蝕刻該基底,以形成多個第二通孔;拓寬連通該些第二通孔,以形成一瓶狀通孔;形成一絕緣層於該底上的該瓶狀通孔中;沉積一第一導電層於該些瓶狀通孔中,其中該第一導電層定義該瓶狀通孔底部的一腔體;形成一連接墊於該半導體基底的正側,其中該連接墊與該第一導電層電連接;研磨該半導體基底的背側以暴露出該腔體;以及由該半導體基底的該背側填入一第二導電層於該腔體中。
- 如申請專利範圍第11項所述之直通基材穿孔結構的製造方法,其中該多個第一通孔包含一主要通孔以及多個次要通孔,其中該些次要通孔圍繞該主要通孔。
- 如申請專利範圍第11項所述之直通基材穿孔結構的製造方法,其中該多個第一通孔包含一主要通孔以及一環狀通孔環繞該主要通孔。
- 如申請專利範圍第11項所述之直通基材穿孔結構的製造方法,其中該側壁子由相較於該半導體基底具有較高蝕刻選擇比的材料組成。
- 如申請專利範圍第11項所述之直通基材穿孔結構的製造方法,其中該絕緣層包含一氧化矽層。
- 如申請專利範圍第15項所述之直通基材穿孔結構的製造方法,其中該氧化矽層係由熱氧化製程、化學氣相沉積製程或是原子層沉積製程所形成。
- 如申請專利範圍第15項所述之直通基材穿孔結構的製造方法,其中該氧化矽層形成於該半導體基底所暴露出的表面,其中該表面未被該第二通孔中的該側壁子所覆蓋。
- 如申請專利範圍第11項所述之直通基材穿孔結構的製造方法,其中該絕緣層未填滿該瓶狀通孔。
- 如申請專利範圍第11項所述之直通基材穿孔結構的製造方法,其中該第一導電層包含鎢、氮化鎢、氮化鈦、氮化鉭或多晶矽。
- 如申請專利範圍第11項所述之直通基材穿孔結構的製造方法, 其中該第一導電層封蓋該第一通孔。
- 如申請專利範圍第20項所述之直通基材穿孔結構的製造方法,其中該第一導電層順著該瓶狀通孔底部的內壁沉積。
- 如申請專利範圍第11項所述之直通基材穿孔結構的製造方法,其中該第二導電層包含銅。
- 一種直通基材穿孔結構,包含:一基底,具有一第一側及一第二側;一第一半部,其由多個彼此緊鄰設置的通孔插塞所構成,並由該基底的一第一側延伸至該基底的一預定深度;一第二半部,接觸該第一半部,且由該第一半部的底部延伸至該基底的一第二側;以及一襯墊層,位於該第一半部與該基底之間及該第二半部與該基底之間。
- 如申請專利範圍第23項所述之直通基材穿孔結構,其中該第一半部包含由鎢所製成的一導電插栓。
- 如申請專利範圍第23項所述之直通基材穿孔結構,其中該第二半部包含一鎢層,並且該鎢層包覆一銅層。
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JP5868202B2 (ja) * | 2012-02-01 | 2016-02-24 | ローム株式会社 | 静電容量型圧力センサおよびその製造方法 |
US8872235B2 (en) * | 2012-02-23 | 2014-10-28 | Infineon Technologies Austria Ag | Integrated Schottky diode for HEMTs |
WO2014002154A1 (ja) * | 2012-06-26 | 2014-01-03 | パナソニック株式会社 | 半導体装置及びその製造方法 |
US9005458B2 (en) | 2013-02-26 | 2015-04-14 | Micron Technology, Inc. | Photonic device structure and method of manufacture |
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US10699954B2 (en) | 2018-04-19 | 2020-06-30 | Teledyne Scientific & Imaging, Llc | Through-substrate vias formed by bottom-up electroplating |
US10998279B2 (en) * | 2018-08-27 | 2021-05-04 | Infineon Technologies Ag | On-chip integrated cavity resonator |
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US20090278237A1 (en) * | 2008-05-06 | 2009-11-12 | International Business Machines Corporation | Through substrate via including variable sidewall profile |
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