CN111293103A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN111293103A
CN111293103A CN201910389424.4A CN201910389424A CN111293103A CN 111293103 A CN111293103 A CN 111293103A CN 201910389424 A CN201910389424 A CN 201910389424A CN 111293103 A CN111293103 A CN 111293103A
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China
Prior art keywords
electrode
film
insulating
conductive
electrode portion
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CN201910389424.4A
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Inventor
廖俊诚
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本公开提供一种半导体装置。该半导体装置包括一半导体基底、一导电贯通电极、一绝缘膜、一凸块以及一连接层，其中该连接层包括一可图案化材料，而可该图案化材料包含有多个导电粒子。该可图案化材料包括感光材料。该感光材料为光刻胶或聚亚酰胺。该导电粒子包括铜、镍、金、或银。该连接层可由下列方式予以形成：旋转涂布、化学气相沉积工艺、或是物理气相沉积工艺。该导电贯通电极贯穿该半导体基底。该绝缘膜围绕该导电贯通电极且使该导电贯通电极与该半导体基底电性地绝缘。该凸块设置在该导电贯通电极上。该连接层是设置在该凸块上。

Description

半导体装置
相关申请的交叉引用
本公开主张2018/12/07申请的美国临时申请案第62/776,548号及2019/02/22申请的美国正式申请案第16/283,292号的优先权及益处，该美国临时申请案及该美国正式申请案的内容以全文引用的方式并入本文中。
技术领域
本公开涉及一种半导体装置。特别涉及一种半导体装置，其具有一贯通电极以及具有导电粒子的可图案化材料的一连接层。
背景技术
二维的方式是已应用在传统的集成电路构装上。新款集成电路封装是可满足消费者市场的需求，例如增加功能性以及具有缩小尺寸与降低成本的优势，而对于新款集成电路封装的持续需求是已驱使半导体产业进行发展更创新的封装技术，如使用垂直的三维集成电路构装。
三维封装技术的大体上的优点，包括尺寸架构微型化(即缩小尺寸与减少重量)、在一单一封装中构装异质技术、以短且垂直互连取代冗长的二维互连，以及降低耗电。
半导体存储器的特性需求包括高数据稳定性、高速存储存取、低功率消耗以及缩小芯片尺寸等。近年来，已采用三维存储器装置，这种三维存储器装置是由垂直堆叠的积层型半导体芯片所形成，并使用硅穿孔与半导体芯片互连。硅穿孔为贯通电极，其是贯穿一半导体芯片，此半导体芯片包括典型地含有硅的一半导体基底。三维存储器装置的优点包括在多个芯片与存储器控制器之间，以大量的垂直硅穿孔堆叠多个芯片，其是允许多个宽频宽总线在多个芯片中的多个功能区域之间以高传输速率进行传输，而另一个优点为一可考虑的较小占用范围。因此，三维存储器装置是提供高存储容量、高存储存取速度，以及缩小芯片尺寸。而三维存储器装置包括混合存储器立方体以及高频宽存储器。
在三维存储器装置上的硅穿孔是可由中间通孔工艺所形成。举例来说，该工艺是可包括：1)在一半导体装置的一前表面上沉积多个前凸块；2)将一硅基底的一背表面变薄，并在晶圆加工期间(例如在晶体管成型与一配线工艺之间)，以硅显露蚀刻暴露多个铜质硅穿孔3)沉积一介电膜：以及4)以化学机械平坦化研磨该介电膜，以形成多个后凸块。上述的中间通孔工艺，特别是铜质硅穿孔的沉积以及以介电膜以化学机械平坦化的研磨，会带来显著的制造成本。在制造流程期间，会产生许多问题，包括由于晶圆翘曲所造成的背表面加工的不平整、由于硅显露蚀刻所造成的铜质硅穿孔的高度的不一致、当化学机械平坦化的一工艺容许范围降低时在暴露铜质硅穿孔的失败，以及当化学机械平坦化的一工艺容许范围提升时形成在一硅板上的浅划痕、裂缝以及其他缺陷。
上文的“现有技术”说明仅提供背景技术，并未承认上文的“现有技术”说明披露本公开的标的，不构成本公开的现有技术，且上文的“现有技术”的任何说明均不应作为本公开的任一部分。
发明内容
本公开的一实施例提供一种半导体结构。该半导体结构包括：一半导体基底、一导电贯通电极、一绝缘膜、一凸块，以及一连接层，其中该连接层包括一可图案化材料，而该可图案化材料包含有多个导电粒子。该导电贯通电极贯穿该半导体基底。该绝缘膜围绕该导电贯通电极且使该导电贯通电极与该半导体基底电性地绝缘。该凸块是设置在该导电贯通电极上。该连接层设置在该凸块上。
在本公开的一些实施例中，该可图案化材料包括感光材料。
在本公开的一些实施例中，该感光材料为光刻胶或聚亚酰胺。
在本公开的一些实施例中，该等导电粒子为铜、镍、金或是银。
在本公开的一些实施例中，该连接层由下列方式所形成：旋转涂布、化学气相沉积工艺或是物理气相沉积工艺。
在本公开的一些实施例中，该导电贯通电极包括一第一电极部、一第二电极部，以及一第三电极部。该第一电极部位在该半导体基底中。该第二电极部从该第一电极部垂直地突伸。该第三电极部从该第二电极部横向地突伸，该第三电极部包括一侧表面，以界定出该第三电极部的一宽度。
在本公开的一些实施例中，该导电贯通电极的该第三电极部是渐缩而呈锥形，以斜向的方式形成该第三电极部的该侧表面。
在本公开的一些实施例中，该导电贯通电极的该第三电极部朝向与该导电贯通电极的该第一电极部相对的一侧而渐缩而呈锥形。
在本公开的一些实施例中，该导电贯通电极的该第二电极部的一宽度，大致与该导电贯通电极的该第一电极部的一宽度相同，且该导电贯通电极的该第三电极部的该宽度，大于该第一电极部的该宽度与该第二电极部的该宽度。
在本公开的一些实施例中，该第二电极部、该第三电极部以及该半导体基底之间，形成一间隙。
在本公开的一些实施例中，该导电贯通电极的该第一电极部、该第二电极部以及该第三电极部是由相同材料所形成。
在本公开的一些实施例中，该绝缘膜包括一第一膜部、一第二膜部，以及一第三膜部。该第一膜部位于该第一电极部与该半导体基底之间。该第二膜部位在该间隙中。该第三膜部是从该第二膜部突伸，以覆盖该第三电极部的该侧表面的一部分。
在本公开的一些实施例中，该第三电极部的该侧表面的一剩余部分并未被该第三膜部所覆盖。
在本公开的一些实施例中，该绝缘膜的该第一膜部在该导电贯通电极的该第一电极部与该半导体基底之间具有一第一厚度，该绝缘膜的该第二膜部在该导电贯通电极的该第二电极部与该半导体基底之间具有一第二厚度，而该第二厚度大于该第一厚度。
在本公开的一些实施例中，该绝缘膜的该第三膜部是从该绝缘膜的该第二膜部突伸而具有一第三厚度，以覆盖该导电贯通电极的该第三电极部的该侧表面的该部分，该第三厚度小于该绝缘膜的该第二膜部的该第二厚度。
在本公开的一些实施例中，该绝缘膜的该第一膜部包括一第一绝缘层以及一第一绝缘衬垫，该绝缘膜的该第二膜部包括一第二绝缘层以及一第二绝缘衬垫，该绝缘膜的该第三膜部包括一第三绝缘衬垫，而该第二绝缘衬垫与该第一绝缘衬垫及该第三绝缘衬垫是连续的。
在本公开的一些实施例中，该绝缘膜的该第一膜部包括一第四绝缘衬垫，该第四绝缘衬垫位在该第一绝缘衬垫与该导电贯通电极的该第一电极部之间，该绝缘膜的该第二膜部包括一第五绝缘衬垫，该第五绝缘衬垫位在该第二绝缘衬垫与该导电贯通电极的该第二电极部之间，该绝缘膜的该第三膜部包括一第六绝缘衬垫，该第六绝缘衬垫位在该第三绝缘衬垫与该导电贯通电极的该第三电极部之间，且该第五绝缘衬垫与该第四绝缘衬垫及该第六绝缘衬垫是连续的。
在本公开的一些实施例中，该第一绝缘层在该第一绝缘衬垫与该半导体基底之间具有一第一厚度，该第二绝缘层在该导电贯通电极的该第三电极部与该半导体基底之间具有一第二厚度，而该第二厚度大于该第一厚度。
在本公开的一些实施例中，该第一绝缘衬垫、该第二绝缘衬垫以及该第三绝缘衬垫包括有一氮化硅膜，且该第五绝缘衬垫、该第五绝缘衬垫以及该第六绝缘衬垫包括有一氧化硅膜。
在本公开的一些实施例中，该氮化硅膜比该氧化硅膜更厚。
本公开的另一方面提供一电子单元。该电子单元包括至少两个上述的半导体结构。其中一个半导体结构的该导电贯通电极的第三电极部是经由该连接层而电性地连接到另一半导体结构的该凸块。该连接层是图案化在另一个半导体结构的该凸块上。
上文已相当广泛地概述本公开的技术特征及优点，从而使下文的本公开详细描述得以获得优选了解。构成本公开的保护范围标的的其它技术特征及优点将描述于下文。本公开所属技术领域中技术人员应了解，可相当容易地利用下文披露的概念与特定实施例可作为修改或设计其它结构或工艺而实现与本公开相同的目的。本公开所属技术领域中技术人员亦应了解，这类等效建构无法脱离本申请保护范围所界定的本公开的构思和范围。
附图说明
参阅实施方式与保护范围合并考量附图时，可得以更全面了解本申请的公开内容，附图中相同的元件符号是指相同的元件。
图1为结构示意图，例示本公开一些实施例的半导体装置的多个贯通电极。
图2为结构示意图，例示本公开一些实施例的半导体装置的一个贯通电极的一部分。
图3至图15为剖视示意图，例示本公开一些实施例的半导体装置的制造过程中的结构。
图16为剖视示意图，例示本公开一些实施例的电子单元的一对堆叠半导体装置的贯通电极。
附图标记说明：
10 半导体装置
10" 半导体装置
11 半导体基底
11a 膜层
11b 膜层
11c 膜层
12 元件区
13 配线区
14 电路元件
15 线路
16 前凸块
17 连接层
17a 可图案化材料
17b 导电粒子
18 贯通电极
18' 开口
18" 贯通电极
19 后凸块
19' 容室
19" 第三电极部
20 外衬垫
21 内衬垫
21a 膜层
21b 膜层
22 障壁膜
23 导电材料
23a 障壁层
23b 晶种层
24 光刻胶
25 抗热粘合材料
26 残留的硅层
27 暂时载体
28a 障壁-晶种层
28b 可图案化保护层
100 电子单元
具体实施方式
本公开的以下说明伴随并入且组成说明书的一部分的附图，说明本公开的实施例，然而本公开并不受限于该实施例。此外，以下的实施例可适当整合以下实施例以完成另一实施例。
“一实施例”、“实施例”、“例示实施例”、“其他实施例”、“另一实施例”等是指本公开所描述的实施例可包含特定特征、结构或是特性，然而并非每一实施例必须包含该特定特征、结构或是特性。再者，重复使用“在实施例中”一语并非必须指相同实施例，然而可为相同实施例。
为了使得本公开可被完全理解，以下说明提供详细的步骤与结构。显然，本公开的实施不会限制该技术领域中的技术人员已知的特定细节。此外，已知的结构与步骤不再详述，以免不必要地限制本公开。本公开的优选实施例详述如下。然而，除了详细说明之外，本公开亦可广泛实施于其他实施例中。本公开的范围不限于详细说明的内容，而是由保护范围定义。
图1为结构示意图，例示本公开一些实施例的半导体装置10中的多个贯通电极。半导体装置10包括一半导体基底11、一元件区12，以及一配线区13。在一些实施例中，半导体基底11可为绝缘层上覆硅(silicon on insulator，SOI)。在一些实施例中，半导体装置10可为一芯片。在一些实施例中，绝缘层上覆硅包括由硅所制的一膜层11a(例如一硅层或一半导体层)以及由氧化硅所制的一膜层11b(例如一氧化硅层或一绝缘层)。在一些实施例中，绝缘层上覆硅包括由硅所制的另一膜层11c，其直接接触膜层11b的一表面并位在膜层11b的表面上，膜层11b直接接触膜层11c的表面是相对直接接触膜层11a的表面。在完成制造半导体装置10的流程期间或之前，已移除由硅所制且直接接触膜层11b的表面并位在膜层11b的表面上的膜层11c。配线区13可形成在元件区12上。在一些实施例中，元件区12可包括一或以上个电路元件14。在一些实施例中，配线区13可包括多个线路15。多个前凸块16可形成在配线区13上。一连接层17可形成在每一前凸块16上。在一些实施例中，连接层17包括一可图案化材料17a，而可图案化材料17a含有多个导电粒子17b。可图案化材料17a可包括光刻胶材料。而光刻胶材料可为光刻胶或聚亚酰胺的材料。而导电粒子17b可包括铜、镍、金或是银，但并不以此为限。在一些实施例中，连接层17由下列方式所形成：旋转涂布、化学气相沉积工艺或是物理气相沉积工艺，但并不以此为限。
每一贯通电极18的周围，可形成一内衬垫21以及一外衬垫20，以当作在贯通电极18与半导体基底11之间的绝缘膜。在一些实施例中，内衬垫21以及外衬垫20可形成如一圆形柱、一正方形柱，或者是一多边形柱。在一些实施例中，内衬垫21可由非等向性蚀刻而形成在半导体基底11上。在一些实施例中，外衬垫20可由氧化硅铜扩散到膜层11a。当形成一容室时，外衬垫20可当作膜层11a的一保护膜的功能，其将在本公开中于后文进行详述。
图2为结构示意图，例示本公开一些实施例的半导体装置10中的一个贯通电极18的一部分。贯通电极18可经由半导体基底11的膜层11a及膜层11b所形成。在一些实施例中，从半导体基底11突伸的一后凸块19，由干蚀刻所暴露。在一些实施例中，贯通电极18在半导体基底11的膜层11a中的部分的一截面宽度(cross-sectional width)，可小于后凸块19的一截面宽度。在一些实施例中，外衬垫20可形成在半导体基底11的膜层11a内。在一些实施例中，内衬垫21可延伸到每一后凸块19的一侧表面。在一些实施例中，内衬垫21的一部分位在后凸块19的侧表面上，以当作一侧壁间隙子。在一些实施例中，内衬垫21可包括直接接触外衬垫20且由氮化硅所制的一膜层21a，以及直接接触与半导体基底11中的贯通电极18且由氧化硅所制的一膜层21b。内衬垫21可延伸到后凸块19的侧表面的至少一部分。因此，导电的贯通电极18可包括一第一电极部、一第二电极部，以及一第三电极部，第一电极部穿经一半导体基底(例如膜层11a)，第二电极部从第一电极部垂直地突伸，第三电极部(后凸块)19从第二电极部横向地突伸。因此，在第二电极部、第三电极部，以及半导体基底之间形成一间隙(gap)，且形成来将贯动电极18与膜层11a绝缘的绝缘膜(11b、20、21a、21b)包括一第一膜部、一第二膜部，以及一第三膜部，第一膜部位在贯通电极18的第一电极部与半导体基底(或膜层11a)之间，第二膜部在贯通电极18的第二电极部、第三电极部，以及半导体基底之间的间隙中；而当留下未被覆盖的第三电极部的侧表面的一剩余部分时，第三膜部(对应膜层21a与膜层21b的部分)从第二膜部突伸，以覆盖第三电极部的一侧表面的一部分。
图3至图15为剖视示意图，例示本公开一些实施例的半导体装置10的制造过程中的结构。参考图3，半导体装置10可包括一半导体基底11、一元件区12以及一障壁膜22，半导体基底11包括膜层11a、11c以及在膜层11a、11c之间的膜层11b。在一些实施例中，元件区12可形成在膜层11a的一表面上，膜层11a的该表面相对直接接触膜层11b的一表面。在一些实施例中，膜层11a的一厚度可接近2.5μm，膜层11b的一厚度可接近20μm，而元件区12的一厚度可接近20μm。在一些实施例中，障壁膜22可形成在元件区12上。障壁膜22可作为防铜扩散膜以及作为一蚀刻终止膜。在一些实施例中，障壁膜22可包括氮化硅、碳化硅，但并不以此为限。
参考图4，用于形成贯通电极18的干蚀刻可经由障壁膜22、元件区12以及膜层11a来实现。因此，用于贯通电极18的一开口18'可通过一干蚀刻方法经由障壁膜22、元件区12以及膜层11a来形成。在一些实施例中，当铺开膜层11a时，一波希法(Bosch method)可用于干蚀刻。在一些实施例中，六氟化硫(SF6)气体可用于干蚀刻，八氟环丁烷(C4F8)气体可用于聚合物沉积。在一些实施例中，贯通电极是可由如图4的中间通孔方法所形成，或者是其他工艺，例如一先通孔方法。
参考图5，在一些实施例中，外衬垫20可为一氧化硅层，且在接近350℃至500℃进行沉积。外衬垫20的一厚度可为1μm。在此工艺中，可使用一氧化硅模或一层压膜，而层压膜包括一氧化硅层以及一氮化硅层。在一些实施例中，层压膜可包括具有接近0.3μm厚度的氧化硅层以及具有接近0.7μm厚度的氮化硅层。在一些实施例中，层压膜可包括具有接近0.7μm厚度的一氧化硅层以及具有接近0.3μm厚度的一氮化硅层，但并不以此为限。
参考图6，为了暴露在开口18'下方的膜层11c，外衬垫20面对在开口18'底部的半导体基底11的膜层11b的一部分，以及膜层11b位在开口18'底部下方的一部分，通过蚀刻而铺开。在一些实施例中，可通过使用一或多个气体的结合的非等向性干蚀刻方法来实现开口18'的形成，而一或多个气体的结合是例如四氟甲烷(CF4)气体、八氟环丁烷(C4F8)气体、六氟丁二烯(C4F6)气体、八氟环戊烯(C5F8)气体、氧气、一氧化碳气体、氩气等等，但并不以此为限。在一些实施例中，可通过使用障壁膜22当作用于蚀刻的终止物的非等向性干蚀刻，来移除在障壁膜22上的外衬垫20。在贯通电极18的一侧壁上的外衬垫20可残留(remain)在膜层11a中。
参考图7，在一些实施例中，可通过一非等向性湿蚀刻对已暴露的膜层11c进行蚀刻。在一些实施例中，为了形成具有接近2μm到5μm的深度的多个容室19'，非等向性湿蚀刻可使用一氢氧化钾基溶液。在非等向性湿蚀刻中，可通过在膜层11c中使用不同的蚀刻速度，来形成用于后凸块19的具有一梯形体(trapezoid body)的该等容室19'。因此，该等容室19'的每一容室19'可具有一斜侧壁，且每一后凸块19可朝相对开口18'的一侧逐渐变细，以形成后凸块19的一斜侧表面。在一些实施例中，用于蚀刻以形成该等容室19'，可使用一等向性湿蚀刻方法或是一等向性干蚀刻方法来取代非等向性干蚀刻方法。在一些实施例中，该等容室19'的形状可取决于蚀刻方式而有所不同。外衬垫20可残留在开口18'的侧壁上。
参考图8，在一些实施例中，内衬垫21可为一层压膜，层压膜位在一氮化硅膜上，且层压膜为厚度0.3μm的一氧化硅膜，而氮化硅膜具有0.2μm的厚度，且由原子层沉积方法所形成。当将铜填满在开口18'与容室19'中时，氮化硅膜可避免铜扩散到硅层。在一些实施例中，氮化硅膜的一厚度可足够小，以避免在贯通电极18与一邻近贯通电极之间的寄生电容增加。在一些实施例中，氧化硅膜可被形成来补足氮化硅膜的厚度。在一些实施例中，氧化硅膜可低于氮化硅膜，以避免铜扩散，然而，氧化硅膜可高于氮化硅膜，以避免寄生电容。
参考图9，在一些实施例中，一导电材料可由铜电镀所填满。在一些实施例中，于应用原子层沉积以传入在开口18'与容室19'的一内壁上的一障壁层23a(例如钽及/或氮化钽)以及一晶种层23b(例如铜)之后，可通过向上式铜电镀方法以实施铜电镀。在一些实施例中，可使用电子束诱发沉积、铜沉积或者是熔化金属填充来取代向上式铜电镀方法。
参考图10，在一些实施例中，在障壁膜22上的铜可通过化学机械平坦化而被移除。在一些实施例中，内衬垫21的一部分可残留在障壁膜22上，以覆盖元件区12。因此，可形成贯通电极18以填满开口18'及容室19'。
参考图11，在一些实施例中，一配线区13可形成在元件区12上的障壁膜22之上。一可图案化保护层28b以及包括一障壁层(例如具有15nm厚度的一钛层与一晶种层(例如具有200nm厚度的一铜层)的障壁-晶种层)28a，可形成在配线区13的一顶表面上。在形成用于一些前凸块的一光刻胶24之后，在光刻胶24上的一前凸块形成区可被打开，以暴露障壁-晶种层28a。在一些实施例中，光刻胶24的一厚度可接近50μm，但本公开并不以此为限。
参考图12，前凸块16可在已暴露的障壁-晶种层28a上通过铜电镀所形成。在一些实施例中，从铜电镀所形成的前凸块的一厚度，可接近10μm。在一些实施例中，于铜电镀之后，连接层17可被连续地图案化，并可通过旋转涂布、化学气相沉积工艺，或者是物理气相沉积工艺所形成，但本公开并不以此为限。连接层17可包括一可图案化材料17a，而可图案化材料17a包含多个导电粒子17B，且可图案化材料17a可具有18μm的一厚度。在一些实施例中，可图案化材料17a可为可图案化的，且可形成在前凸块16上，而导电粒子17b包括铜、镍、金或者是银，但本公开并不以此为限。于使用等离子体灰化与一氨气成分的溶液移除光刻胶24之后，可在使用前凸块当作一遮罩时，用一磷酸溶液将已暴露的障壁-晶种层28a进行移除。
参考图13，在一些实施例中，半导体装置10可垂直地被翻转。前凸块16可通过抗热粘合材料25而粘接到暂时载体27。
参考图14，在一些实施例中，已暴露的膜层11c可通过晶背研磨及/或化学机械平坦化所移除，但本公开并不以此为限。在一些实施例中，为了保护膜层11c不会从贯通电极18而来的铜污染，用以移除的已暴露的膜层11c的部分的一厚度，可被控制来保护贯通电极18避免被暴露。因此，在移除半导体基底11的一部分(例如膜层11c)之后，一残留的硅层26可残留下来。残留的硅层26可覆盖该等后凸块19。
参考图15，在一些实施例中，可移除在膜层11b上的残留的硅层26。在一些实施例中，使用六氟化硫气体成分的干蚀刻，对膜层11b与内衬垫21具有接近20到50蚀刻选择比。在一些实施例中，围绕后凸块19的内衬垫21可用一蚀刻气体进行蚀刻，以暴露后凸块19。在一些实施例中，蚀刻气体可为氟碳气体与惰性气体的一气体混合物。内衬垫21与障壁层23a的蚀刻是可被执行，直至后凸块19暴露。在一些实施例中，后凸块19通过非等向性蚀刻而暴露。因此，当内衬垫21的一部分可残留在后凸块19上时，每一后凸块19的一顶表面可完全地暴露。于后凸块19暴露之后，可执行例如包含腐蚀抑制剂的碱金属溶液的后处理，以避免铜腐蚀并移除一蚀刻残存物。
因此，本公开一些实施例的半导体装置的贯通电极，可由以下的方法所形成：提供一基底11，基底11包括一半导体膜层11a、一牺牲层11c，以及一绝缘层，而绝缘膜层11b位在半导体膜层11a与牺牲膜层11c之间；形成贯穿半导体膜层11a与绝缘膜层11b的一开口18'；对牺牲膜层11c进行蚀刻，以在牺牲膜层11c形成一容室19'；在开口18'与容室19'涂上一导电材料23，以形成具有一后凸块19(例如第一凸块)的一贯通电极18；以及暴露后凸块19的一部分。接下来，一前凸块(例如一第二凸块)16形成在贯通电极18相对后凸块19的一端上。再者，一连接层17被图案化在前凸块16上。在一些实施例中，连接层17是可图案化的，且包括一可图案化材料17a，可图案化材料17a包含多个导电粒子17b。在一些实施例中，可图案化材料17a包括感光材料。在一些实施例中，感光材料为一光刻胶或聚亚酰胺。在一些实施例中，该等导电粒子17b包括铜、镍、金或是银。在一些实施例中，连接层17可由下列方式所形成：旋转涂布、化学气相沉积工艺或是物理气相沉积工艺。
图16为示意图，例示本公开一些实施例的电子单元100的一对堆叠半导体装置10、10"的贯通电极。图16显示每一后凸块19是物理上经由连接层17而连接到前凸块16之后的示意图。在一些实施例中，后凸块19的一截面宽度可大于前凸块16的一截面宽度。为了降低流动性所造成的缺陷，流动性可造成可图案化材料17a朝向后凸块19的一侧壁移动并从可图案化材料17a落下，则后凸块19的截面宽度设计为大于前凸块16的截面宽度。
再者，本公开的一目的在于提供一电子单元。电子单元100(如图16所示)包括至少二上述的半导体装置10、10"。一半导体装置10"的导电贯通电极18"的第三电极部19"经由连接层17而电性地连接到另一半导体装置10的前凸块16。连接层17为可图案化的。意即，如上的二相邻的半导体装置10、10"，经由连接层17而可电性地相互连接，其中连接层17为可图案化的，且包括一可图案化材料17a，而可图案化材料17a包含多个导电粒子17B。在一些实施例中，该导电粒子17b包括铜、镍、金或是银。在一些实施例中，连接层17可由下列方式所形成：旋转涂布、化学气相沉积工艺或是物理气相沉积工艺。
本公开的一实施例提供一种半导体结构。该半导体结构包括：一半导体基底、一导电贯通电极、一绝缘膜、一凸块，以及一连接层，其中该连接层包括一可图案化材料，而该可图案化材料包含有多个导电粒子。该导电贯通电极贯穿该半导体基底。该绝缘膜围绕该导电贯通电极且使该导电贯通电极与该半导体基底电性地绝缘。该凸块设置在该导电贯通电极上。该连接层设置在该凸块上。
本公开的一目的在于提供一电子单元。电子单元包括至少二上述的半导体装置。其中一半导体装置的导电贯通电极的第三电极部经由连接层而电性地连接到另一半导体装置的前凸块。连接层可图案化在另一半导体装置的凸块上。
虽然已详述本公开及其优点，然而应理解可进行各种变化、取代与替代而不脱离本申请保护范围所定义的本公开的构思与范围。例如，可用不同的方法实施上述的许多工艺，并且以其他工艺或其组合替代上述的许多工艺。
再者，本公开的范围并不受限于说明书中的工艺、机械、制造、物质组成物、手段、方法与步骤的特定实施例。该技术领域的技术人员可自本公开的披露内容理解可根据本公开而使用与本文的对应实施例具有相同功能或是达到实质上相同结果的现存或是未来发展的工艺、机械、制造、物质组成物、手段、方法或步骤。据此，这些工艺、机械、制造、物质组成物、手段、方法或步骤包含于本公开的保护范围内。

Claims (20)

1.一种半导体结构，包括：
一半导体基底；
一导电贯通电极，贯穿该半导体基底；
一绝缘膜，围绕该导电贯通电极且使该导电贯通电极与该半导体基底电性地绝缘；
一凸块，设置在该导电贯通电极上；以及
一连接层，设置在该凸块上；
其中该连接层包括一可图案化材料，而该可图案化材料包含有多个导电粒子。
2.如权利要求1的半导体结构，其中该可图案化材料包括感光材料。
3.如权利要求2的半导体结构，其中该感光材料为光刻胶或聚亚酰胺。
4.如权利要求1的半导体结构，其中所述导电粒子为铜、镍、金或是银。
5.如权利要求1的半导体结构，其中该连接层由下列方式所形成：旋转涂布、化学气相沉积工艺或是物理气相沉积工艺。
6.如权利要求1的半导体结构，其中该导电贯通电极包括：
一第一电极部，位在该半导体基底中；
一第二电极部，从该第一电极部垂直地突伸；以及
一第三电极部，从该第二电极部横向地突伸，该第三电极部包括一侧表面，以界定出该第三电极部的一宽度。
7.如权利要求6的半导体结构，其中该导电贯通电极的该第三电极部是渐缩而呈锥形，以斜向的方式形成该第三电极部的该侧表面。
8.如权利要求7的半导体结构，其中该导电贯通电极的该第三电极部朝向与该导电贯通电极的该第一电极部相对的一侧而渐缩而呈锥形。
9.如权利要求8的半导体结构，其中该导电贯通电极的该第二电极部的一宽度，大致与该导电贯通电极的该第一电极部的一宽度相同，且该导电贯通电极的该第三电极部的该宽度，大于该第一电极部的该宽度与该第二电极部的该宽度。
10.如权利要求6的半导体结构，其中该第二电极部、该第三电极部以及该半导体基底之间，形成一间隙。
11.如权利要求6的半导体结构，其中该导电贯通电极的该第一电极部、该第二电极部以及该第三电极部由相同材料所形成。
12.如权利要求10的半导体结构，其中该绝缘膜包括：
一第一膜部，位于该第一电极部与该半导体基底之间；
一第二膜部，位在该间隙中；以及
一第三膜部，从该第二膜部突伸，以覆盖该第三电极部的该侧表面的一部分。
13.如权利要求12的半导体结构，其中该第三电极部的该侧表面的一剩余部分并未被该第三膜部所覆盖。
14.如权利要求12的半导体结构，其中该绝缘膜的该第一膜部在该导电贯通电极的该第一电极部与该半导体基底之间具有一第一厚度，该绝缘膜的该第二膜部在该导电贯通电极的该第二电极部与该半导体基底之间具有一第二厚度，而该第二厚度大于该第一厚度。
15.如权利要求14的半导体结构，其中该绝缘膜的该第三膜部从该绝缘膜的该第二膜部突伸而具有一第三厚度，以覆盖该导电贯通电极的该第三电极部的该侧表面的该部分，该第三厚度小于该绝缘膜的该第二膜部的该第二厚度。
16.如权利要求12的半导体结构，其中该绝缘膜的该第一膜部包括一第一绝缘层以及一第一绝缘衬垫，该绝缘膜的该第二膜部包括一第二绝缘层以及一第二绝缘衬垫，该绝缘膜的该第三膜部包括一第三绝缘衬垫，而该第二绝缘衬垫与该第一绝缘衬垫及该第三绝缘衬垫是连续的。
17.如权利要求16的半导体结构，其中该绝缘膜的该第一膜部包括一第四绝缘衬垫，该第四绝缘衬垫位在该第一绝缘衬垫与该导电贯通电极的该第一电极部之间，该绝缘膜的该第二膜部包括一第五绝缘衬垫，该第五绝缘衬垫位在该第二绝缘衬垫与该导电贯通电极的该第二电极部之间，该绝缘膜的该第三膜部包括一第六绝缘衬垫，该第六绝缘衬垫位在该第三绝缘衬垫与该导电贯通电极的该第三电极部之间，且该第五绝缘衬垫与该第四绝缘衬垫及该第六绝缘衬垫是连续的。
18.如权利要求17的半导体结构，其中该第一绝缘层在该第一绝缘衬垫与该半导体基底之间具有一第一厚度，该第二绝缘层在该导电贯通电极的该第三电极部与该半导体基底之间具有一第二厚度，而该第二厚度大于该第一厚度。
19.如权利要求17的半导体结构，其中该第一绝缘衬垫、该第二绝缘衬垫以及该第三绝缘衬垫包括有一氮化硅膜，且该第五绝缘衬垫、该第五绝缘衬垫以及该第六绝缘衬垫包括有一氧化硅膜。
20.如权利要求19的半导体结构，其中该氮化硅膜比该氧化硅膜更厚。
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