TW202023031A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TW202023031A
TW202023031A TW108110085A TW108110085A TW202023031A TW 202023031 A TW202023031 A TW 202023031A TW 108110085 A TW108110085 A TW 108110085A TW 108110085 A TW108110085 A TW 108110085A TW 202023031 A TW202023031 A TW 202023031A
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Taiwan
Prior art keywords
electrode
insulating
film
conductive
semiconductor structure
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TW108110085A
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English (en)
Inventor
廖俊誠
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南亞科技股份有限公司
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Publication of TW202023031A publication Critical patent/TW202023031A/zh

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Abstract

本揭露提供一種半導體裝置。該半導體裝置包括一半導體基底、一導電貫通電極、一絕緣膜、一凸塊以及一連接層，其中該連接層包括一可圖案化材料，而可該圖案化材料包含有多個導電粒子。該可圖案化材料包括感光材料。該感光材料為光阻或聚亞醯胺。該導電粒子包括銅、鎳、金、或銀。該連接層可由下列方式予以形成：旋轉塗佈、化學氣相沉積製程、或是物理氣相沉積製程。該導電貫通電極貫穿該半導體基底。該絕緣膜圍繞該導電貫通電極且使該導電貫通電極與該半導體基底電性地絕緣。該凸塊設置在該導電貫通電極上。該連接層係設置在該凸塊上。

Description

半導體裝置
本申請案主張2018/12/07申請之美國臨時申請案第62/776,548號及2019/02/22申請之美國正式申請案第16/283,292號的優先權及益處，該美國臨時申請案及該美國正式申請案之內容以全文引用之方式併入本文中。
本揭露係關於一種半導體裝置。特別是關於一種半導體裝置，其具有一貫通電極以及具有導電粒子之可圖案化材料的一連接層。
二維的方式係已應用在傳統的積體電路構裝上。新款積體電路封裝係可滿足消費者市場的需求，例如增加功能性以及具有縮小尺寸與降低成本的優勢，而對於新款積體電路封裝的持續需求係已驅使半導體產業進行發展更創新的封裝技術，如使用垂直的三維積體電路構裝。
三維封裝技術之大體上的優點，包括尺寸架構微型化(即縮小尺寸與減少重量)、在一單一封裝中構裝異質技術、以短且垂直互連取代冗長的二維互連，以及降低耗電。
半導體記憶體的特性需求係包括高資料穩定性、高速記憶存取、低功率消耗以及縮小晶片尺寸等。近年來，係已採用三維記憶體裝置，此種三維記憶體裝置係由垂直堆疊的積層型半導體晶片所形成，並使用矽穿孔與半導體晶片互連。矽穿孔係為貫通電極，其係貫穿一半導體晶片，此半導體晶片係包括典型地含有矽的一半導體基底。三維記憶體裝置的優點包括在複數個晶片與記憶體控制器之間，以大量的垂直矽穿孔推疊複數個晶片，其係允許多個寬頻寬匯流排在複數個晶片中的多個功能區塊之間以高傳輸速率進行傳輸，而另一個優點係為一可考慮的較小佔用範圍。因此，三維記憶體裝置係提供高記憶容量、高記憶存取速度，以及縮小晶片尺寸。而三維記憶體裝置係包括混合記憶體立方體以及高頻寬記憶體。
在三維記體體裝置上的矽穿孔係可由中間通孔製程所形成。舉例來說，該製程係可包括：1)在一半導體裝置的一前表面上沉積多個前凸塊；2)將一矽基底的一背表面變薄，並在晶圓加工期間(例如在電晶體成型與一配線製程之間)，以矽顯露蝕刻暴露多個銅質矽穿孔3)沉積一介電膜：以及4)以化學機械平坦化研磨該介電膜，以形成多個後凸塊。上述的中間通孔製程，特別是銅質矽穿孔的沉積以及以介電膜以化學機械平坦化之研磨，係會帶來顯著的製造成本。在製造流程期間，係會產生許多問題，包括由於晶圓翹曲所造成的背表面加工之不平整、由於矽顯露蝕刻所造成的銅質矽穿孔之高度的不一致、當化學機械平坦化的一製程容許範圍降低時在暴露銅質矽穿孔的失敗，以及當化學機械平坦化的一製程容許範圍提升時形成在一矽板上的淺劃痕、裂縫以及其他缺陷。
上文之「先前技術」說明僅係提供背景技術，並未承認上文之「先前技術」說明揭示本揭露之標的，不構成本揭露之先前技術，且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露之一實施例提供一種半導體結構。該半導體結構包括：一半導體基底、一導電貫通電極、一絕緣膜、一凸塊，以及一連接層，其中該連接層包括一可圖案化材料，而該可圖案化材料係包含有多個導電粒子。該導電貫通電極係貫穿該半導體基底。該絕緣膜係圍繞該導電貫通電極且使該導電貫通電極與該半導體基底電性地絕緣。該凸塊係設置在該導電貫通電極上。該連接層係設置在該凸塊上。
在本揭露之一些實施例中，該可圖案化材料係包括感光材料。
在本揭露之一些實施例中，該感光材料係為光阻或聚亞醯胺。
在本揭露之一些實施例中，該等導電粒子係為銅、鎳、金、或是銀。
在本揭露之一些實施例中，該連接層係由下列方式所形成：旋轉塗佈、化學氣相沉積製程、或是物理氣相沉積製程。
在本揭露之一些實施例中，該導電貫通電極包括一第一電極部、一第二電極部，以及一第三電極部。該第一電極部係位在該半導體基底中。該第二電極部係從該第一電極部垂直地突伸。該第三電極部係從該第二電極部橫向地突伸，該第三電極部包括一側表面，以界定出該第三電極部的一寬度。
在本揭露之一些實施例中，該導電貫通電極的該第三電極部係漸縮而呈錐形，以斜向的方式形成該第三電極部的該側表面。
在本揭露之一些實施例中，該導電貫通電極的該第三電極部係朝向與該導電貫通電極之該第一電極部相對的一側而漸縮而呈錐形。
在本揭露之一些實施例中，該導電貫通電極之該第二電極部的一寬度，係大致與該導電貫通電極之該第一電極部的一寬度相同，且該導電貫通電極之該第三電極部的該寬度，係大於該第一電極部的該寬度與該第二電極部的該寬度。
在本揭露之一些實施例中，該第二電極部、該第三電極部以及該半導體基底之間，係形成一間隙。
在本揭露之一些實施例中，該導電貫通電極的該第一電極部、該第二電極部以及該第三電極部係由相同材料所形成。
在本揭露之一些實施例中，該絕緣膜係包括一第一膜部、一第二膜部，以及一第三膜部。該第一膜部係位於該第一電極部與該半導體基底之間。該第二膜部係位在該間隙中。該第三膜部係從該第二膜部突伸，以覆蓋該第三電極部之該側表面的一部份。
在本揭露之一些實施例中，該第三電極部之該側表面的一剩餘部份係並未被該第三膜部所覆蓋。
在本揭露之一些實施例中，該絕緣膜的該第一膜部在該導電貫通電極的該第一電極部與該半導體基底之間係具有一第一厚度，該絕緣膜的該第二膜部在該導電貫通電極的該第二電極部與該半導體基底之間係具有一第二厚度，而該第二厚度係大於該第一厚度。
在本揭露之一些實施例中，該絕緣膜的該第三膜部係從該絕緣膜的該第二膜部突伸而具有一第三厚度，以覆蓋該導電貫通電極之該第三電極部的該側表面之該部份，該第三厚度係小於該絕緣膜之該第二膜部的該第二厚度。
在本揭露之一些實施例中，該絕緣膜的該第一膜部係包括一第一絕緣層以及一第一絕緣襯墊，該絕緣膜的該第二膜部係包括一第二絕緣層以及一第二絕緣襯墊，該絕緣膜的該第三膜部係包括一第三絕緣襯墊，而該第二絕緣襯墊係與該第一絕緣襯墊及該第三絕緣襯墊是連續的。
在本揭露之一些實施例中，該絕緣膜的該第一膜部係包括一第四絕緣襯墊，該第四絕緣襯墊係位在該第一絕緣襯墊與該導電貫通電極的該第一電極部之間，該絕緣膜的該第二膜部係包括一第五絕緣襯墊，該第五絕緣襯墊係位在該第二絕緣襯墊與該導電貫通電極的該第二電極部之間，該絕緣膜的該第三膜部係包括一第六絕緣襯墊，該第六絕緣襯墊係位在該第三絕緣襯墊與該導電貫通電極的該第三電極部之間，且該第五絕緣襯墊係與該第四絕緣襯墊及該第六絕緣襯墊是連續的。
在本揭露之一些實施例中，該第一絕緣層在該第一絕緣襯墊與該半導體基底之間具有一第一厚度，該第二絕緣層在該導電貫通電極之該第三電極部與該半導體基底之間具有一第二厚度，而該第二厚度係大於該第一厚度。
在本揭露之一些實施例中，該第一絕緣襯墊、該第二絕緣襯墊以及該第三絕緣襯墊包括有一氮化矽膜，且該第五絕緣襯墊、該第五絕緣襯墊以及該第六絕緣襯墊係包括有一氧化矽膜。
在本揭露之一些實施例中，該氮化矽膜係比該氧化矽膜更厚。
本揭露之另一方面係提供一電子單元。該電子單元係包括至少二個上述的半導體結構。其中一個半導體結構的該導電貫通電極之第三電極部係經由該連接層而電性地連接到另一半導體結構的該凸塊。該連接層係圖案化在另一個半導體結構的該凸塊上。
上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
本揭露之以下說明伴隨併入且組成說明書之一部分的圖式，說明本揭露之實施例，然而本揭露並不受限於該實施例。此外，以下的實施例可適當整合以下實施例以完成另一實施例。
「一實施例」、「實施例」、「例示實施例」、「其他實施例」、「另一實施例」等係指本揭露所描述之實施例可包含特定特徵、結構或是特性，然而並非每一實施例必須包含該特定特徵、結構或是特性。再者，重複使用「在實施例中」一語並非必須指相同實施例，然而可為相同實施例。
為了使得本揭露可被完全理解，以下說明提供詳細的步驟與結構。顯然，本揭露的實施不會限制該技藝中的技術人士已知的特定細節。此外，已知的結構與步驟不再詳述，以免不必要地限制本揭露。本揭露的較佳實施例詳述如下。然而，除了詳細說明之外，本揭露亦可廣泛實施於其他實施例中。本揭露的範圍不限於詳細說明的內容，而是由申請專利範圍定義。
圖1為結構示意圖，例示本揭露一些實施例的半導體裝置10中的多個貫通電極。半導體裝置10係包括一半導體基底11、一元件區12，以及一配線區13。在一些實施例中，半導體基底11係可為絕緣層上覆矽(silicon on insulator，SOI)。在一些實施例中，半導體裝置10係可為一晶片。在一些實施例中，絕緣層上覆矽包括由矽所製的一膜層11a(例如一矽層或一半導體層)以及由氧化矽所製的一膜層11b(例如一氧化矽層或一絕緣層)。在一些實施例中，絕緣層上覆矽包括由矽所製的另一膜層11c，其係直接接觸膜層11b的一表面並位在膜層11b的表面上，膜層11b直接接觸膜層11c的表面係相對直接接觸膜層11a的表面。在完成製造半導體裝置10的流程期間或之前，係已移除由矽所製且直接接觸膜層11b的表面並位在膜層11b的表面上的膜層11c。配線區13係可形成在元件區12上。在一些實施例中，元件區12係可包括一或以上個電路元件14。在一些實施例中，配線區13係可包括多個線路15。多個前凸塊16係可形成在配線區13上。一連接層17係可形成在每一前凸塊16上。在一些實施例中，連接層17係包括一可圖案化材料17a，而可圖案化材料17a係含有多個導電粒子17b。可圖案化材料17a係可包括光阻材料。而光阻材料係可為光阻或聚亞醯胺之材料。而導電粒子17b係可包括銅、鎳、金、或是銀，但並不以此為限。在一些實施例中，連接層17係由下列方式所形成：旋轉塗佈、化學氣相沉積製程、或是物理氣相沉積製程，但並不以此為限。
每一貫通電極18的周圍，係可形成一內襯墊21以及一外襯墊20，以當作在貫通電極18與半導體基底11之間的絕緣膜。在一些實施例中，內襯墊21以及外襯墊20係可形成如一圓形柱、一正方形柱，或者是一多邊形柱。在一些實施例中，內襯墊21係可由非等向性蝕刻而形成在半導體基底11上。在一些實施例中，外襯墊20係可由氧化矽銅擴散到膜層11a。當形成一容室時，外襯墊20係可當作膜層11a的一保護膜之功能，其係將在本揭露中於後文進行詳述。
圖2為結構示意圖，例示本揭露一些實施例的半導體裝置10中的一個貫通電極18之一部分。貫通電極18係可經由半導體基底11的膜層11a及膜層11b所形成。在一些實施例中，從半導體基底11突伸的一後凸塊19，係由乾蝕刻所暴露。在一些實施例中，貫通電極18在半導體基底11之膜層11a中的部份之一截面寬度(cross-sectional width)，係可小於後凸塊19的一截面寬度。在一些實施例中，外襯墊20係可形成在半導體基底11之膜層11a內。在一些實施例中，內襯墊21係可延伸到每一後凸塊19的一側表面。在一些實施例中，內襯墊21的一部份係位在後凸塊19的側表面上，以當作一側壁間隙子。在一些實施例中，內襯墊21係可包括直接接觸外襯墊20且由氮化矽所製的一膜層21a，以及直接接觸與半導體基底11中之貫通電極18且由氧化矽所製的一膜層21b。內襯墊21係可延伸到後凸塊19的側表面的至少一部份。因此，導電的貫通電極18係可包括一第一電極部、一第二電極部，以及一第三電極部，第一電極部係穿經一半導體基底(例如膜層11a)，第二電極部係從第一電極部垂直地突伸，第三電極部(後凸塊)19係從第二電極部橫向地突伸。因此，係在第二電極部、第三電極部，以及半導體基底之間係形成一間隙(gap)，且形成來將貫動電極18與膜層11a絕緣的絕緣膜(11b、20、21a、21b)係包括一第一膜部、一第二膜部，以及一第三膜部，第一膜部係位在貫通電極18的第一電極部與半導體基底(或膜層11a)之間，第二膜部係在貫通電極18的第二電極部、第三電極部，以及半導體基底之間的間隙中；而當留下未被覆蓋之第三電極部的側表面的一剩餘部份時，第三膜部(對應膜層21a與膜層21b的部份)係從第二膜部突伸，以覆蓋第三電極部之一側表面的一部份。
圖3至圖15為剖視示意圖，例示本揭露一些實施例的半導體裝置10之製造過程中的結構。參考圖3，半導體裝置10係可包括一半導體基底11、一元件區12以及一障壁膜22，半導體基底11係包括膜層11a、11c以及在膜層11a、11c之間的膜層11b。在一些實施例中，元件區12係可形成在膜層11a的一表面上，膜層11a的該表面係相對直接接觸膜層11b的一表面。在一些實施例中，膜層11a的一厚度係可接近2.5μm，膜層11b的一厚度係可接近20μm，而元件區12的一厚度係可接近20μm。在一些實施例中，障壁膜22係可形成在元件區12上。障壁膜22係可作為防銅擴散膜以及作為一蝕刻終止膜。在一些實施例中，障壁膜22係可包括氮化矽、碳化矽，但並不以此為限。
參考圖4，用於形成貫通電極18的乾蝕刻係可經由障壁膜22、元件區12以及膜層11a來實現。因此，用於貫通電極18的一開口18'係可藉由一乾蝕刻方法經由障壁膜22、元件區12以及膜層11a來形成。在一些實施例中，當鋪開膜層11a時，一波希法(Bosch method)係可用於乾蝕刻。在一些實施例中，六氟化硫(SF6 )氣體係可用於乾蝕刻，八氟環丁烷(C4 F8 )氣體係可用於聚合物沉積。在一些實施例中，貫通電極係可由如圖4的中間通孔方法所形成，或者是其他製程，例如一先通孔方法。
'參考圖5，在一些實施例中，外襯墊20係可為一氧化矽層，且在接近350至500°C進行沉積。外襯墊20的一厚度係可為1μm。在此製程中，係可使用一氧化矽模或一層壓膜，而層壓膜係包括一氧化矽層以及一氮化矽層。在一些實施例中，層壓膜係可包括具有接近0.3μm厚度的氧化矽層以及具有接近0.7μm厚度的氮化矽層。在一些實施例中，層壓膜係可包括具有接近0.7μm厚度的一氧化矽層以及具有接近0.3μm厚度的一氮化矽層，但並不以此為限。
參考圖6，為了暴露在開口18'下方的膜層11c，外襯墊20面對在開口18'底部之半導體基底11的膜層11b之一部份，以及膜層11b位在開口18'底部下方的一部份，係藉由蝕刻而鋪開。在一些實施例中，係可藉由使用一或多個氣體之結合的非等向性乾蝕刻方法來實現開口18'的形成，而一或多個氣體之結合係例如四氟甲烷(CF4 )氣體、八氟環丁烷(C4 F8 )氣體、六氟丁二烯(C4 F6 )氣體、八氟環戊烯(C5 F8 )氣體、氧氣、一氧化碳氣體、氬氣等等，但並不以此為限。在一些實施例中，係可藉由使用障壁膜22當作用於蝕刻的終止物的非等向性乾蝕刻，來移除在障壁膜22上的外襯墊20。在貫通電極18之一側壁上的外襯墊20係可殘留(remain)在膜層11a中。
參考圖7，在一些實施例中，係可藉由一非等向性濕蝕刻對已暴露的膜層11c進行蝕刻。在一些實施例中，為了形成具有接近2μm到5μm之深度的多個容室19'，非等向性濕蝕刻係可使用一氫氧化鉀基溶液。在非等向性濕蝕刻中，係可藉由在膜層11c中使用不同的蝕刻速度，來形成用於後凸塊19之具有一梯形體(trapezoid body)的該等容室19'。因此，該等容室19'的每一容室19'係可具有一斜側壁，且每一後凸塊19係可朝相對開口18'的一側逐漸變細，以形成後凸塊19的一斜側表面。在一些實施例中，用於蝕刻以形成該等容室19'，係可使用一等向性濕蝕刻方法或是一等向性乾蝕刻方法來取代非等向性乾蝕刻方法。在一些實施例中，該等容室19'的形狀係可取決於蝕刻方式而有所不同。外襯墊20係可殘留在開口18'的側壁上。
參考圖8，在一些實施例中，內襯墊21係可為一層壓膜，層壓膜係位在一氮化矽膜上，且層壓膜係為厚度0.3μm的一氧化矽膜，而氮化矽膜係具有0.2μm的厚度，且由原子層沉積方法所形成。當將銅填滿在開口18'與容室19'中時，氮化矽膜係可避免銅擴散到矽層。在一些實施例中，氮化矽膜的一厚度係可足夠小，以避免在貫通電極18與一鄰近貫通電極之間的寄生電容增加。在一些實施例中，氧化矽膜係可被形成來補足氮化矽膜的厚度。在一些實施例中，氧化矽膜係可低於氮化矽膜，以避免銅擴散，然而，氧化矽膜係可高於氮化矽膜，以避免寄生電容。
參考圖9，在一些實施例中，一導電材料係可由銅電鍍所填滿。在一些實施例中，於應用原子層沉積以傳入在開口18'與容室19'的一內壁上的一障壁層23a(例如鉭及/或氮化鉭)以及一晶種層23b(例如銅)之後，係可藉由向上式銅電鍍方法以實施銅電鍍。在一些實施例中，係可使用電子束誘發沉積、銅沉積、或者是熔化金屬填充來取代向上式銅電鍍方法。
參考圖10，在一些實施例中，在障壁膜22上的銅係可藉由化學機械平坦化而被移除。在一些實施例中，內襯墊21的一部份係可殘留在障壁膜22上，以覆蓋元件區12。因此，係可形成貫通電極18以填滿開口18'及容室19'。
參考圖11，在一些實施例中，一配線區13係可形成在元件區12上之障壁膜22之上。一可圖案化保護層28b以及包括一障壁層(例如具有15nm厚度的一鈦層與一晶種層(例如具有200nm厚度的一銅層)的障壁-晶種層)28a，係可形成在配線區13的一頂表面上。在形成用於一些前凸塊的一光阻24之後，在光阻24上的一前凸塊形成區係可被打開，以暴露障壁-晶種層28a。在一些實施例中，光阻24的一厚度係可接近50μm，但本揭露並不以此為限。
參考圖12，前凸塊16係可在已暴露的障壁-晶種層28a上藉由銅電鍍所形成。在一些實施例中，從銅電鍍所形成之前凸塊的一厚度，係可接近10μm。在一些實施例中，於銅電鍍之後，連接層17係可被連續地圖案化，並可藉由旋轉塗佈、化學氣相沉積製程，或者是物理氣相沉積製程所形成，但本揭露並不以此為限。連接層17係可包括一可圖案化材料17a，而可圖案化材料17a係包含多個導電粒子17B，且可圖案化材料17a係可具有18μm的一厚度。在一些實施例中，可圖案化材料17a係可為可圖案化，且可形成在前凸塊16上，而導電粒子17b係包括銅、鎳、金、或者是銀，但本揭露並不以此為限。於使用電漿灰化與一氨氣成份的溶液移除光阻24之後，係可在使用前凸塊當作一遮罩時，用一磷酸溶液將已暴露的障壁-晶種層28a進行移除。
參考圖13，在一些實施例中，半導體裝置10係可垂直地被翻轉。前凸塊16係可透過抗熱黏合材料25而黏接到暫時載體27。
參考圖14，在一些實施例中，已暴露的膜層11c係可藉由晶背研磨及/或化學機械平坦化所移除，但本揭露並不以此為限。在一些實施例中，為了保護膜層11c不會從貫通電極18而來的銅汙染，用以移除之已暴露的膜層11c的部分之一厚度，係可被控制來保護貫通電極18避免被暴露。因此，在移除半導體基底11的一部份(例如膜層11c)之後，一殘留的矽層26係可殘留下來。殘留的矽層26係可覆蓋該等後凸塊19。
參考圖15，在一些實施例中，係可移除在膜層11b上之殘留的矽層26。在一些實施例中，使用六氟化硫氣體成份的乾蝕刻，對膜層11b與內襯墊21具有接近20到50蝕刻選擇比。在一些實施例中，圍繞後凸塊19的內襯墊21係可用一蝕刻氣體進行蝕刻，以暴露後凸塊19。在一些實施例中，蝕刻氣體係可為氟碳氣體與惰性氣體的一氣體混合物。內襯墊21與障壁層23a的蝕刻係可被執行，直至後凸塊19暴露。在一些實施例中，後凸塊19係藉由非等向性蝕刻而暴露。因此，當內襯墊21的一部分可殘留在後凸塊19上時，每一後凸塊19的一頂表面係可完全地暴露。於後凸塊19暴露之後，係可執行例如包含腐蝕抑制劑之鹼金屬溶液的後處理，以避免銅腐蝕並移除一蝕刻殘存物。
因此，本揭露一些實施例的半導體裝置的貫通電極，係可由以下的方法所形成：提供一基底11，基底11包括一半導體膜層11a、一犧牲層11c，以及一絕緣層，而絕緣膜層11b係位在半導體膜層11a與犧牲膜層11c之間；形成貫穿半導體膜層11a與絕緣膜層11b的一開口18'；對犧牲膜層11c進行蝕刻，以在犧牲膜層11c形成一容室19'；在開口18'與容室19'塗上一導電材料23，以形成具有一後凸塊19(例如第一凸塊)的一貫通電極18；以及暴露後凸塊19的一部分。接下來，一前凸塊(例如一第二凸塊)16係形成在貫通電極18相對後凸塊19之一端上。再者，一連接層17係圖案化在前凸塊16上。在一些實施例中，連接層17是可圖案化的，且包括一可圖案化材料17a，可圖案化材料17a係包含多個導電粒子17b。在一些實施例中，可圖案化材料17a係包括感光材料。在一些實施例中，感光材料係為一光阻或聚亞醯胺。在一些實施例中，該等導電粒子17b係包括銅、鎳、金、或是銀。在一些實施例中，連接層17係可由下列方式所形成：旋轉塗佈、化學氣相沉積製程、或是物理氣相沉積製程。
圖16為示意圖，例示本揭露一些實施例之電子單元100的一對堆疊半導體裝置10、10"的貫通電極。圖16顯示每一後凸塊19係物理上經由連接層17而連接到前凸塊16之後的示意圖。在一些實施例中，後凸塊19的一截面寬度係可大於前凸塊16的一截面寬度。為了降低流動性所造成的缺陷，流動性係可造成可圖案化材料17a朝向後凸塊19的一側壁移動並從可圖案化材料17a落下，則後凸塊19的截面寬度係設計為大於前凸塊16的截面寬度。
再者，本揭露的一目的係在於提供一電子單元。電子單元100(如圖16所示)係包括至少二上述的半導體裝置10、10"。一半導體裝置10"之導電貫通電極18"的第三電極部19"係經由連接層17而電性地連接到另一半導體裝置10的前凸塊16。連接層17係為可圖案化的。意即，如上之二相鄰的半導體裝置10、10"，係經由連接層17而可電性地相互連接，其中連接層17係為可圖案化的，且包括一可圖案化材料17a，而可圖案化材料17a係包含多個導電粒子17B。在一些實施例中，該等導電粒子17b係包括銅、鎳、金、或是銀。在一些實施例中，連接層17係可由下列方式所形成：旋轉塗佈、化學氣相沉積製程、或是物理氣相沉積製程。
本揭露之一實施例提供一種半導體結構。該半導體結構包括：一半導體基底、一導電貫通電極、一絕緣膜、一凸塊，以及一連接層，其中該連接層包括一可圖案化材料，而該可圖案化材料係包含有多個導電粒子。該導電貫通電極係貫穿該半導體基底。該絕緣膜係圍繞該導電貫通電極且使該導電貫通電極與該半導體基底電性地絕緣。該凸塊係設置在該導電貫通電極上。該連接層係設置在該凸塊上。
本揭露的一目的係在於提供一電子單元。電子單元包括至少二上述的半導體裝置。其中一半導體裝置之導電貫通電極的第三電極部係經由連接層而電性地連接到另一半導體裝置的前凸塊。連接層係可圖案化在另一半導體裝置的凸塊上。
雖然已詳述本揭露及其優點，然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，並且以其他製程或其組合替代上述的許多製程。
再者，本申請案的範圍並不受限於說明書中之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
10:半導體裝置 10":半導體裝置 11:半導體基底 11a:膜層 11b:膜層 11c:膜層 12:元件區 13:配線區 14:電路元件 15:線路 16:前凸塊 17:連接層 17a:可圖案化材料 17b:導電粒子 18:貫通電極 18':開口 18":貫通電極 19:後凸塊 19':容室 19":第三電極部 20:外襯墊 21:內襯墊 21a:膜層 21b:膜層 22:障壁膜 23:導電材料 23a:障壁層 23b:晶種層 24:光阻 25:抗熱黏合材料 26:殘留的矽層 27:暫時載體 28a:障壁-晶種層 28b:可圖案化保護層 100:電子單元
參閱實施方式與申請專利範圍合併考量圖式時，可得以更全面了解本申請案之揭示內容，圖式中相同的元件符號係指相同的元件。 圖1為結構示意圖，例示本揭露一些實施例的半導體裝置的多個貫通電極。 圖2為結構示意圖，例示本揭露一些實施例的半導體裝置的一個貫通電極之一部分。 圖3至圖15為剖視示意圖，例示本揭露一些實施例的半導體裝置之製造過程中的結構。 圖16為剖視示意圖，例示本揭露一些實施例之電子單元的一對堆疊半導體裝置的貫通電極。
10:半導體裝置
11:半導體基底
11a:膜層
11b:膜層
12:元件區
13:配線區
14:電路元件
15:線路
16:前凸塊
17:連接層
17a:可圖案化材料
17b:導電粒子
18:貫通電極
19:後凸塊
20:外襯墊
21:內襯墊
22:障壁膜

Claims (20)

  1. 一種半導體結構，包括： 一半導體基底； 一導電貫通電極，係貫穿該半導體基底； 一絕緣膜，係圍繞該導電貫通電極且使該導電貫通電極與該半導體基底電性地絕緣； 一凸塊，設置在該導電貫通電極上；以及 一連接層，設置在該凸塊上； 其中該連接層包括一可圖案化材料，而該可圖案化材料係包含有多個導電粒子。
  2. 如請求項1之半導體結構，其中該可圖案化材料係包括感光材料。
  3. 如請求項2之半導體結構，其中該感光材料係為光阻或聚亞醯胺。
  4. 如請求項1之半導體結構，其中該等導電粒子係為銅、鎳、金、或是銀。
  5. 如請求項1之半導體結構，其中該連接層係由下列方式所形成：旋轉塗佈、化學氣相沉積製程、或是物理氣相沉積製程。
  6. 如請求項1之半導體結構，其中該導電貫通電極包括： 一第一電極部，係位在該半導體基底中； 一第二電極部，係從該第一電極部垂直地突伸；以及 一第三電極部，係從該第二電極部橫向地突伸，該第三電極部包括一側表面，以界定出該第三電極部的一寬度。
  7. 如請求項6之半導體結構，其中該導電貫通電極的該第三電極部係漸縮而呈錐形，以斜向的方式形成該第三電極部的該側表面。
  8. 如請求項7之半導體結構，其中該導電貫通電極的該第三電極部係朝向與該導電貫通電極之該第一電極部相對的一側而漸縮而呈錐形。
  9. 如請求項8之半導體結構，其中該導電貫通電極之該第二電極部的一寬度，係大致與該導電貫通電極之該第一電極部的一寬度相同，且該導電貫通電極之該第三電極部的該寬度，係大於該第一電極部的該寬度與該第二電極部的該寬度。
  10. 如請求項6之半導體結構，其中該第二電極部、該第三電極部以及該半導體基底之間，係形成一間隙。
  11. 如請求項6之半導體結構，其中該導電貫通電極的該第一電極部、該第二電極部以及該第三電極部係由相同材料所形成。
  12. 如請求項10之半導體結構，其中該絕緣膜係包括： 一第一膜部，係位於該第一電極部與該半導體基底之間； 一第二膜部，係位在該間隙中；以及 一第三膜部，係從該第二膜部突伸，以覆蓋該第三電極部之該側表面的一部份。
  13. 如請求項12之半導體結構，其中該第三電極部之該側表面的一剩餘部份係並未被該第三膜部所覆蓋。
  14. 如請求項12之半導體結構，其中該絕緣膜的該第一膜部在該導電貫通電極的該第一電極部與該半導體基底之間係具有一第一厚度，該絕緣膜的該第二膜部在該導電貫通電極的該第二電極部與該半導體基底之間係具有一第二厚度，而該第二厚度係大於該第一厚度。
  15. 如請求項14之半導體結構，其中該絕緣膜的該第三膜部係從該絕緣膜的該第二膜部突伸而具有一第三厚度，以覆蓋該導電貫通電極之該第三電極部的該側表面之該部份，該第三厚度係小於該絕緣膜之該第二膜部的該第二厚度。
  16. 如請求項12之半導體結構，其中該絕緣膜的該第一膜部係包括一第一絕緣層以及一第一絕緣襯墊，該絕緣膜的該第二膜部係包括一第二絕緣層以及一第二絕緣襯墊，該絕緣膜的該第三膜部係包括一第三絕緣襯墊，而該第二絕緣襯墊係與該第一絕緣襯墊及該第三絕緣襯墊是連續的。
  17. 如請求項16之半導體結構，其中該絕緣膜的該第一膜部係包括一第四絕緣襯墊，該第四絕緣襯墊係位在該第一絕緣襯墊與該導電貫通電極的該第一電極部之間，該絕緣膜的該第二膜部係包括一第五絕緣襯墊，該第五絕緣襯墊係位在該第二絕緣襯墊與該導電貫通電極的該第二電極部之間，該絕緣膜的該第三膜部係包括一第六絕緣襯墊，該第六絕緣襯墊係位在該第三絕緣襯墊與該導電貫通電極的該第三電極部之間，且該第五絕緣襯墊係與該第四絕緣襯墊及該第六絕緣襯墊是連續的。
  18. 如請求項17之半導體結構，其中該第一絕緣層在該第一絕緣襯墊與該半導體基底之間具有一第一厚度，該第二絕緣層在該導電貫通電極之該第三電極部與該半導體基底之間具有一第二厚度，而該第二厚度係大於該第一厚度。
  19. 如請求項17之半導體結構，其中該第一絕緣襯墊、該第二絕緣襯墊以及該第三絕緣襯墊包括有一氮化矽膜，且該第五絕緣襯墊、該第五絕緣襯墊以及該第六絕緣襯墊係包括有一氧化矽膜。
  20. 如請求項19之半導體結構，其中該氮化矽膜係比該氧化矽膜更厚。
TW108110085A 2018-12-07 2019-03-22 半導體裝置 TW202023031A (zh)

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