TWI763246B - 半導體封裝的製備方法 - Google Patents

半導體封裝的製備方法 Download PDF

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TWI763246B
TWI763246B TW110100999A TW110100999A TWI763246B TW I763246 B TWI763246 B TW I763246B TW 110100999 A TW110100999 A TW 110100999A TW 110100999 A TW110100999 A TW 110100999A TW I763246 B TWI763246 B TW I763246B
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die
layer
section
redistribution layer
conductive
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TW202145377A (zh
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施信益
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南亞科技股份有限公司
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Abstract

本揭露提供一種半導體封裝及其製備方法。該半導體封裝具有一第一晶粒、一第二晶粒、複數個導電栓塞以及一重分佈層。該重分佈層具有一第一區段以及一第二區段，該第二區段與該第一區段為電性絕緣。該重分佈層的該第一區段電性連接該第一晶粒到該第二晶粒，且該重分佈層的該第二區段電性連接該第一晶粒到該等導電栓塞。

Description

半導體封裝的製備方法
本申請案主張2020年2月19日申請之美國正式申請案第16/795,006號的優先權及益處，該美國正式申請案之內容以全文引用之方式併入本文中。
本揭露係關於一種半導體元件及該半導體元件的製備方法。特別是有關於一種半導體封裝及該半導體封裝的製備方法，其中該半導體封裝具有多個堆疊半導體晶粒以及多個直通模封穿孔(through molding vias)。
當積體電路技術持續進步時，其係正在進行不斷的努力以提高效能和密度。設計者為實現這些好處而探索出的一種方法，係實施堆疊式三維積體電路。三維積體電路適於考慮的的一些區域係包括二或多個晶片的堆疊，而二或多個晶片的堆疊係使用相同或不同製造程序進行製造，以降低積體電路系統的佔據面積(footprint)。
上文之「先前技術」說明僅係提供背景技術，並未承認上文之「先前技術」說明揭示本揭露之標的，不構成本揭露之先前技術，且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露之一實施例提供一種半導體封裝。該半導體封裝包括一第一晶粒、一第二晶粒、複數個導電栓塞以及一重分佈層。該重分佈層包括一第一區段以及一第二區段，該第二區段與該第一區段電性絕緣。該重分佈層的該第一區段電性連接該第一晶粒到該第二晶粒，且該重分佈層的該第二區段電性連接該第一晶粒到該等導電栓塞。
在本揭露的一些實施例中，該第一晶粒堆疊在該第二晶粒與該等導電栓塞上。
在本揭露的一些實施例中，該重分佈層的該第一區段設置在該第一晶粒與該第二晶粒之間，且該重分佈層的該第二區段設置在該第一晶粒與該等導電栓塞之間。
在本揭露的一些實施例中，該重分佈層的該第二區段圍繞該重分佈層的該第一區段。
在本揭露的一些實施例中，該等第二晶粒水平地配置以平行該等導電栓塞。
在本揭露的一些實施例中，該半導體封裝還包括：一介電層，包住該重分佈層；一第一隔離材料，圍繞該第一晶粒；以及一第二隔離材料，圍繞該第二晶粒與該等導電栓塞。
在本揭露的一些實施例中，該半導體封裝還包括：一鈍化層，覆蓋該第二晶粒與該等導電栓塞；一導電層，穿經該鈍化層，並包括一第一部份以及一第二部份，該第一部份連接到該第二晶粒，該第二部份連接到該等導電栓塞；以及複數個焊料凸塊(solder bumps)，貼銲在該導電層上。
本揭露之另一實施例提供一種半導體封裝組件的製備方 法。該製備方法的步驟包括提供水平設置的複數個第一晶粒；形成一重分佈層以電性連接到該等第一晶粒，其中該重分佈層劃分成一第一區段以及一第二區段，該第二區段與該第一區段係電性絕緣；安裝複數個第二晶粒在該重分佈層的該第一區段上；沉積一第二隔離材料在該等第二晶粒與該重分佈層上；以及形成複數個導電栓塞以穿經該第二隔離層，並接觸該重分佈層的該第二區段。
在本揭露的一些實施例中，該製備方法還包括：形成至少一介電層以包住該重分佈層。
在本揭露的一些實施例中，該製備方法還包括：沉積一鈍化層在該等第二晶粒、該等導電栓塞以及該第二隔離層上；形成一導電層以穿經該鈍化層，其中該導電層包括一第一部份以及一第二部份，該第一部份電性耦接到該等第二晶粒，該第二部份與該第一部份電性絕緣，並接觸該等導電栓塞；以及形成複數個錫料凸塊以連接到該導電層。
在本揭露的一些實施例中，該製備方法還包括：執行一研磨(grinding)製程，以暴露該等第二晶粒的各導電線，其係在該鈍化層沉積之前執行。
在本揭露的一些實施例中，該第一隔離材料的一熔點(melting point)係大於該第二隔離材料的熔點。
在本揭露的一些實施例中，該等第一晶粒之間具有一第一距離，該等第二晶粒之間具有一第二距離，且該第二距離小於該第一距離。
在本揭露的一些實施例中，該第一區段設置在該重分佈層的中心部位，且該第二區段圍繞該第一區段。
在本揭露的一些實施例中，該等第一晶粒與該等第二晶粒以該半導體封裝的一中心軸而對稱設置。
在本揭露的一些實施例中，該製備方法還包括：在該重分佈層形成之前以一第一隔離材料執行模造該等第一晶粒。
上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
10:半導體封裝
30:製備方法
110:第一晶粒
112:接觸墊
120:第二晶粒
122:接觸墊
124:導電線
130:導電栓塞
140:重分佈層
142:第一區段
144:第二區段
146:介電層
150:第一隔離材料
152:上表面
154:下表面
160:第二隔離材料
170:鈍化層
180:導電層
182:第一部份
184:第二部份
190:錫料凸塊
210:遮罩層
220:開孔
230:開孔
302:步驟
304:步驟
306:步驟
308:步驟
310:步驟
312:步驟
314:步驟
316:步驟
318:步驟
1102:前表面
1104:後表面
D1:第一距離
D2:第二距離
參閱實施方式與申請專利範圍合併考量圖式時，可得以更全面了解本申請案之揭示內容，圖式中相同的元件符號係指相同的元件。
圖1為依據本揭露一些實施例中一種半導體封裝的剖視示意圖。
圖2為依據本揭露一些實施例中一種半導體封裝之製備方法的流程示意圖。
圖3到圖14為依據本揭露一些實施例中在一種半導體封裝的形成中之各個中間階段的剖視示意圖。
本揭露之以下說明伴隨併入且組成說明書之一部分的圖式，說明本揭露之實施例，然而本揭露並不受限於該實施例。此外，以下的實施例可適當整合以下實施例以完成另一實施例。
應當理解，雖然用語「第一(first)」、「第二(second)」、「第三(third)」等可用於本文中以描述不同的元件、部件、區域、層及/或部分，但是這些元件、部件、區域、層及/或部分不應受這些用語所限制。這些用語僅用於從另一元件、部件、區域、層或部分中區分一個元件、部件、區域、層或部分。因此，以下所討論的「第一裝置(firstelement)」、「部件(component)」、「區域(region)」、「層(layer)」或「部分(section)」可以被稱為第二裝置、部件、區域、層或部分，而不背離本文所教示。
本文中使用之術語僅是為了實現描述特定實施例之目的，而非意欲限制本發明。如本文中所使用，單數形式「一(a)」、「一(an)」，及「該(the)」意欲亦包括複數形式，除非上下文中另作明確指示。將進一步理解，當術語「包括(comprises)」及/或「包括(comprising)」用於本說明書中時，該等術語規定所陳述之特徵、整數、步驟、操作、元件，及/或組件之存在，但不排除存在或增添一或更多個其他特徵、整數、步驟、操作、元件、組件，及/或上述各者之群組。
圖1為依據本揭露一些實施例中一種半導體封裝10的剖視示意圖。請參考圖1，半導體封裝10可為一晶圓級(wafer-level)半導體封裝，並包括一或多個第一晶粒110、一或多個第二晶粒120、複數個導電栓塞130以及一重分佈層140，而重分佈層140具有一第一區段142以及至少一第二區段144，而第二區段144與第一區段142為電性絕緣，其中第一區段142電性連接該等第一晶粒110到該等第二晶粒120，且該第二區段144電性連接該等第一晶粒110到該等導電栓塞130。
水平設置的該等第一晶粒110可堆疊在該等第二晶粒120與該等導電栓塞130上，重分佈層140的第一區段142設置在該等第一晶粒 110與該等第二晶粒120之間，且重分佈層140的第二區段144設置在該等第一晶粒110與該等導電栓塞130之間，以降低半導體封裝10的一佔據面積(footprint)。
在一些實施例中，第一晶粒110為一系統上晶片(system-on-chip，SoC)，其係包括一中央處理器(central processing unit，CPU)、一圖形處理單元(graphics processing unit，GPU)、一動態隨機存取記憶體(dynamic random access memory，DRAM)控制器，或其組合。水平設置的該等第二晶粒120可為記憶體晶粒，例如動態隨機存取記憶體(DRAM)晶粒。該等第一晶粒110具有一第一佔據面積，且該等第二晶粒120具有一第二佔據面積，而該第二佔據面積小於該第一佔據面積；因此，該等導電栓塞130可水平設置以平行該等第二晶粒120。在一些實施例中，圍繞該等第二晶粒120的導電栓塞130係以等間隙(equally-spaced)架構進行配置。在一些實施例中，該等第一晶粒110之間具有一第一距離D1，且該等第二晶粒120之間具有一第二距離D2；第一距離S1大於第二距離D2，以促進散熱。
半導體封裝10還可包括一第一隔離材料150以及一第二隔離材料160，第一隔離材料150圍繞該等第一晶粒110，第二隔離材料160圍繞該等第二晶粒120與該等導電栓塞130。在一些實施例中，該等導電栓塞130係穿經第二隔離材料160並接觸重分佈層140的第二區段144，而該等導電栓塞130可具有一高度，係等於或大於該等第二晶粒120的高度。
在一些實施例中，半導體封裝10還可包括一鈍化層170、一導電層180以及複數個錫料凸塊190，而該等錫料凸塊180電性耦接到導 電層180。鈍化層170覆蓋該等第二晶粒120與該等導電栓塞130相對重分佈層140設置的側邊。導電層180穿經鈍化層170，並包括一第一部份182以及一第二部份184，第一部份182實體連接到該等第二晶粒120的各導電線(例如直通係穿孔(through silicon vias))124，第二部份184則實體連接到該等導電栓塞130。
圖2為依據本揭露一些實施例中一種半導體封裝之製備方法30的流程示意圖。圖3到圖14為依據本揭露一些實施例中在一種半導體封裝的形成中之各個中間階段的剖視示意圖。圖3到圖14所示的各階段係亦示意地繪示在圖2中的流程圖。在下列的討論中，圖3到圖14所示的各製造階段係參考圖2所述的處理步驟進行討論。
請參考圖3，依據圖2中的一步驟302，提供以一第一隔離材料150模造一或多個第一晶粒110。由第一隔離材料150包住的該等第一晶粒110係水平設置。第一晶粒110具有一前表面1102以及一後表面1104，而後表面1104係相對前表面1102設置，其係經由第一隔離材料150暴露。在一些實施例中，第一晶粒110可包括複數個接觸墊112，連接到後表面1104。在一些實施例中，第一隔離材料150據以一上表面152以及一下表面154，上表面152與該等第一晶粒110的前表面1102為共面，下表面154與該等第一晶粒110的後表面1104為共面。以第一隔離材料150模造該等第一晶粒110的形成係包括(1)黏著該等第一晶粒110在一暫時載體(temporary carrier)上，其係藉由一黏著層所執行；(2)塗敷一第一隔離材料以圍繞該等第一晶粒110；以及(3)移除黏著層與暫時載體。在一些實施例中，暫時載體可包含矽、陶瓷(ceramics)、金屬或其類似物，且黏著層為暫時性的，且為可剝離(strippable)或易於移除材料，舉例來說，其係可 使用膜(films)、膠帶(tapes)、液態膠(liquid adhesives)。在一些實施例中，舉例來說，第一隔離材料150可使用熱固性模塑料(thermoset molding compounds)在一轉換模壓機(transfer mold press)中所形成。
請參考圖4，依據圖2中一步驟304，至少形成一重分佈層140以連接到該等第一晶粒110的各接觸墊112。重分佈層140可包括複數個金屬層以及彼此堆疊的複數個穿孔(vias)。重分佈層140具有一第一區段142以及至少一第二區段144，第二區段144與第一區段142為電性絕緣。重分佈層140的第二區段144可圍繞重分佈層140的第一區段142。換言之，重分佈層140的第二區段144設置在第一區段142的一周圍(periphery)。重分佈層140可包含鋁、銅、鎢、鈦、氮化鈦或其類似物。
如圖4所示，在一些實施例中，可形成至少一介電層146以包住重分佈層140，進而減少重分佈層140的腐蝕(corrosion)。在一些實施例中，介電層146還可覆蓋該等第一晶粒110的後表面1104以及第一隔離材料150的下表面154。在一些實施例中，重分佈層140遠離該等第一晶粒110的一部份係經由介電層146暴露。在一些實施例中，介電層146的沉積溫度係小於第一隔離材料150的熔點(melting point)，以避免第一隔離材料150斷裂(breaking)。介電層146可包含有機材料或非有機材料(inorganic materials)，有機材料係例如聚亞醯胺(polyimide，PI)，而非有機材料係例如氮化矽或氧化矽。
請參考圖5，依據圖2中一步驟306，提供一或多個第二晶粒120，並安裝在重分佈層140的第一區段142上。據此，位在該等第一晶粒110與該等第二晶粒120之間的重分佈層140的第一區段142，係當成該等第一晶粒110與該等第二晶粒120的一電性內連接。在一些實施例中， 該等第二晶粒120可經由一或多個接觸墊122電性連接到重分佈層140，一或多個接觸墊122係形成在該等第二晶粒120上。在一些實施例中，該等第一晶粒110與該等第二晶粒120係以一中心軸C而對稱設置。
請參考圖6，依據圖2中的一步驟308，在該等第二晶粒120安裝在重分佈層140上之後，塗敷一第二隔離材料160以包住該等第二晶粒120。第二隔離材料160還可覆蓋重分佈層140與介電層146。在一些實施例中，第一隔離材料150與第二隔離材料160可具有不同組成(compositions)，以便第二隔離材料160可在相對較低溫度下固化(cured)。
請參考圖7，依據圖2中的一步驟310，執行一研磨製程(grinding process)，以擦掉該等第二晶粒12與第二隔離材料160的一些部分。據此，暴露該等第二晶粒120的各導電線124。在一些實施例中，研磨製程包括一化學機械研磨(chemical mechanical polishing，CMP)製程及/或濕蝕刻製程。
請參考圖8到圖10，依據圖2中一步驟312，形成複數個導電栓塞130，以穿過第二隔離材料160，並接觸重分佈層140的第二區段144。該等導電栓塞130藉由下列步驟所形成：提供一遮罩層210在第二隔離材料160上(如圖8所示)；執行一蝕刻製程以移除第二隔離材料160未被遮罩層210覆蓋的部份，以形成複數個開孔220(如圖9所示)；以及沉積一導電材料在該等開孔220中(如圖10所示)。如圖8所示，該等第二晶粒120係被遮罩層210所覆蓋。在一些實施例中，舉例來說，在執行蝕刻製程之後，遮罩層210係藉由灰化(ashing)製程或濕式剝除(wet strip)製程而移除。在一些實施例中，導電材料可包含銅、鋁、鎢或其類似物，並藉由使 用一鍍覆(electroplating)製程或一化學氣相沉積(CVD)製程而沉積在該等開孔220中及在第二隔離材料160上。在一些實施例中，在導電材料沉積之後，可執行一平坦化製程，以暴露第二隔離材料160。在一些實施例中，平坦化製程包括一CMP製程及/或一濕蝕刻製程。
請參考圖11，依據圖2中一步驟314，沉積一鈍化層170以覆蓋該等第二晶粒120、該等導電栓塞130以及第二隔離材料160。在一些實施例中，鈍化層170典型地以一低壓CVD製程或一電漿加強CVD製程所沉積。在鈍化層170沉積之後，一平坦化製程係可選擇地執行在鈍化層170上以提供較佳的形貌(topography)，而平坦化製程係使用任何適合的方法，例如一回蝕(etch-back)製程或一CMP製程。
請參考圖12，在鈍化層170沉積之後，複數個開孔230可形成在鈍化層170中，以暴露該等第二晶粒120之相對應的導電線124以及該等導電栓塞130。在一些實施例中，該等開孔230的形成包括：(1)形成一光阻圖案(圖未示)在鈍化層170上，其中光阻圖案界定出一圖案以蝕刻進入鈍化層170；(2)執行一第三蝕刻製程，係使用光阻圖案當作一遮罩，以蝕刻鈍化層170，藉此形成該等開孔230在鈍化層170中；(3)移除光阻圖案。
請參考圖13，依據圖2中的一步驟316，一或多個導電材料沉積在鈍化層170上以及在該等開孔230中，以形成一導電層180。導電層180可劃分成一第一部份182以及一第二部份184，第一部份182實體連接到該等導電縣124，而第二部份184則實體連接到該等導電栓塞130。
請參考圖14，依據圖2中一步驟318，複數個錫料凸塊190沉積在導電層180上。在一些實施例中，該等錫料凸塊190係藉由下列方 式貼銲：初始置放一助銲劑(solder flux)(圖未示)在導電層180上，然後設置該等錫料凸塊190在助銲劑上，而一旦該等錫料凸塊190接觸助銲劑時，可執行一回焊(reflow)以回焊該等錫料凸塊190與助銲劑的材料，進而實體接合該等錫料凸塊190到導電層180。在一些實施例中，導電層180的第一部份182可當作是該等第二晶粒120與該等錫料凸塊190的一電性內連接，而導電層180的第二部份184可當作是導電栓塞130與錫料凸塊190的一電性內連接。
綜上所述，由於半導體封裝10的架構，該等第一晶粒110堆疊在該等第二晶粒120與該等導電栓塞130上，且該等第一晶粒110水平配置，以縮減半導體封裝10的佔據面積(footprint)。
本揭露之一實施例提供一種半導體封裝。該半導體封裝包括一第一晶粒、一第二晶粒、複數個導電栓塞以及一重分佈層。該重分佈層包括一第一區段以及一第二區段，該第二區段與該第一區段電性絕緣。該重分佈層的該第一區段電性連接該第一晶粒到該第二晶粒，且該重分佈層的該第二區段電性連接該第一晶粒到該等導電栓塞。
本揭露之另一實施例提供一種半導體封裝組件的製備方法。該製備方法的步驟包括提供水平設置的複數個第一晶粒；形成一重分佈層以電性連接到該等第一晶粒，其中該重分佈層劃分成一第一區段以及一第二區段，該第二區段與該第一區段係電性絕緣；安裝複數個第二晶粒在該重分佈層的該第一區段上；沉積一第二隔離材料在該等第二晶粒與該重分佈層上；以及形成複數個導電栓塞以穿經該第二隔離層，並接觸該重分佈層的該第二區段。
雖然已詳述本揭露及其優點，然而應理解可進行各種變 化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，並且以其他製程或其組合替代上述的許多製程。
再者，本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
10:半導體封裝
110:第一晶粒
120:第二晶粒
124:導電線
130:導電栓塞
140:重分佈層
142:第一區段
144:第二區段
146:介電層
150:第一隔離材料
160:第二隔離材料
170:鈍化層
180:導電層
182:第一部份
184:第二部份
190:錫料凸塊
D1:第一距離
D2:第二距離

Claims (9)

  1. 一種半導體封裝組件的製備方法，包括：提供水平設置的複數個第一晶粒；形成一重分佈層以電性連接到該等第一晶粒，其中該重分佈層劃分成一第一區段以及一第二區段，該第二區段與該第一區段係電性絕緣；安裝複數個第二晶粒在該重分佈層的該第一區段上；沉積一第二隔離材料在該等第二晶粒與該重分佈層上；以及形成複數個導電栓塞以穿經該第二隔離層，並接觸該重分佈層的該第二區段。
  2. 如請求項1所述之製備方法，還包括形成至少一介電層以包住該重分佈層。
  3. 如請求項1所述之製備方法，還包括：沉積一鈍化層在該等第二晶粒、該等導電栓塞以及該第二隔離層上；形成一導電層以穿經該鈍化層，其中該導電層包括一第一部份以及一第二部份，該第一部份電性耦接到該等第二晶粒，該第二部份與該第一部份電性絕緣，並接觸該等導電栓塞；以及形成複數個錫料凸塊以連接到該導電層。
  4. 如請求項3所述之製備方法，還包括執行一研磨製程，以暴露該等第二晶粒的各導電線，其係在該鈍化層沉積之前執行。
  5. 如請求項1所述之製備方法，其中該等第一晶粒之間具有一第一距離，該等第二晶粒之間具有一第二距離，且該第二距離小於該第一距離。
  6. 如請求項1所述之製備方法，其中該第一區段設置在該重分佈層的中心部位，且該第二區段圍繞該第一區段。
  7. 如請求項1所述之製備方法，其中該等第一晶粒與該等第二晶粒以該半導體封裝組件的一中心軸而對稱設置。
  8. 如請求項1所述之製備方法，還包括在該重分佈層形成之前以一第一隔離材料執行模造該等第一晶粒。
  9. 如請求項8所述之製備方法，其中該第一隔離材料的一熔點(melting point)係大於該第二隔離材料的熔點。
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