TWI722957B - 半導體元件及其製備方法 - Google Patents

半導體元件及其製備方法 Download PDF

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TWI722957B
TWI722957B TW109128136A TW109128136A TWI722957B TW I722957 B TWI722957 B TW I722957B TW 109128136 A TW109128136 A TW 109128136A TW 109128136 A TW109128136 A TW 109128136A TW I722957 B TWI722957 B TW I722957B
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Taiwan
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layer
bonding dielectric
semiconductor component
semiconductor
opening
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TW109128136A
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TW202117967A (zh
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施江林
吳珮甄
張慶弘
丘世仰
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南亞科技股份有限公司
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Abstract

本揭露提供一種半導體元件及其製備方法。該半導體元件具有一半導體部件、一重佈線層、一接合介電質以及一隔離層。該重佈線層設置在該半導體部件上，並電性耦接到該半導體部件。該接合介電質設置在該半導體部件上，以圍繞該重佈線層的一頂部。該隔離層設置在該半導體部件與該接合介電質之間，以圍繞該重佈線層的一底部。

Description

半導體元件及其製備方法
本申請案主張2019年10月28日申請之美國正式申請案第16/665,408號的優先權及益處，該美國正式申請案之內容以全文引用之方式併入本文中。
本揭露係關於一種半導體元件及其製備方法。特別是有關於一種具有接合結構(bonding structure)的半導體元件及其製備方法。
半導體元件係使用在不同的電子應用，例如個人電腦、手機、數位相機，或其他電子設備。半導體元件的製造包含依序沉積不同材料層在一半導體基底上，以及使用微影及蝕刻製程圖案化該等材料層，以在半導體基底上形成微電子部件，包括電晶體、二極體、電阻器及/或電容器。
半導體產業藉由在最小特徵尺寸的持續縮小，以持續改善不同電子部件的積體密度(integration density)，而最小特徵尺寸的持續縮小允許更多部件整合在一給定區域中。發展出占用更小面積之更小的封裝結構，以封裝半導體元件。舉例來說，為了嘗試進一步增加半導體元件的密度，已經在研究包括二或多個微電子部件之堆疊的三維積體電路。
上文之「先前技術」說明僅係提供背景技術，並未承認上文之「先前技術」說明揭示本揭露之標的，不構成本揭露之先前技術，且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露之一實施例提供一種半導體元件。該半導體元件包括一半導體部件、一重佈線層、一接合介電質以及一隔離層。該重佈線層設置在該半導體部件上，並電性耦接到該半導體部件。該接合介電質位在該半導體部件上，並圍繞該重佈線層的一頂部設置。該隔離層位在該半導體部件與該接合介電質之間，以圍繞該重佈線層的一底部設置。
在本揭露的一些實施例中，從一剖視圖所視，該底部具有一第一寬度，而該頂部與該底部為一體成型，並具有一第二寬度，該第二寬度大於該第一寬度。
在本揭露的一些實施例中，該第一寬度在距該半導體組件的距離增加的位置處逐漸增加。
在本揭露的一些實施例中，該隔離層接觸該頂部。
在本揭露的一些實施例中，該接合介電質具有一第一厚度，而該隔離層具有一第二厚度，該第二厚度小於該第一厚度。
在本揭露的一些實施例中，該隔離層包括：一下層膜，位在該半導體部件上；以及一上層膜，位在該下層膜與該接合介電質之間。
在本揭露的一些實施例中，該半導體元件還包括一互連層，包含有至少一金屬墊，並位在該半導體部件與該重佈線層之間，以將該半導體部件電性耦接到該重佈線層，其中該金屬墊具有一材料，該材料不同於該重佈線層的一材料。
在本揭露的一些實施例中，該半導體元件還包括一擴散阻障層，位在該接合介電質與該重佈線層的該頂部之間，以及位在該隔離層與該重佈線層的該底部之間。
本揭露之另一實施例提供一種半導體元件的製備方法。該製備方法包括：形成一互連層在一半導體部件上，其中該互連層包含至少一金屬墊，該至少一金屬墊電性耦接到該半導體部件；沉積一隔離層在該互連層上；沉積一接合介電質在該隔離層上；以及形成一重佈線層，以穿經該接合介電質與該隔離層，並接觸該互連層。
在本揭露的一些實施例中，該重佈線層的形成包括：產生一第一開口在該隔離層中，以暴露該金屬墊的一部份；同時充填該接合介電質的沉積在該第一開口中；產生一第二開口在該接合介電質中，並重新產生該第一開口；以及沉積一導電材料在該第一開口與該第二開口中。
在本揭露的一些實施例中，在該第一開口與該第二開口中之該導電材料的沉積包括：充填一含銅導電材料在該第一開口與該第二開口並溢出，其中該含銅導電材料覆蓋該接合介電質；以及研磨該含銅導電材料以暴露該接合介電質的一頂表面，其中在該含銅導電材料研磨之後，該重佈線層的一頂表面與該接合介電質的該頂表面為共面。
在本揭露的一些實施例中，該隔離層的一頂表面經由該第二開口暴露。
在本揭露的一些實施例中，在該隔離層的區域移除之後，係留下一殘留隔離層，而該互連層與該殘留隔離層的各側壁之間的一夾角係大於90度。
在本揭露的一些實施例中，該半導體元件的製備方法還包 括執行一平坦化製程，以提供具有一大致平面的頂表面之該接合介電質。
在本揭露的一些實施例中，平坦化該接合介電質從5.5μm到3μm。
上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
10:半導體元件
10A:第一半導體元件
10B:第二半導體元件
100:基底
110:半導體部件
120:互連層
130:重佈線層
130A:第一重佈線層
130B:第二重佈線層
132:底部
134:頂部
136:頂表面
140:接合介電質
140A:接合介電質
140B:接合介電質
142:頂表面
144:側壁
150:隔離層
151:隔離層
152:上層膜
153:上層膜
154:下層膜
155:下層膜
156:頂表面
157:側壁
158:頂表面
160:擴散阻障層
162:頂表面
20:半導體元件組件
210:第一開口
220:第一蝕刻遮罩
230:第二蝕刻遮罩
240:第二開口
250:導電材料
300:製備方法
302:步驟
304:步驟
306:步驟
308:步驟
310:步驟
312:步驟
314:步驟
316:步驟
318:步驟
ILD1:介電材料
ILD2:介電材料
ILD3:介電材料
M1:金屬墊
M2:金屬墊
M3:金屬墊
T1:厚度
T2:厚度
T3:厚度
V1:通孔
V2:通孔
V3:通孔
W1:第一寬度
W2:第二寬度
θ:夾角
參閱實施方式與申請專利範圍合併考量圖式時，可得以更全面了解本申請案之揭示內容，圖式中相同的元件符號係指相同的元件。
圖1為依據本揭露一實施例中一種半導體元件的剖視示意圖。
圖2為依據本揭露一實施例中一種半導體元件組件的剖視示意圖。
圖3為依據本揭露一實施例中一種半導體元件之製備方法的流程示意圖。
圖4到圖12為依據本揭露一實施例中半導體元件的製備方法之中間階段的剖視示意圖。
現在使用特定語言描述附圖中所繪示的本揭露之實施例或例示。應當理解，在此並非意指限制本揭露的範圍。所描述的實施例的任何改變或修改，以及本文中所描述的原理的任何進一步應用，都被認為 是通常發生在與本揭露內容相關的所屬技術領域中具有通常知識者其中之一。在整個實施例中可以重複使用參考元件編號，但這不一定意味著一個實施例的特徵適用於另一實施例，即使它們共享相同的參考元件編號。
應當理解，儘管這裡可以使用術語第一，第二，第三等來描述各種元件、部件、區域、層或區段(sections)，但是這些元件、部件、區域、層或區段不受這些術語的限制。相反，這些術語僅用於將一個元件、組件、區域、層或區段與另一個區域、層或區段所區分開。因此，在不脫離本發明進部性構思的教導的情況下，下列所討論的第一元件、組件、區域、層或區段可以被稱為第二元件、組件、區域、層或區段。
本文中使用之術語僅是為了實現描述特定實施例之目的，而非意欲限制本發明。如本文中所使用，單數形式「一(a)」、「一(an)」，及「該(the)」意欲亦包括複數形式，除非上下文中另作明確指示。將進一步理解，當術語「包括(cormprises)」及/或「包括(comprising)」用於本說明書中時，該等術語規定所陳述之特徵、整數、步驟、操作、元件，及/或組件之存在，但不排除存在或增添一或更多個其他特徵、整數、步驟、操作、元件、組件，及/或上述各者之群組。
圖1為依據本揭露一實施例中一種半導體元件10的剖視示意圖。請參考圖1，半導體元件10包括一基底100、一或多個半導體部件(semiconductor components)110、一互連層(interconnect layer)120、一重佈線層(re-routing layer)130、一接合介電質(bonding dielectric)140以及一隔離層(insulating layer)151；一或多個半導體部件110位在基底100中，互連層120設置在半導體部件110上，重佈線層130接觸互連層120，接合介電質140位在互連層120上，而隔離層151位在互連層120與接 合介電質140之間，以圍繞重佈線層130。
在一些實施例中，基底100為由矽所製的一半導體基底。在其他實施例中，基底100可包含其他半導體材料，例如III-V族半導體材料。半導體部件110可包括多個摻雜區、多個絕緣元件(isolation features)以及不同層，其並不會分開說明，而是組合在一起形成不同的微電子元件，例如金屬氧化半導體(MOS)部件。
藉由嵌置在介電材料ILD1、ILD2、ILD3中交錯疊置的金屬墊M1、M2、M3以及通孔V1、V2、V3的方法，重佈線層130經由互連層120而電性耦接到半導體部件110。在一些實施例中，重佈線層130包括一底部132以及一頂部134，底部132接觸互連層120，且隔離層151圍繞底部132設置，而頂部134與底部132為一體成型，且接合介電質140圍繞頂部134設置。在一些實施例中，從剖視圖所視，底部132具有一第一寬度W1，且頂部134具有一第二寬度W2，而第二寬度W2大於第一寬度W1。在一些實施例中，第一寬度W1在距半導體組件110的距離減小的位置處逐漸減小，而第二寬度W2為一大致一致的寬度。在一些實施例中，隔離層150接觸頂部134。
在一些實施例中，由含銅材料所製的重佈線層130容易擴散；因此一擴散阻障層160至少鋪設在重佈線層130與接合介電質140之間以及重佈線層130與隔離層1151之間。擴散阻障層160亦可鋪設在重佈線層130與互連層120之間。在一些實施例中，擴散阻障層160的一頂表面162與重佈線層130的一頂表面136等高，其係與接合介電質140的一頂表面142為共面。耐火金屬(例如鈦或鉭)、耐火氮化金屬(例如氮化鈦或氮化鉭)以及耐火氮化矽金屬(例如氮化矽鈦或氮化矽鉭)係典型地使用於擴散 阻障層160。
在例示的實施中，位在隔離層151上的接合介電質140具有一第一厚度T1，而隔離層151具有一第二厚度T2，第二厚度T2小於第一厚度T1。隔離層150具有一單一層或者是一堆疊層結構，並具有一氮化矽膜。在此實施例中，隔離層151具有一上層膜153以及一下層膜155，上層膜153為氮化矽，並接觸接合介電質140，而下層膜155未在互連層120與上層膜153之間。在一些實施例中，上層膜153可具有一蝕刻率，係不同於下層膜154的蝕刻率，以產生重佈線層130之大致無空孔(void-free)的底部132。在一些實施例中，下層膜155包含氧化物，例如氧化矽。
在一些實施例中，可調整上層膜153與下層膜155的厚度，以終止在基底100與含有矽的下層膜154之界面(interface)處的矽原子懸空鍵結(dangling bond)。詳而言之，在氧化矽之下層膜154與矽界面之基底100的界面處之矽原子懸空鍵結，係與導入在氮化矽之上層膜152的氫原子接合(bonded)，或是由導入在氮化矽之上層膜152的氫原子所終止(terminated)。在一些實施例中，重佈線層130與接合介電質140當作是一接合層(bonding layer)，以促進與其他半導體元件10的接合。
圖2為依據本揭露一實施例中一種半導體元件組件20的剖視示意圖。請參考半導體元件組件20包括二半導體元件，具有一第一半導體元件10A以及一第二半導體元件10B，以前面對前面(front-to-front)架構接合在一起。第一半導體元件10A與第二半導體元件10B的不同層矽可大致類似於如圖1所示的半導體元件10的各層，為了簡潔，則省略該等層的詳細敘述。
在一些實施例中，第二半導體元件10B為上下顛倒設置， 並疊置在第一半導體元件10A上，而第二半導體元件10B係混合接合(hybrid-bonded)至第一半導體元件10A，以成為第一半導體元件10A與第二半導體元件10B之間的物理性與電性連接。不同製程可用於將第一半導體元件10A接合至第二半導體元件10B；在一些實施例中，用於將第一半導體元件10A接合至第二半導體元件10B的該等製程，包括金屬對金屬接合製程(metal-to-metal bonding process)以及介電質對介電質接合製程(dielectric-to-dielectric bonding process)。
在一些實施例中，第一半導體元件10A與第二半導體元件10B係對準以使第一半導體元件10A的一第一重佈線層130A接觸第二半導體元件10B的一第二重佈線層130B，並使第一半導體元件10A的一接合介電質140A接觸第二半導體元件10B的第二接合介電質140B，其中第二重佈線層130B與第一重佈線層130A具有大致相同的形狀。
在第一半導體元件10A與第二半導體元件10B對準之後，係施加熱及/或力以將第一重佈線層130A接合到第二重佈線層130B，並將第一接合介電質140A固化(cure)至第二接合介電質140B；藉此形成半導體元件組件20。
圖3為依據本揭露一實施例中一種半導體元件100之製備方法300的流程示意圖。圖4到圖12為依據本揭露一實施例中半導體元件100之製備方法300的中間階段的剖視示意圖。圖4至圖12所示的各階段亦圖例說明在圖3的流程圖中。在接下來的說明中，圖4至圖12的各製造階段係參考圖3所示的處理步驟進行說明。
請參考圖4，依據圖3中的步驟302，係提供一或多個半導體部件110與一互連層120。該等半導體部件110形成在含有矽的一半導體 基底100中。在一些實施例中，該等半導體部件110使用製程所製，包括沉積(deposition)、蝕刻(etching)、植入(implantation)、微影(photolithography)、回火(annealing)，及/或其他適合製程。再者，舉例來說，該等半導體部件110可與另一半導體部件互連(經由互連層120)，以形成一邏輯元件、一記憶體元件、一輸入/輸出元件、一單晶片(system-on-chip)元件、其他適合類型元件，或其組合。在一些實施例中，在前段(front-end-of-line，FEOL)製程期間，該等半導體部件110可形成在半導體基底100中。
形成在半導體部件110上並電性耦接到半導體部件110的互連層120，具有嵌置在介電材料ILD1、ILD2、ILD3中交錯疊置的金屬墊M1、M2、M3以及通孔V1、V2、V3。在此實施例中，通孔V1接觸半導體部件110，而距半導體部件110最遠的金屬墊M3則經由介電材料ILD3而暴露。在一些實施例中，金屬墊M1、M2、M3可包含鋁或鋁合金。在一些實施例中，介電材料ILD1、ILD2、ILD3包含相同材料或不同材料。介電材料ILD1、ILD2、ILD3可包含氧化矽、氮化矽、氮氧化物(oxynitride)、硼矽玻璃(borosilicate glass，BSG)、低介電常數材料、其他適合材料或其組合。在一些實施例中，金屬墊M1、M2、M3可使用鍍覆製程(plating process)形成，通孔V1、V2、V3可使用化學氣相沉積(CVD)製程形成，而介電材料ILD1、ILD2、ILD3可使用氣相沉積製程形成。
請參考圖5，在一些實施例中，依據圖3中的步驟304，一隔離層150沉積在互連層120上。在一些實施例中，隔離層150的沉積可包括沉積一毯覆下層膜(blanket underlying film)154、以及沉積一毯覆上層 膜(blanket overlying film)152在毯覆下層膜154上，而毯覆下層膜154係接觸金屬墊M3以及距基底100最遠之互連層120的介電材料ILD3。在一些實施例中，在毯覆上層膜152沉積之後，可執行一平坦化製程，以提供毯覆上層膜152一大致平面的頂表面156。在一些實施例中，毯覆下層膜154以及毯覆上層膜152係以低壓化學氣相沉積(CVD)製程或一原子層沉積(atomic layer deposition，ALD)製程進行沉積。在另外的實施例中，毯覆下層膜154以及毯覆上層膜152可使用氣相沉積製程形成。在一些實施例中，毯覆下層膜154包含氧化物，例如氧化矽。毯覆上層膜152包含氮化物，例如氮化矽，以提供半導體元件100一均勻懸空鍵結架構。
請參考圖6，在一些實施例中，依據圖3中的步驟306，形成一第一開口210以暴露互連層120。在一些實施例中，如圖5所示，藉由塗佈在毯覆上層膜152上的一第一蝕刻遮罩220以及執行一第一蝕刻製程，以移除毯覆上層膜152與毯覆下層膜154未被第一蝕刻遮罩220保護的部分，藉以形成第一開口210；據此，金屬墊M3的一或多個部分係經由第一開口210而暴露。在一些實施例中，藉由執行一暴露製程以及一顯影製程(develop process)在完全覆蓋毯覆上層膜152的一第一光阻材料上，以形成第一蝕刻遮罩220。在一些實施例中，使用一乾蝕刻製程、一非等向性濕蝕刻製程或其他適合非等向性製程，蝕刻隔離層150以形成一殘留隔離層151，而第一蝕刻製程可使用多個蝕刻劑(etchants)，以蝕刻毯覆上層膜152與毯覆下層膜154，其中係依據被蝕刻的材料來選擇該等蝕刻劑。
請參考圖6，在一些實施例中，殘留的隔離膜151具有多個側壁157，該等側壁157係經由第一開口210而暴露，而殘留的隔離層151包括未在互連層120上的一上層膜153以及位在互連層120與上層膜153之 間的一下層膜153。在一些實施例中，該等側壁157與互連層120之間的一夾角θ大於90度，以產生一無空孔(void-free)重佈層，進而依序形成在第一開口210中。舉例來說，然後藉由一灰化製程(ashing process)或一濕式剝離製程(wet strip process)，以移除第一蝕刻製程220，其中該濕式剝離製程可化學改變第一蝕刻遮罩220，以使其不再連接到上層膜153。
請參考圖7，在已經移除第一光阻圖案220之後，依據圖3中的步驟308，一接合介電質140係沉積在隔離層151的一頂表面158上以及在第一開口210中。在一些實施例中，接合介電質140係填滿第一開口210。在一些實施例中，在沉積之後，在隔離層150上的接合介電質140具有一初始厚度T3，為5.5μm。
請參考圖8，依據在圖3中的步驟310，平坦化接合介電質140。在一些實施例中，接合介電質140變薄至一厚度T1，為3μm。在一些實施例中，在平坦化製程之後，接合介電質140具有一大致平面頂表面142。在一些實施例中，舉例來說，使用化學機械研磨(CMP)製程以平坦化接合介電質140。接下來，形成一第二蝕刻遮罩230，並圖案化在接合介電質140上。
請參考圖9，在一些實施例中，依據圖3中的步驟312，執行一第二蝕刻製程以移除接合介電質140的區域。在一些實施例中，在第二蝕刻製程之後，移除接合介電質140經由第二蝕刻遮罩230而暴露的該等區域。接合介電質140之該等區域的移除係在接合介電質140中產生一第二開口240，並再產生第一開口220，其係輪流暴露金屬墊M3的一些部分以及殘留的隔離層151之頂表面的一些部分。第二開口240連通第一開口220。然後移除第二蝕刻遮罩230。
請參考圖10，在一些實施例中，依據圖3中的步驟314，一擴散阻障層160沉積在接合介電質140的頂表面142上、接合介電質140的各側壁144上、隔離層151的頂表面158上以及隔離層151的各側壁157上。在一些實施例中，擴散阻障層160亦沉積在互連層120的金屬墊M3與介電材料ILD3上。在一些實施例中，舉例來說，使用物理氣相沉積(PVD)製程形成具有一大致均勻厚度的擴散阻障層160。
請參考圖11，在一些實施例中，依據圖3中的步驟314，一導電材料250沉積在擴散阻障層160(以及金屬墊M3)上。在一些實施例中，不僅填滿第一開口220與第二開口240，而且覆蓋接合介電質140的頂表面142。在一些實施例中，使用一鍍覆製程形成導電材料250。
請參考圖12，在一些實施例中，執行一研磨製程以從接合介電質140的頂表面142移除導電材料250與擴散阻障層160，藉此形成一重佈線層130。因此，完全地形成半導體元件100。
本揭露之一實施例提供一種半導體元件。該半導體元件包括一半導體部件、一重佈線層、一接合介電質以及一隔離層。該重佈線層設置在該半導體部件上，並電性耦接到該半導體部件。該接合介電質位在該半導體部件上，並圍繞該重佈線層的一頂部設置。該隔離層位在該半導體部件與該接合介電質之間，以圍繞該重佈線層的一底部設置。
本揭露之另一實施例提供一種半導體元件的製備方法。該製備方法包括：形成一互連層在一半導體部件上，其中該互連層包含至少一金屬墊，該至少一金屬墊電性耦接到該半導體部件；沉積一隔離層在該互連層上；沉積一接合介電質在該隔離層上；以及形成一重佈線層，以穿經該接合介電質與該隔離層，並接觸該互連層。
雖然已詳述本揭露及其優點，然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，並且以其他製程或其組合替代上述的許多製程。
再者，本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
10:半導體元件
100:基底
110:半導體部件
120:互連層
130:重佈線層
132:底部
134:頂部
136:頂表面
140:接合介電質
142:頂表面
151:隔離層
153:上層膜
155:下層膜
157:側壁
158:頂表面
160:擴散阻障層
162:頂表面
ILD1:介電材料
ILD2:介電材料
ILD3:介電材料
M1:金屬墊
M2:金屬墊
M3:金屬墊
T1:厚度
T2:厚度
V1:通孔
V2:通孔
V3:通孔
W1:第一寬度
W2:第二寬度

Claims (12)

  1. 一種半導體元件，包括：一半導體部件；一重佈線層，設置在該半導體部件上，並電性耦接到該半導體部件；一接合介電質，位在該半導體部件上，並圍繞該重佈線層的一頂部設置；一隔離層，位在該半導體部件與該接合介電質之間，以圍繞該重佈線層的一底部設置；以及一互連層，包含有至少一金屬墊，並位在該半導體部件與該重佈線層之間，以將該半導體部件電性耦接到該重佈線層，其中該金屬墊具有一材料，該材料不同於該重佈線層的一材料。
  2. 如請求項1所述之半導體元件，其中從一剖視圖所視，該底部具有一第一寬度，而該頂部與該底部為一體成型，並具有一第二寬度，該第二寬度大於該第一寬度。
  3. 如請求項2所述之半導體元件，其中該第一寬度在距該半導體部件的距離增加的位置處逐漸增加。
  4. 如請求項2所述之半導體元件，其中該隔離層接觸該頂部。
  5. 如請求項1所述之半導體元件，其中該接合介電質具有一第一厚度， 而該隔離層具有一第二厚度，該第二厚度小於該第一厚度。
  6. 如請求項1所述之半導體元件，其中該隔離層包括：一下層膜，位在該半導體部件上；以及一上層膜，位在該下層膜與該接合介電質之間。
  7. 如請求項1所述之半導體元件，還包括一擴散阻障層，位在該接合介電質與該重佈線層的該頂部之間，以及位在該隔離層與該重佈線層的該底部之間。
  8. 一種半導體元件的製備方法，包括：形成一互連層在一半導體部件上，其中該互連層包含至少一金屬墊，該至少一金屬墊電性耦接到該半導體部件；沉積一隔離層在該互連層上；沉積一接合介電質在該隔離層上；以及形成一重佈線層，以穿經該接合介電質與該隔離層，並接觸該互連層；其中該重佈線層的形成包括：產生一第一開口在該隔離層中，以暴露該金屬墊的一部份；同時充填該接合介電質的沉積在該第一開口中；產生一第二開口在該接合介電質中，並重新產生該第一開口；以及沉積一導電材料在該第一開口與該第二開口中； 其中在該第一開口與該第二開口中之該導電材料的沉積包括：充填一含銅導電材料在該第一開口與該第二開口並溢出，其中該含銅導電材料覆蓋該接合介電質；以及研磨該含銅導電材料以暴露該接合介電質的一頂表面，其中在該含銅導電材料研磨之後，該重佈線層的一頂表面與該接合介電質的該頂表面為共面。
  9. 如請求項8所述之半導體元件的製備方法，其中該隔離層的一頂表面經由該第二開口暴露。
  10. 如請求項8所述之半導體元件的製備方法，其中在該隔離層的區域移除之後，係留下一殘留隔離層，而該互連層與該殘留隔離層的各側壁之間的一夾角係大於90度。
  11. 如請求項8所述之半導體元件的製備方法，還包括執行一平坦化製程，以提供具有一大致平面的頂表面之該接合介電質。
  12. 如請求項11所述之半導體元件的製備方法，其中平坦化該接合介電質從5.5μm到3μm。
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