TWI750009B - 具有矽穿孔插塞的半導體元件及其製備方法 - Google Patents
具有矽穿孔插塞的半導體元件及其製備方法 Download PDFInfo
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- TWI750009B TWI750009B TW110101935A TW110101935A TWI750009B TW I750009 B TWI750009 B TW I750009B TW 110101935 A TW110101935 A TW 110101935A TW 110101935 A TW110101935 A TW 110101935A TW I750009 B TWI750009 B TW I750009B
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- layer
- semiconductor device
- semiconductor wafer
- dielectric layer
- wire
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Abstract
本揭露提供一種半導體元件及其製備方法。該半導體元件包括一基板、一導電部件、一重分佈層、至少一矽穿孔插塞、以及至少一凸塊。該導電部件設置於該基板的一前表面之上,且該重分佈層設置於與該前表面相對的一後表面之上。該矽穿孔插塞穿過該基板並接觸內埋於一絕緣層中的該導電部件。該凸塊接觸該重分佈層和該矽穿孔插塞並作為兩者之間的電性連接。
Description
本申請案主張2020年2月18日申請之美國正式申請案第16/793,069號的優先權及益處,該美國正式申請案之內容以全文引用之方式併入本文中。
本揭露係關於一種半導體元件及其製備方法。特別是關於一種具有矽穿孔插塞(through silicon vias)的半導體元件及其製備方法。
製造更可靠、輕巧、緊密(compact)、快速、多功能、和高效的低成本半導體產品一直是電子工業的重要目標。隨著高度集成半導體產品的發展,輸入/輸出接腳(pin)的數量顯著增加,透過使用具有細間距的矽穿孔插塞來連接半導體晶片的技術已經廣泛地發展,且透過使用這些技術,半導體堆疊結構已被使用於一般應用中。
上文之「先前技術」說明僅係提供背景技術,並未承認上文之「先前技術」說明揭示本揭露之標的,不組成本揭露之先前技術,且上文之「先前技術」之任何說明均不應做為本案之任一部分。
本揭露的一方面提供了一種半導體元件。該半導體元件包括一基板、一導電部件、一重分佈層、至少一矽穿孔插塞、以及至少一凸塊。該導電部件設置於該基板的一前表面之上,且該重分佈層設置於與該前表面相對的一後表面之上。該矽穿孔插塞穿過該基板並接觸該導電部件。該凸塊將該重分佈層連接至該矽穿孔插塞。
在一些實施例中,該矽穿孔插塞包括一導線和包圍(enclosing)該導線的一隔離襯層,且該重分佈層包括複數個水平區段和連接至該些水平區段且設置於該隔離襯層之上的複數個垂直區段。
在一些實施例中, 該半導體元件更包括一介電層,設置於該基板的該後表面和該重分佈層的該些水平區段之間,且設置於該隔離襯層的該外圍和該重分佈層的該些垂直區段之間。
在一些實施例中,部分的該介電層透過該重分佈層的該些水平區段而暴露出來
在一些實施例中, 該半導體元件更包括一覆蓋層,覆蓋該重分佈層的該些水平區段。
在一些實施例中,該覆蓋層的厚度大於該重分佈層和該介電層的厚度。
在一些實施例中,該半導體元件更包括包圍該導電部件的一絕緣層,其中該矽穿孔插塞延伸至該絕緣層中。
本揭露的另一方面提供一種半導體元件的製備方法。該方法包括以下步驟:形成至少一溝槽於一半導體晶圓中;沈積一隔離膜於該溝槽中;沈積一導電材料於該隔離膜上以形成至少一導線於該溝槽中;形成一導電部件於該半導體晶圓的一前表面之上,其中該導電部件電性耦合至該導線;薄化該半導體晶圓直到該半導體晶圓的一後表面位於該隔離膜的一端部表面(end surface)下方,其中該後表面與該前表面相對;形成一金屬層於該半導體晶圓的該後表面之上和該隔離膜透過該半導體晶圓而暴露出來的一外圍之一部分之上;進行一研磨製程以移除部分的該金屬層和該隔離膜直到暴露出該導線;以及形成至少一凸塊以將該金屬層的剩餘部分連接至該導線。
在一些實施例中,該方法包括在形成該凸塊之前進行一圖案化製程以移除部分的該金屬層之步驟。
在一些實施例中,該金屬層之拓撲(topology)跟隨隔離膜的暴露部分和該半導體晶圓的該後表面之拓撲。
在一些實施例中,該金屬層的一厚度介於1 μm至5 μm的範圍之間。
在一些實施例中, 該方法更包括以下步驟:在形成該金屬層之前,沉積一第一介電層於該半導體晶圓的該後表面上和該隔離膜透過該半導體晶圓而暴露出來的該外圍之該部分上;以及在該研磨製程期間移除位於該導線的一端部表面上方之部分的該第一介電層。在此實施例中,該第一介電層具有一實質上均勻的厚度。
在一些實施例中,該第一介電層的一厚度介於0.5 μm至3 μm的範圍之間。
在一些實施例中,該方法更包括以下步驟:沉積一第二介電層於該金屬層上直到該第二介電層的一頂表面位於該導線的一端部表面上方,其中該第二介電層位於該半導體晶圓之上;以及在該研磨製程期間移除位於該導線的該端部表面上方之部分的該第二介電層。在此實施例中,該第二介電層具有一實質上均勻的厚度。
在一些實施例中,該第二介電層的一厚度介於0.5 μm至5 μm的範圍之間。
在一些實施例中,該方法更包括進行一圖案化製程以依序地移除部分的該第二介電層和該金屬層之步驟。
在一些實施例中,該隔離膜的該端部表面和該半導體晶圓的該後表面之間的一距離介於0.5 μm至10 µm的範圍之間。
在一些實施例中,該方法更包括在形成該導電部件的同時,形成一絕緣層以包圍該隔離膜和該導電部件的一外圍。
在一些實施例中,形成該溝槽包括以下步驟:依序地形成一緩衝層和一犧牲層於該半導體晶圓的該前表面上;形成至少一開口穿過該緩衝層和該犧牲層;以及透過該開口蝕刻該半導體晶圓以形成該溝槽,其中在沉積該導電材料之後將該緩衝層和該犧牲層移除,使得該導線的一端部表面位於該半導體晶圓的該前表面上方。
在一些實施例中,薄化該半導體晶圓包括以下步驟:進行一研磨製程以減少該半導體晶圓的一厚度,其中該隔離膜並未在進行該研磨製程之後被暴露出來;以及進行一蝕刻製程以進一步減少該半導體晶圓的該厚度,直到該半導體晶圓的該後表面位於該隔離膜的該端部表面下方。
上文已相當廣泛地概述本揭露之技術特徵及優點,俾使下文之本揭露詳細描述得以獲得較佳瞭解。組成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解,可相當容易地利用下文揭示之概念與特定實施例可做為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解,這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
現在使用特定的語言描述圖式所示之本揭露實施例或示例。應理解的是,此處無意限制本揭露的範圍。所述實施例的任何改變或修改,以及本文所述原理的任何進一步應用,都被視為是本揭露相關技術領域具有通常知識者可思及的。本揭露可能在不同實施例中重複參考符號,但即使它們共用相同的參考符號,也不一定意味著一實施例的部件適用於另一實施例。
應理解的是,儘管本文可以使用用語第一、第二、第三等來描述各種元件、構件、區域、層、或部分,但是這些構件、區域、層、或部分不受到這些用語的限制。相反地,這些用語僅用於區分一個元件、構件、區域、層、或部分與另一個元件、構件、區域、層、或部分。因此,例如,在不脫離本揭露概念的情況下,以下所討論的第一元件、構件、區域、層、或部分可以被稱為第二元件、構件、區域、層、或部分。
本文使用的用語僅出於描述特定示例實施例的目的,並且不用以限制本揭露之概念。如本文所使用的,除非上下文另外明確指出,單數形式的“一(a/an)”和“該”也包括複數形式。應理解的是,在本說明書中使用用語“包括(comprises)”和“包含(comprising)”時指出所述之部件、整數、步驟、操作、元件、或構件的存在,但不排除存在或增加一個或多個其他部件、整數、步驟、操作、元件、構件、或前述之組合。
圖1是根據本揭露一些實施例顯示半導體元件10的剖面圖。參照圖1,半導體元件10包括一基板110、設置於基板110的前表面1102之上的一導電部件140、設置於與前表面1102相對的後表面1104之上的一重分佈層174、一個或多個矽穿孔插塞(through silicon via)190穿過基板110並接觸導電部件140;以及一個或多個凸塊200,將重分佈層174連接至矽穿孔插塞190。
基板110包括晶圓112和設置於晶圓112中的一個或多個主要構件114。導電部件140包括交替堆疊的複數個水平元件142和複數個垂直元件144。矽穿孔插塞190作為導電部件140和凸塊200之間的電性內連接。矽穿孔插塞190包括穿過晶圓112的導線132和包圍導線132的隔離襯層124。重分佈層174包括平行於基板110的後表面1104之複數個水平區段1742,以及設置於隔離襯層124的外圍1226之上的複數個垂直區段1744。換句話說,隔離襯層124將重分佈層174的垂直區段1744與導線132分開。水平區段1742和連接到水平區段1742的垂直區段1744是一體成形的。凸塊200接觸矽穿孔插塞190和重分佈層174的垂直區段1744並作為導線132和重分佈層174之間的電性連接。在半導體元件10中,導線132和凸塊200共同作為導電部件140和重分佈層174的電性連接。
半導體元件10進一步包括一介電層162,其設置於基板110的後表面1104和重分佈層174的水平區段1742之間以及隔離襯層124的外圍1226和重分佈層174的垂直區段1744之間。半導體元件10也包括設置於重分佈層174的水平區段1742上的一覆蓋層184和設置於基板110的前表面1102上並包圍導電部件140的一絕緣層150。
半導體元件10可以透過凸塊200電性連接至外部元件20以形成電子系統。換句話說,凸塊200作為輸入/輸出(I/O)連接,以將半導體元件10電性連接至外部元件20。
圖2是根據本揭露一些實施例顯示半導體元件10的製備方法300之流程圖,且圖3到圖21是根據本揭露一些實施例顯示形成半導體元件10之中間階段剖面圖。圖3至圖21所示的階段也示意性地顯示在圖2的流程圖中。在隨後的討論中,圖3至圖21所示的製造階段將參照圖2所示的製程步驟進行討論。
參照圖3,根據圖2中的步驟S302,形成一緩衝層210和一犧牲層220於一基板100上。基板100包括半導體晶圓111和設置於半導體晶圓111中的一個或多個主要構件114。半導體晶圓111可以由矽製成。可選地或額外地,半導體晶圓111可以包括像是鍺的其他元素半導體材料。在一些實施例中,半導體晶圓111由化合物半導體製成,例如碳化矽、砷化鎵、砷化銦、或磷化銦。在一些實施例中,半導體晶圓111由合金半導體製成,例如矽鍺、碳化矽鍺、磷砷化鎵(gallium arsenide phosphide)、或磷化銦鎵(gallium indium phosphide)。在一些實施例中,半導體晶圓111可以包括磊晶層。例如,半導體晶圓111具有覆蓋塊狀半導體的磊晶層。半導體晶圓111可以包括摻雜有像是硼的p-型摻雜物及/或像是磷或砷的n-型摻雜物的各種摻雜區域(未顯示)。在一些實施例中,可以將像是淺溝槽隔離(shallow trench isolation;STI)部件或矽局部氧化(local oxidation of silicon;LOCOS)部件的隔離部件(未顯示)引入半導體晶圓111中以定義和隔離半導體晶圓111中的各個主要構件114。主要構件114可以形成於由隔離部件所定義的主動區域(未顯示)中。
主要構件114可以包括像是電晶體及/或二極體的主動構件,以及像是電容器、電阻器、或其類似構件的被動構件。使用包括沉積、蝕刻、植入、微影、退火、及/或其他可應用製程的各種製程來形成主要構件114。在一些實施例中,可以在前端(front-end-of-line;FEOL)製程期間形成主要構件114於半導體晶圓111中。
依序地堆疊緩衝層210和犧牲層220於基板100上,其中,緩衝層210防止污染並減輕基板100和犧牲層220間界面處的應力。包括含矽介電質的緩衝層210覆蓋基板100的整個前表面1002。可以使用例如化學氣相沉積(chemical vapor deposition;CVD)製程或熱氧化(thermal oxidation process)製程來形成包括二氧化矽的緩衝層210。換句話說,緩衝層210可以是一沉積層或一氧化層,其中熱生長的氧化物可以比沉積的氧化物包含更高的純度。
覆蓋緩衝層210的犧牲層220作為用於圖案化半導體晶圓111的硬罩幕。犧牲層220可以由包括氮化物的無機材料形成,可以使用CVD製程、物理氣相沉積(physical vapor deposition;PVD)製程、旋塗(spin-coating)製程、或另一種可以形成無機材料的合適製程來形成犧牲層220。例如,在一些實施例中,犧牲層220包括氮化矽。
接下來,將第一光阻罩幕230施加在犧牲層220上。第一光阻罩幕230包括一個或多個窗口232以暴露出部分的犧牲層220。透過對完全覆蓋犧牲層220的光敏材料進行曝光製程和顯影製程來形成第一光阻罩幕230,其中,可以透過旋塗製程將光敏材料施加在犧牲層220上,然後使用軟烤(soft-baking)製程進行乾燥。
參照圖4,根據圖2的步驟S304,透過窗口232依序地蝕刻犧牲層220和緩衝層210以形成穿過犧牲層220和緩衝層210的複數個開口240。從而,部分的半導體晶圓111透過開口240而暴露出來。使用至少一個蝕刻製程形成開口240以移除未被第一光阻罩幕230保護之部分犧牲層220和部分的緩衝層210。應注意的是,蝕刻製程可以使用多種蝕刻劑來蝕刻緩衝層210和犧牲層220,該些蝕刻劑係根據緩衝層210和犧牲層220的材料而選擇的。在使用例如灰化製程或濕剝離製程(wet strip process)進行蝕刻製程之後,移除第一光阻罩幕230。
參照圖5,根據圖2的步驟S306,透過開口240蝕刻基板100以形成複數個溝槽116於基板100中。例如,藉由反應離子刻蝕(reactive ion etching;RIE)製程,透過開口240對基板100進行非等向性乾蝕刻以形成溝槽116於半導體晶圓111中,因此在溝槽116中維持了在開口240中的寬度。在一些實施例中,溝槽116可以具有均勻的寬度,但本揭露不限於此。
參照圖6,根據圖2的步驟S308,形成隔離膜120於基板100的暴露部分上。具有實質上均勻厚度的隔離膜120覆蓋基板100的暴露部分,但不填充溝槽116。隔離膜120優選地包括對半導體晶圓111具有高蝕刻選擇性的材料。在一些實施例中,可以使用熱氧化製程在基板100的暴露部分上生長隔離膜120。在替代實施例中,隔離膜120不僅可以沉積在基板100的暴露部分上,也可以沉積在緩衝層210和犧牲層220的暴露部分上。換句話說,隔離膜120的拓撲跟隨基板100、緩衝層210、和犧牲層220的暴露部分之拓撲。作為示例,隔離膜120包括氧化物、氮化物、氮氧化物、或高介電常數(k)材料,並且可以使用CVD製程、原子層沉積(atomic layer deposition;ALD)製程、或其類似製程來進行沉積。
參照圖7和圖8,根據圖2的步驟S310,形成複數個導線132於塗覆有該隔離膜120的該溝槽116中。導線132的形成包括(1)共形且均勻地沉積導電材料130於隔離膜120上(如圖7所示),直到導電材料130完全填充溝槽116為止,以及(2)進行平坦化製程以移除溢出溝槽116和開口240的導電材料130。參照圖8,導線132穿過緩衝層210和犧牲層220並延伸至基板100中。
導線132可以包括多晶矽或金屬,例如銅、鎢、鋁、銀、金、銦、或其類似物。可以使用CVD製程、PVD製程、ALD製程、或另一種合適的製程來形成導線132。在一些實施例中,可以使用電鍍製程(plating process)形成包括銅的導電材料130於隔離膜120上。平坦化製程可以包括化學機械研磨(chemical mechanical polishing;CMP)製程及/或濕蝕刻製程。在一些實施例中,可以在形成導電材料130之前,使用例如PVD製程、CVD製程、或其類似製程來形成擴散阻障層(未顯示)於隔離膜120上,以防止導線132從隔離膜120剝落或剝離。
參照圖9,根據2中的步驟S312,依序地移除位在堆疊的緩衝層210和犧牲層220上之部分隔離膜120、犧牲層220、和緩衝層210。從而,暴露出基板100的前表面1002,並形成包圍導線132的隔離襯層122。在一些實施例中,可以使用研磨製程(polishing process)將部分的隔離膜120從堆疊的緩衝層210和犧牲層220移除,並且使用濕蝕刻製程依序地移除犧牲層220和緩衝層210。在進行研磨製程期間,犧牲層220可以作為研磨停止層。在移除犧牲層220和緩衝層210之後,暴露出部分的隔離襯層122的外圍1222。參照圖9,導線132具有一端部表面1322,其位在基板100的前表面1002上方。
參照圖10,根據圖2的步驟S314,形成一導電部件140和包圍該導電部件140的一絕緣層150於基板100、隔離襯層122、和導線132上。電性耦合到主要構件114及/或導線132的導電部件140包括交替堆疊的複數個垂直元件144和複數個水平元件142。在一些實施例中,主要構件114可以與透過導電部件140與彼此內連接以形成例如邏輯元件、記憶體元件、輸入/輸出元件、晶片上系統(system-on-chip)元件、另一種合適類型的元件、或前述之組合。
可以透過電鍍製程由銅或鋁製成水平元件142;可以使用CVD製程由鎢製成垂直元件144。參照圖9和圖10,絕緣層150包圍隔離襯層122的外圍1222之暴露部分,並且覆蓋基板100之部分前表面1002以及透過導電部件140而暴露出來的導線132之部分端部表面1322。絕緣層150包括氧化矽、氮化矽、氮氧化物、硼矽酸鹽玻璃(borosilicate glass;BSG)、低介電常數(k)材料,另一種合適的材料、或前述之組合。絕緣層150的形成包括透過CVD或旋塗進行一種或多種製程。在一些實施例中,可使用習知的鑲嵌製程形成水平元件142和垂直元件144於絕緣層140中。在一些實施例中,於例如後端(back-end-of-line BEOL)製程中形成導電部件140和絕緣層150。
參照圖11和圖12,根據圖2的步驟S316進行薄化製程以薄化半導體晶圓111。從而,暴露出隔離襯層122的外圍1222的另一部分,與由絕緣層150包圍的外圍1222的該部分相對。參照圖11,在進行薄化製程之前,將圖10中所得的結構上下翻轉並透過黏合層252接合到載體晶圓250。換句話說,絕緣層150與黏合層252接觸。載體晶圓250可以是空白玻璃載體、空白陶瓷載體、或其類似材料。黏合層252在暴露於熱或光時可被分解,因此黏合層252可將載體晶圓250從薄化結構釋放。在一些實施例中,載體晶圓250可為可重複使用的,故其可以在移除之後再次使用。換句話說,載體晶圓250可被再次利用;例如,載體晶圓250可以重複地進行步驟S316以製造中間結構,如圖11和12所示。
半導體晶圓111的薄化包括(1)在半導體晶圓111上進行研磨製程以減少其厚度,從而形成接地晶圓(ground wafer)111',以及(2)進行蝕刻製程以暴露出絕緣襯層122的外圍1222的另一部分,從而形成經蝕刻的晶圓112。經蝕刻的晶圓112和主要構件114構成基板110。在圖11中,虛線表示半導體晶圓111的原始厚度,並且隔離襯層122並未透過接地晶圓111'而暴露。在圖12中,虛線表示接地晶圓111'的原始厚度。在一些實施例中,進行減少接地晶圓111'的厚度的蝕刻製程,直到隔離襯層122的端部表面1224與經蝕刻的晶圓112的後表面1122之間的距離D介於0.5 µm至10 µm的範圍之間,例如約5 µm。進行薄化製程之後,位於導線132上剩餘的隔離襯層122具有鈍化作用,用以在研磨和蝕刻製程之後的清洗製程期間,為接地晶圓111'和經蝕刻的晶圓112屏蔽導線132中的金屬材料。
參照圖13,根據圖2的步驟S318,形成第一介電層160於經蝕刻的晶圓112的後表面1122和隔離襯層122的暴露部分上。共形且均勻地形成第一介電層160於經蝕刻的晶圓112和隔離襯層122上。換句話說,第一介電層160的拓撲跟隨經蝕刻的晶圓112和隔離襯層122的暴露部分之拓撲。第一介電層160具有第一厚度T1,其可以例如介於0.5 µm至3 µm的範圍之間,例如約2 µm。第一介電層160包括像是氧化矽或氮化矽的含矽材料。在一些實施例中,可以使用旋塗製程、電漿增強(plasma-enhanced)CVD製程、或可以形成介電材料的另一種合適的製程來形成第一介電層160。
參照圖14,根據圖2的步驟S320,形成一金屬層170於第一介電層160上。共形且均勻地沉積金屬層170於第一介電層160上,使得第一介電層160被埋藏在金屬層170中。第一介電層160作為緩衝層以減輕金屬層170和隔離襯層122之間界面處的應力,並用於屏蔽金屬層170中的金屬材料使其不進入經蝕刻的晶圓112。
金屬層170的第二厚度T2實質上等於或大於第一介電層160的第一厚度T1。在一些實施例中,第二厚度T2可以介於例如1 µm至5 µm的範圍之間,例如2 µm。金屬層170可以包括銅、鋁、鎢、鈷、鈦、金、鉑、或前述之組合。可以使用CVD製程、PVD製程、或濺鍍製程來形成金屬層170。
參照圖15,根據圖2的步驟S322,沉積一第二介電層180於金屬層170上。共形且均勻地沉積第二介電層180於金屬層170上。沉積第二介電層180直到經蝕刻的晶圓112之上的第二介電層180的頂表面181位於導線132的端部表面1324上方。第二介電層180包括含矽材料,並且具有一第三厚度T3,其實質上等於或大於第一介電層160的第一厚度T1。在一些實施例中,第三厚度T3可以例如介於0.5 µm至5 µm的範圍之間,例如3 µm。在一些實施例中,第一和第二介電層160和180可以具有不同的介電材料。例如,使用旋塗製程、電漿增強CVD製程、或可以形成介電材料的另一種合適的製程來形成包括氧化矽或氮化矽的第二介電層180。
參照圖16,根據圖2的步驟S324,進行研磨製程以研磨掉部分的隔離襯層122、第一介電層160、金屬層170、和第二介電層180。據此,暴露出導線132並且形成包括導線132和隔離襯層124的複數個矽穿孔插塞190,其中導線132被隔離襯層134圍繞。剩餘的第一介電層(在下文中稱為“介電層”)162、剩餘的金屬層172、和剩餘的第二介電層182設置於矽穿孔插塞190的兩側。在一些實施例中,研磨製程包括化學機械研磨(CMP)製程及/或濕蝕刻製程。在一些實施例中,覆蓋金屬層170的第二介電層180可以在研磨過程期間用來保持期望的研磨速率。
參照圖17,將第二光阻罩幕260施加在介電層162、剩餘的金屬層172、部分剩餘的第二介電層182、以及矽穿孔插塞190上。第二光阻罩幕260用於圖案化剩餘的金屬層172和剩餘的第二介電層182。形成第二光阻罩幕260的步驟包括:(1)塗佈光敏材料於介電層162、剩餘的金屬層172、剩餘的第二介電層182、和矽穿孔插塞190上、(2)將光敏材料曝光於一圖案(未顯示);(3)進行曝光後烘烤製程(post-exposure bake process);以及(4)顯影光敏材料,從而形成窗口262以暴露出部分剩餘的第二介電層182(在矽穿孔插塞190之間)。矽穿孔插塞190受到第二光阻罩幕260保護。
參照圖18,根據圖2的步驟S326,進行圖案化製程以移除透過第二光阻罩幕260而暴露出來的部分剩餘的第二介電層182和剩餘的金屬層172。從而,形成了重分佈層174和覆蓋層184。參照圖17至圖18,使用一種或多種非等向性製程透過第二光阻罩幕260中的窗口262依序地蝕刻剩餘的第二介電層182和剩餘的金屬層172。在形成重分佈層174和覆蓋層184之後,例如,使用灰化製程或剝離製程來移除第二光阻罩幕260。
如圖19所示,在形成重分佈層174和覆蓋層184之後,將一第三光阻罩幕270施加於重分佈層174和覆蓋層184上。如圖19所示,第三光阻罩幕270包括複數個窗口272以暴露出介電層162、部分的重分佈層174、部分的覆蓋層184、和矽穿孔插塞190。第三光阻罩幕270的形成包括(1)使用旋塗製程將光敏材料施加在介電層162、重分佈層174、覆蓋層184、和矽穿孔插塞190上;(2)使用軟烤製程乾燥光敏材料;以及(3)進行微影製程以形成窗口272。
參照圖20,根據圖2的步驟S328,設置複數個凸塊200以將重分佈層174連接至矽穿孔插塞190。凸塊200作為導線132和重分佈層174之間的電性內連接。凸塊200的安裝可以透過先將助焊劑(未顯示)放置於介電層162、部分的重分佈層174和覆蓋層184、和矽穿孔插塞190上,然後將凸塊200設置於助焊劑上;一旦凸塊200與助焊劑接觸,就可以進行回焊以使凸塊200的材料和助焊劑回流,以將凸塊200物理性接合到導線132和重分佈層174。
參照圖21,可以使用灰化製程或濕剝離製程來移除第三光阻罩幕270,其中,濕剝離製程可以化學性地改變第三光阻罩幕270,使其不再黏附至介電層162、重分佈層174、和覆蓋層184。
本揭露的一方面提供了一種半導體元件。該半導體元件包括一基板、一導電部件、一重分佈層、至少一矽穿孔插塞、以及至少一凸塊。該導電部件設置於該基板的一前表面之上。該重分佈層設置於與該前表面相對的一後表面之上。該矽穿孔插塞穿過該基板並接觸該導電部件。該凸塊將該重分佈層連接至該矽穿孔插塞。
本揭露的一方面提供一種半導體元件的製備方法。該方法包括以下步驟:形成至少一溝槽於一半導體晶圓中;沈積一隔離膜於該溝槽中;沈積一導電材料於該隔離膜上以形成至少一導線於該溝槽中;形成一導電部件於該半導體晶圓的一前表面之上,其中該導電部件電性耦合至該導線;薄化該半導體晶圓直到該半導體晶圓的一後表面位於該隔離膜的一端部表面下方;形成一金屬層於該隔離膜透過該半導體晶圓而暴露出來的一外圍之上和與該前表面相對的一後表面之上;進行一研磨製程以移除部分的該金屬層和該隔離膜直到暴露出該導線;以及形成至少一凸塊將剩餘的該金屬層連接至該導線。
雖然已詳述本揭露及其優點,然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如,可用不同的方法實施上述的許多製程,並且以其他製程或前述之組合替代上述的許多製程。
再者,本申請案的範圍並不受限於說明書中該之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文該之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此,此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
10:半導體元件
100:基板
1002:前表面
110:基板
1102:前表面
1104:後表面
111:半導體晶圓
111':接地晶圓
112:晶圓
1122:後表面
114:主要構件
116:溝槽
120:隔離膜
122:隔離襯層
1222:外圍
1224:端部表面
1226:外圍
124:隔離襯層
130:導電材料
132:導線
1322:端部表面
1324:端部表面
134:隔離襯層
140:導電部件
142:水平元件
144:垂直元件
150:絕緣層
160:第一介電層
162:介電層
172:剩餘的金屬層
174:重分佈層
1742:水平區段
1744:垂直區段
180:第二介電層
181:頂表面
182:剩餘的第二介電層
184:覆蓋層
190:矽穿孔插塞
20:外部元件
200:凸塊
210:緩衝層
220:犧牲層
230:第一光阻罩幕
232:窗口
240:窗口
250:載體晶圓
252:黏合層
260:第二光阻罩幕
262:窗口
270:第三光阻罩幕
272:窗口
300:方法
D:距離
S302:步驟
S304:步驟
S306:步驟
S308:步驟
S310:步驟
S312:步驟
S314:步驟
S316:步驟
S318:步驟
S320:步驟
S322:步驟
S324:步驟
S326:步驟
S328:步驟
T1:第一厚度
T2:第二厚度
T3:第三厚度
本揭露各方面可配合以下圖式及詳細說明閱讀以便了解。要強調的是,依照工業上的標準慣例,各個部件(feature)並未按照比例繪製。事實上,為了清楚之討論,可能任意的放大或縮小各個部件的尺寸。
圖1是根據本揭露一些實施例顯示一半導體元件的剖面圖。
圖2是根據本揭露一些實施例顯示一半導體元件的製備方法流程圖。
圖3到圖21是根據本揭露一些實施例顯示形成半導體元件之中間階段剖面圖。
10:半導體元件
110:基板
1102:前表面
1104:後表面
112:晶圓
114:主要構件
1226:外圍
124:隔離襯層
132:導線
140:導電部件
142:水平元件
144:垂直元件
150:絕緣層
162:介電層
172:剩餘的金屬層
174:重分佈層
1742:水平區段
1744:垂直區段
184:覆蓋層
190:矽穿孔插塞
20:外部元件
200:凸塊
Claims (17)
- 一種半導體元件,包括:一基板;一導電部件,設置於該基板的一前表面之上;一重分佈層,設置於與該前表面相對的一後表面之上;至少一矽穿孔插塞(through silicon via),穿過該基板並接觸該導電部件,其中該矽穿孔插塞包括一導線和包圍該導線的一隔離襯層,且該重分佈層包括複數個水平區段和連接至該些水平區段且設置於該隔離襯層的一外圍之上的複數個垂直區段;至少一凸塊,將該重分佈層連接至該矽穿孔插塞;以及一介電層,設置於該基板的該後表面和該重分佈層的該些水平區段之間,且設置於該隔離襯層的該外圍和該重分佈層的該些垂直區段之間。
- 如請求項1所述之半導體元件,其中部分的該介電層透過該重分佈層的該些水平區段而暴露出來。
- 如請求項1所述之半導體元件,更包括一覆蓋層,覆蓋該重分佈層的該些水平區段。
- 如請求項3所述之半導體元件,其中該覆蓋層的厚度大於該重分佈層和該介電層的厚度。
- 如請求項1所述之半導體元件,更包括包圍該導電部件的一絕緣層,其中該矽穿孔插塞延伸至該絕緣層中。
- 一種半導體元件的製備方法,包括:形成至少一溝槽於一半導體晶圓中;沈積一隔離膜於該溝槽中;沈積一導電材料於該隔離膜上以形成至少一導線於該溝槽中;形成一導電部件於該半導體晶圓的一前表面之上,其中該導電部件電性耦合至該導線;薄化該半導體晶圓直到該半導體晶圓的一後表面位於該隔離膜的一端部表面(end surface)下方,其中該後表面與該前表面相對;形成一金屬層於該半導體晶圓的該後表面之上和該隔離膜透過該半導體晶圓而暴露出來的一外圍之一部分之上;進行一研磨製程以移除部分的該金屬層和該隔離膜直到暴露出該導線;以及形成至少一凸塊以將該金屬層的剩餘部分連接至該導線;其中在形成該凸塊之前進行一圖案化製程以移除部分的該金屬層。
- 如請求項6所述之半導體元件的製備方法,其中該金屬層之拓撲跟隨隔離膜的暴露部分和該半導體晶圓的該後表面之拓撲。
- 如請求項6所述之半導體元件的製備方法,其中該金屬層的一厚度介於1μm至5μm的範圍之間。
- 如請求項6所述之半導體元件的製備方法,更包括:在形成該金屬層之前,沉積一第一介電層於該半導體晶圓的該後表面上和該隔離膜透過該半導體晶圓而暴露出來的該外圍之該部分上;以及在該研磨製程期間移除位於該導線的一端部表面上方之部分的該第一介電層,其中該第一介電層具有一實質上均勻的厚度。
- 如請求項9所述之半導體元件的製備方法,其中該第一介電層的一厚度介於0.5μm至3μm的範圍之間。
- 如請求項6所述之半導體元件的製備方法,更包括:沉積一第二介電層於該金屬層上直到該第二介電層的一頂表面位於該導線的一端部表面上方,其中該第二介電層位於該半導體晶圓之上;以及在該研磨製程期間移除位於該導線的該端部表面上方之部分的該第二介電層,其中該第二介電層具有一實質上均勻的厚度。
- 如請求項10所述之半導體元件的製備方法,其中該第二介電層的一 厚度介於0.5μm至5μm的範圍之間。
- 如請求項11所述之半導體元件的製備方法,更包括進行一圖案化製程以依序地移除部分的該第二介電層和該金屬層。
- 如請求項6所述之半導體元件的製備方法,該隔離膜的該端部表面和該半導體晶圓的該後表面之間的一距離介於0.5μm至10μm的範圍之間。
- 如請求項6所述之半導體元件的製備方法,更包括在形成該導電部件的同時,形成一絕緣層以包圍該隔離膜和該導電部件的一外圍。
- 如請求項6所述之半導體元件的製備方法,其中形成該溝槽包括:依序地形成一緩衝層和一犧牲層於該半導體晶圓的該前表面上;形成至少一開口穿過該緩衝層和該犧牲層;以及透過該開口蝕刻該半導體晶圓以形成該溝槽,其中在沉積該導電材料之後將該緩衝層和該犧牲層移除,使得該導線的一端部表面位於該半導體晶圓的該前表面上方。
- 如請求項6所述之半導體元件的製備方法,其中薄化該半導體晶圓包括:進行一研磨製程以減少該半導體晶圓的一厚度,其中該隔離膜並未在進行該研磨製程之後被暴露出來;以及進行一蝕刻製程以進一步減少該半導體晶圓的該厚度,直到該半 導體晶圓的該後表面位於該隔離膜的該端部表面下方。
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