CN112736054B - 半导体元件及其制备方法 - Google Patents

半导体元件及其制备方法 Download PDF

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Publication number
CN112736054B
CN112736054B CN202010946678.4A CN202010946678A CN112736054B CN 112736054 B CN112736054 B CN 112736054B CN 202010946678 A CN202010946678 A CN 202010946678A CN 112736054 B CN112736054 B CN 112736054B
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layer
semiconductor device
dielectric
opening
semiconductor
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CN112736054A (zh
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施江林
吴珮甄
张庆弘
丘世仰
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本公开提供一种半导体元件及其制备方法。该半导体元件具有一半导体部件、一重布线层、一接合介电质以及一隔离层。该重布线层设置在该半导体部件上，并电性耦接到该半导体部件。该接合介电质设置在该半导体部件上，以围绕该重布线层的一顶部。该隔离层设置在该半导体部件与该接合介电质之间，以围绕该重布线层的一底部。

Description

半导体元件及其制备方法
技术领域
本公开主张2019年10月28日申请的美国正式申请案第16/665,408号的优先权及益处，该美国正式申请案的内容以全文引用的方式并入本文中。
本公开涉及一种半导体元件及其制备方法。特别涉及一种具有接合结构(bondingstructure)的半导体元件及其制备方法。
背景技术
半导体元件使用在不同的电子应用，例如个人电脑、手机、数码相机，或其他电子设备。半导体元件的制造包含依序沉积不同材料层在一半导体基底上，以及使用微影及蚀刻工艺图案化该些材料层，以在半导体基底上形成微电子部件，包括晶体管、二极管、电阻器及/或电容器。
半导体产业通过在最小特征尺寸的持续缩小，以持续改善不同电子部件的集成密度(integration density)，而最小特征尺寸的持续缩小允许更多部件整合在一给定区域中。发展出占用更小面积的更小的封装结构，以封装半导体元件。举例来说，为了尝试进一步增加半导体元件的密度，已经在研究包括二或多个微电子部件的堆叠的三维集成电路。
上文的“现有技术”说明仅是提供背景技术，并未承认上文的“现有技术”说明公开本公开的标的，不构成本公开的现有技术，且上文的“现有技术”的任何说明均不应作为本公开的任一部分。
发明内容
本公开的一实施例提供一种半导体元件。该半导体元件包括一半导体部件、一重布线层、一接合介电质以及一隔离层。该重布线层设置在该半导体部件上，并电性耦接到该半导体部件。该接合介电质位在该半导体部件上，并围绕该重布线层的一顶部设置。该隔离层位在该半导体部件与该接合介电质之间，以围绕该重布线层的一底部设置。
在本公开的一些实施例中，从一剖视图所视，该底部具有一第一宽度，而该顶部与该底部为一体成型，并具有一第二宽度，该第二宽度大于该第一宽度。
在本公开的一些实施例中，该第一宽度在距该半导体组件的距离增加的位置处逐渐增加。
在本公开的一些实施例中，该隔离层接触该顶部。
在本公开的一些实施例中，该接合介电质具有一第一厚度，而该隔离层具有一第二厚度，该第二厚度小于该第一厚度。
在本公开的一些实施例中，该隔离层包括：一下层膜，位在该半导体部件上；以及一上层膜，位在该下层膜与该接合介电质之间。
在本公开的一些实施例中，该半导体元件还包括一互连层，包含有至少一金属垫，并位在该半导体部件与该重布线层之间，以将该半导体部件电性耦接到该重布线层，其中该金属垫具有一材料，该材料不同于该重布线层的一材料。
在本公开的一些实施例中，该半导体元件还包括一扩散阻障层，位在该接合介电质与该重布线层的该顶部之间，以及位在该隔离层与该重布线层的该底部之间。
本公开的另一实施例提供一种半导体元件的制备方法。该制备方法包括：形成一互连层在一半导体部件上，其中该互连层包含至少一金属垫，该至少一金属垫电性耦接到该半导体部件；沉积一隔离层在该互连层上；沉积一接合介电质在该隔离层上；以及形成一重布线层，以穿经该接合介电质与该隔离层，并接触该互连层。
在本公开的一些实施例中，该重布线层的形成包括：产生一第一开口在该隔离层中，以暴露该金属垫的一部分；同时充填该接合介电质的沉积在该第一开口中；产生一第二开口在该接合介电质中，并重新产生该第一开口；以及沉积一导电材料在该第一开口与该第二开口中。
在本公开的一些实施例中，在该第一开口与该第二开口中的该导电材料的沉积包括：充填一含铜导电材料在该第一开口与该第二开口并溢出，其中该含铜导电材料覆盖该接合介电质；以及研磨该含铜导电材料以暴露该接合介电质的一顶表面，其中在该含铜导电材料研磨之后，该重布线层的一顶表面与该接合介电质的该顶表面为共面。
在本公开的一些实施例中，该隔离层的一顶表面经由该第二开口暴露。
在本公开的一些实施例中，在该隔离层的区域移除之后，留下一残留隔离层，而该互连层与该残留隔离层的各侧壁之间的一夹角大于90度。
在本公开的一些实施例中，该半导体元件的制备方法还包括执行一平坦化工艺，以提供具有一大致平面的顶表面的该接合介电质。
在本公开的一些实施例中，平坦化该接合介电质从5.5μm到3μm。
上文已相当广泛地概述本公开的技术特征及优点，从而使下文的本公开详细描述得以获得较好了解。构成本公开的保护范围标的的其它技术特征及优点将描述于下文。本公开所属技术领域中技术人员应了解，可相当容易地利用下文公开的概念与特定实施例可作为修改或设计其它结构或工艺而实现与本公开相同的目的。本公开所属技术领域中技术人员亦应了解，这类等效建构无法脱离相关申请文件所界定的本公开的构思和范围。
附图说明
参阅实施方式与相关申请文件合并考量附图时，可得以更全面了解本公开的公开内容，附图中相同的元件符号是指相同的元件。
图1为依据本公开一实施例中一种半导体元件的剖视示意图。
图2为依据本公开一实施例中一种半导体元件组件的剖视示意图。
图3为依据本公开一实施例中一种半导体元件的制备方法的流程示意图。
图4到图12为依据本公开一实施例中半导体元件的制备方法的中间阶段的剖视示意图。
附图标记说明：
10：半导体元件
10A：第一半导体元件
10B：第二半导体元件
100：基底
110：半导体部件
120：互连层
130：重布线层
130A：第一重布线层
130B：第二重布线层
132：底部
134：顶部
136：顶表面
140：接合介电质
140A：接合介电质
140B：接合介电质
142：顶表面
144：侧壁
150：隔离层
151：隔离层
152：上层膜
153：上层膜
154：下层膜
155：下层膜
156：顶表面
157：侧壁
158：顶表面
160：扩散阻障层
162：顶表面
20：半导体元件组件
210：第一开口
220：第一蚀刻遮罩
230：第二蚀刻遮罩
240：第二开口
250：导电材料
300：制备方法
302：步骤
304：步骤
306：步骤
308：步骤
310：步骤
312：步骤
314：步骤
316：步骤
318：步骤
ILD1：介电材料
ILD2：介电材料
ILD3：介电材料
M1：金属垫
M2：金属垫
M3：金属垫
T1：厚度
T2：厚度
T3：厚度
V1：通孔
V2：通孔
V3：通孔
W1：第一宽度
W2：第二宽度
θ：夹角
具体实施方式
现在使用特定语言描述附图中所示出的本公开的实施例或例示。应当理解，在此并非意指限制本公开的范围。所描述的实施例的任何改变或修改，以及本文中所描述的原理的任何进一步应用，都被认为是通常发生在与本公开内容相关的所属技术领域中技术人员其中之一。在整个实施例中可以重复使用参考元件编号，但这不一定意味着一个实施例的特征适用于另一实施例，即使它们共享相同的参考元件编号。
应当理解，尽管这里可以使用术语第一，第二，第三等来描述各种元件、部件、区域、层或区段(sections)，但是这些元件、部件、区域、层或区段不受这些术语的限制。相反，这些术语仅用于将一个元件、组件、区域、层或区段与另一个区域、层或区段所区分开。因此，在不脱离本发明进部性构思的教导的情况下，下列所讨论的第一元件、组件、区域、层或区段可以被称为第二元件、组件、区域、层或区段。
本文中使用的术语仅是为了实现描述特定实施例的目的，而非意欲限制本发明。如本文中所使用，单数形式“一(a)”、“一(an)”，及“该(the)”意欲亦包括复数形式，除非上下文中另作明确指示。将进一步理解，当术语“包括(cormprises)”及/或“包括(comprising)”用于本说明书中时，该些术语规定所陈述的特征、整数、步骤、操作、元件，及/或组件的存在，但不排除存在或增添一或更多个其他特征、整数、步骤、操作、元件、组件，及/或上述各者的群组。
图1为依据本公开一实施例中一种半导体元件10的剖视示意图。请参考图1，半导体元件10包括一基底100、一或多个半导体部件(semiconductor components)110、一互连层(interconnect layer)120、一重布线层(re-routing layer)130、一接合介电质(bonding dielectric)140以及一隔离层(insulating layer)151；一或多个半导体部件110位在基底100中，互连层120设置在半导体部件110上，重布线层130接触互连层120，接合介电质140位在互连层120上，而隔离层151位在互连层120与接合介电质140之间，以围绕重布线层130。
在一些实施例中，基底100为由硅所制的一半导体基底。在其他实施例中，基底100可包含其他半导体材料，例如III-V族半导体材料。半导体部件110可包括多个掺杂区、多个绝缘元件(isolation features)以及不同层，其并不会分开说明，而是组合在一起形成不同的微电子元件，例如金属氧化半导体(MOS)部件。
通过嵌置在介电材料ILD1、ILD2、ILD3中交错叠置的金属垫M1、M2、M3以及通孔V1、V2、V3的方法，重布线层130经由互连层120而电性耦接到半导体部件110。在一些实施例中，重布线层130包括一底部132以及一顶部134，底部132接触互连层120，且隔离层151围绕底部132设置，而顶部134与底部132为一体成型，且接合介电质140围绕顶部134设置。在一些实施例中，从剖视图所视，底部132具有一第一宽度W1，且顶部134具有一第二宽度W2，而第二宽度W2大于第一宽度W1。在一些实施例中，第一宽度W1在距半导体组件110的距离减小的位置处逐渐减小，而第二宽度W2为一大致一致的宽度。在一些实施例中，隔离层150接触顶部134。
在一些实施例中，由含铜材料所制的重布线层130容易扩散；因此一扩散阻障层160至少铺设在重布线层130与接合介电质140之间以及重布线层130与隔离层1151之间。扩散阻障层160亦可铺设在重布线层130与互连层120之间。在一些实施例中，扩散阻障层160的一顶表面162与重布线层130的一顶表面136等高，其是与接合介电质140的一顶表面142为共面。耐火金属(例如钛或钽)、耐火氮化金属(例如氮化钛或氮化钽)以及耐火氮化硅金属(例如氮化硅钛或氮化硅钽)是典型地使用于扩散阻障层160。
在例示的实施中，位在隔离层151上的接合介电质140具有一第一厚度T1，而隔离层151具有一第二厚度T2，第二厚度T2小于第一厚度T1。隔离层150具有一单一层或者是一堆叠层结构，并具有一氮化硅膜。在此实施例中，隔离层151具有一上层膜153以及一下层膜155，上层膜153为氮化硅，并接触接合介电质140，而下层膜155未在互连层120与上层膜153之间。在一些实施例中，上层膜153可具有一蚀刻率，是不同于下层膜154的蚀刻率，以产生重布线层130的大致无空孔(void-free)的底部132。在一些实施例中，下层膜155包含氧化物，例如氧化硅。
在一些实施例中，可调整上层膜153与下层膜155的厚度，以终止在基底100与含有硅的下层膜154的界面(interface)处的硅原子悬空键结(dangling bond)。详而言之，在氧化硅的下层膜154与硅界面的基底100的界面处的硅原子悬空键结，是与导入在氮化硅的上层膜152的氢原子接合(bonded)，或是由导入在氮化硅的上层膜152的氢原子所终止(terminated)。在一些实施例中，重布线层130与接合介电质140当作是一接合层(bondinglayer)，以促进与其他半导体元件10的接合。
图2为依据本公开一实施例中一种半导体元件组件20的剖视示意图。请参考半导体元件组件20包括二半导体元件，具有一第一半导体元件10A以及一第二半导体元件10B，以前面对前面(front-to-front)架构接合在一起。第一半导体元件10A与第二半导体元件10B的不同层硅可大致类似于如图1所示的半导体元件10的各层，为了简洁，则省略该些层的详细叙述。
在一些实施例中，第二半导体元件10B为上下颠倒设置，并叠置在第一半导体元件10A上，而第二半导体元件10B是混合接合(hybrid-bonded)至第一半导体元件10A，以成为第一半导体元件10A与第二半导体元件10B之间的物理性与电性连接。不同工艺可用于将第一半导体元件10A接合至第二半导体元件10B；在一些实施例中，用于将第一半导体元件10A接合至第二半导体元件10B的该些工艺，包括金属对金属接合工艺(metal-to-metalbonding process)以及介电质对介电质接合工艺(dielectric-to-dielectric bondingprocess)。
在一些实施例中，第一半导体元件10A与第二半导体元件10B是对准以使第一半导体元件10A的一第一重布线层130A接触第二半导体元件10B的一第二重布线层130B，并使第一半导体元件10A的一接合介电质140A接触第二半导体元件10B的第二接合介电质140B，其中第二重布线层130B与第一重布线层130A具有大致相同的形状。
在第一半导体元件10A与第二半导体元件10B对准之后，是施加热及/或力以将第一重布线层130A接合到第二重布线层130B，并将第一接合介电质140A固化(cure)至第二接合介电质140B；借此形成半导体元件组件20。
图3为依据本公开一实施例中一种半导体元件100的制备方法300的流程示意图。图4到图12为依据本公开一实施例中半导体元件100的制备方法300的中间阶段的剖视示意图。图4至图12所示的各阶段亦图例说明在图3的流程图中。在接下来的说明中，图4至图12的各制造阶段是参考图3所示的处理步骤进行说明。
请参考图4，依据图3中的步骤302，是提供一或多个半导体部件110与一互连层120。该些半导体部件110形成在含有硅的一半导体基底100中。在一些实施例中，该些半导体部件110使用工艺所制，包括沉积(deposition)、蚀刻(etching)、植入(implantation)、微影(photolithography)、回火(annealing)，及/或其他适合工艺。再者，举例来说，该些半导体部件110可与另一半导体部件互连(经由互连层120)，以形成一逻辑元件、一存储器元件、一输入/输出元件、一单芯片(system-on-chip)元件、其他适合类型元件，或其组合。在一些实施例中，在前段(front-end-of-line，FEOL)工艺期间，该些半导体部件110可形成在半导体基底100中。
形成在半导体部件110上并电性耦接到半导体部件110的互连层120，具有嵌置在介电材料ILD1、ILD2、ILD3中交错叠置的金属垫M1、M2、M3以及通孔V1、V2、V3。在此实施例中，通孔V1接触半导体部件110，而距半导体部件110最远的金属垫M3则经由介电材料ILD3而暴露。在一些实施例中，金属垫M1、M2、M3可包含铝或铝合金。在一些实施例中，介电材料ILD1、ILD2、ILD3包含相同材料或不同材料。介电材料ILD1、ILD2、ILD3可包含氧化硅、氮化硅、氮氧化物(oxynitride)、硼硅玻璃(borosilicate glass，BSG)、低介电常数材料、其他适合材料或其组合。在一些实施例中，金属垫M1、M2、M3可使用镀覆工艺(plating process)形成，通孔V1、V2、V3可使用化学气相沉积(CVD)工艺形成，而介电材料ILD1、ILD2、ILD3可使用气相沉积工艺形成。
请参考图5，在一些实施例中，依据图3中的步骤304，一隔离层150沉积在互连层120上。在一些实施例中，隔离层150的沉积可包括沉积一毯覆下层膜(blanket underlyingfilm)154、以及沉积一毯覆上层膜(blanket overlying film)152在毯覆下层膜154上，而毯覆下层膜154是接触金属垫M3以及距基底100最远的互连层120的介电材料ILD3。在一些实施例中，在毯覆上层膜152沉积之后，可执行一平坦化工艺，以提供毯覆上层膜152一大致平面的顶表面156。在一些实施例中，毯覆下层膜154以及毯覆上层膜152是以低压化学气相沉积(CVD)工艺或一原子层沉积(atomic layer deposition，ALD)工艺进行沉积。在另外的实施例中，毯覆下层膜154以及毯覆上层膜152可使用气相沉积工艺形成。在一些实施例中，毯覆下层膜154包含氧化物，例如氧化硅。毯覆上层膜152包含氮化物，例如氮化硅，以提供半导体元件100一均匀悬空键结架构。
请参考图6，在一些实施例中，依据图3中的步骤306，形成一第一开口210以暴露互连层120。在一些实施例中，如图5所示，通过涂布在毯覆上层膜152上的一第一蚀刻遮罩220以及执行一第一蚀刻工艺，以移除毯覆上层膜152与毯覆下层膜154未被第一蚀刻遮罩220保护的部分，借此形成第一开口210；据此，金属垫M3的一或多个部分是经由第一开口210而暴露。在一些实施例中，通过执行一暴露工艺以及一显影工艺(develop process)在完全覆盖毯覆上层膜152的一第一光刻胶材料上，以形成第一蚀刻遮罩220。在一些实施例中，使用一干蚀刻工艺、一非等向性湿蚀刻工艺或其他适合非等向性工艺，蚀刻隔离层150以形成一残留隔离层151，而第一蚀刻工艺可使用多个蚀刻剂(etchants)，以蚀刻毯覆上层膜152与毯覆下层膜154，其中是依据被蚀刻的材料来选择该些蚀刻剂。
请参考图6，在一些实施例中，残留的隔离膜151具有多个侧壁157，该些侧壁157是经由第一开口210而暴露，而残留的隔离层151包括未在互连层120上的一上层膜153以及位在互连层120与上层膜153之间的一下层膜153。在一些实施例中，该些侧壁157与互连层120之间的一夹角θ大于90度，以产生一无空孔(void-free)重布层，进而依序形成在第一开口210中。举例来说，然后通过一灰化工艺(ashing process)或一湿式剥离工艺(wet stripprocess)，以移除第一蚀刻工艺220，其中该湿式剥离工艺可化学改变第一蚀刻遮罩220，以使其不再连接到上层膜153。
请参考图7，在已经移除第一光刻胶图案220之后，依据图3中的步骤308，一接合介电质140是沉积在隔离层151的一顶表面158上以及在第一开口210中。在一些实施例中，接合介电质140是填满第一开口210。在一些实施例中，在沉积之后，在隔离层150上的接合介电质140具有一初始厚度T3，为5.5μm。
请参考图8，依据在图3中的步骤310，平坦化接合介电质140。在一些实施例中，接合介电质140变薄至一厚度T1，为3μm。在一些实施例中，在平坦化工艺之后，接合介电质140具有一大致平面顶表面142。在一些实施例中，举例来说，使用化学机械研磨(CMP)工艺以平坦化接合介电质140。接下来，形成一第二蚀刻遮罩230，并图案化在接合介电质140上。
请参考图9，在一些实施例中，依据图3中的步骤312，执行一第二蚀刻工艺以移除接合介电质140的区域。在一些实施例中，在第二蚀刻工艺之后，移除接合介电质140经由第二蚀刻遮罩230而暴露的该些区域。接合介电质140的该些区域的移除是在接合介电质140中产生一第二开口240，并再产生第一开口220，其是轮流暴露金属垫M3的一些部分以及残留的隔离层151的顶表面的一些部分。第二开口240连通第一开口220。然后移除第二蚀刻遮罩230。
请参考图10，在一些实施例中，依据图3中的步骤314，一扩散阻障层160沉积在接合介电质140的顶表面142上、接合介电质140的各侧壁144上、隔离层151的顶表面158上以及隔离层151的各侧壁157上。在一些实施例中，扩散阻障层160亦沉积在互连层120的金属垫M3与介电材料ILD3上。在一些实施例中，举例来说，使用物理气相沉积(PVD)工艺形成具有一大致均匀厚度的扩散阻障层160。
请参考图11，在一些实施例中，依据图3中的步骤316，一导电材料250沉积在扩散阻障层160(以及金属垫M3)上。在一些实施例中，不仅填满第一开口220与第二开口240，而且覆盖接合介电质140的顶表面142。在一些实施例中，使用一镀覆工艺形成导电材料250。
请参考图12，在一些实施例中，执行一研磨工艺以从接合介电质140的顶表面142移除导电材料250与扩散阻障层160，借此形成一重布线层130。因此，完全地形成半导体元件100。
本公开的一实施例提供一种半导体元件。该半导体元件包括一半导体部件、一重布线层、一接合介电质以及一隔离层。该重布线层设置在该半导体部件上，并电性耦接到该半导体部件。该接合介电质位在该半导体部件上，并围绕该重布线层的一顶部设置。该隔离层位在该半导体部件与该接合介电质之间，以围绕该重布线层的一底部设置。
本公开的另一实施例提供一种半导体元件的制备方法。该制备方法包括：形成一互连层在一半导体部件上，其中该互连层包含至少一金属垫，该至少一金属垫电性耦接到该半导体部件；沉积一隔离层在该互连层上；沉积一接合介电质在该隔离层上；以及形成一重布线层，以穿经该接合介电质与该隔离层，并接触该互连层。
虽然已详述本公开及其优点，然而应理解可进行各种变化、取代与替代而不脱离相关申请文件所定义的本公开的构思与范围。例如，可用不同的方法实施上述的许多工艺，并且以其他工艺或其组合替代上述的许多工艺。
再者，本公开的范围并不受限于说明书中所述的工艺、机械、制造、物质组成物、手段、方法与步骤的特定实施例。本领域的技术人士可自本公开的公开内容理解可根据本公开而使用与本文所述的对应实施例具有相同功能或是达到实质上相同结果的现存或是未来发展的工艺、机械、制造、物质组成物、手段、方法、或步骤。据此，这些工艺、机械、制造、物质组成物、手段、方法、或步骤是包含于本公开的保护范围内。

Claims (11)

1.一种半导体元件，包括：
一半导体部件；
一重布线层，设置在该半导体部件上，并电性耦接到该半导体部件；
一互连层，包含有至少一金属垫，并位在该半导体部件与该重布线层之间，以将该半导体部件电性耦接到该重布线层，其中该金属垫具有一材料，该材料不同于该重布线层的一材料；
一接合介电质，位在该半导体部件上，并围绕该重布线层的一顶部设置；以及
一隔离层，位在该半导体部件与该接合介电质之间，以围绕该重布线层的一底部设置；
其中该隔离层包括：一下层膜，位在该半导体部件上；以及一上层膜，位在该下层膜与该接合介电质之间，其中该下层膜包括二氧化硅，而该上层膜包括氮化硅，其中该下层膜和该上层膜包围该重布线层的该底部，其中该上层膜具有一蚀刻率，该蚀刻率不同于该下层膜的一蚀刻率。
2.如权利要求1所述的半导体元件，其中从一剖视图所视，该底部具有一第一宽度，而该顶部与该底部为一体成型，并具有一第二宽度，该第二宽度大于该第一宽度。
3.如权利要求2所述的半导体元件，其中该第一宽度在距该半导体部件的距离增加的位置处逐渐增加。
4.如权利要求2所述的半导体元件，其中该隔离层接触该顶部。
5.如权利要求1所述的半导体元件，其中该接合介电质具有一第一厚度，而该隔离层具有一第二厚度，该第二厚度小于该第一厚度。
6.如权利要求1所述的半导体元件，还包括一扩散阻障层，位在该接合介电质与该重布线层的该顶部之间，以及位在该隔离层与该重布线层的该底部之间。
7.一种半导体元件的制备方法，包括：
形成一互连层在一半导体部件上，其中该互连层包含至少一金属垫，该至少一金属垫电性耦接到该半导体部件；
沉积一隔离层在该互连层上；
沉积一接合介电质在该隔离层上；以及
形成一重布线层，以穿经该接合介电质与该隔离层，并接触该互连层；
其中该重布线层的形成包括：
产生一第一开口在该隔离层中，以暴露该金属垫的一部分；
同时充填该接合介电质的沉积在该第一开口中；
产生一第二开口在该接合介电质中，并重新产生该第一开口；以及
沉积一导电材料在该第一开口与该第二开口中；
其中在该第一开口与该第二开口中的该导电材料的沉积包括：
充填一含铜导电材料在该第一开口与该第二开口并溢出，其中该含铜导电材料覆盖该接合介电质；以及
研磨该含铜导电材料以暴露该接合介电质的一顶表面，其中在该含铜导电材料研磨之后，该重布线层的一顶表面与该接合介电质的该顶表面为共面。
8.如权利要求7所述的半导体元件的制备方法，其中该隔离层的一顶表面经由该第二开口暴露。
9.如权利要求7所述的半导体元件的制备方法，其中在该隔离层的区域移除之后，留下一残留隔离层，而该互连层与该残留隔离层的各侧壁之间的一夹角大于90度。
10.如权利要求7所述的半导体元件的制备方法，还包括执行一平坦化工艺，以提供具有一平面的顶表面的该接合介电质。
11.如权利要求10所述的半导体元件的制备方法，其中平坦化该接合介电质从5.5μm到3μm。
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Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
US20240047350A1 (en) * 2022-08-03 2024-02-08 Nanya Technology Corporation Metal structure having funnel-shaped interconnect and method of manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1828884A (zh) * 2005-01-25 2006-09-06 台湾积体电路制造股份有限公司 半导体装置及其制造方法
TW201911515A (zh) * 2017-07-27 2019-03-16 台灣積體電路製造股份有限公司 半導體封裝及製作半導體封裝的方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6610594B2 (en) * 2001-07-10 2003-08-26 Advanced Micro Devices, Inc. Locally increasing sidewall density by ion implantation
US6847073B2 (en) * 2002-11-07 2005-01-25 Kabushiki Kaisha Toshiba Semiconductor device using ferroelectric film in cell capacitor, and method for fabricating the same
US7125793B2 (en) * 2003-12-23 2006-10-24 Intel Corporation Method for forming an opening for an interconnect structure in a dielectric layer having a photosensitive material
US20090081864A1 (en) * 2007-09-21 2009-03-26 Texas Instruments Incorporated SiC Film for Semiconductor Processing
JP2010010656A (ja) * 2008-05-26 2010-01-14 Renesas Technology Corp 半導体装置およびその製造方法
US20140159130A1 (en) * 2012-11-30 2014-06-12 Enpirion, Inc. Apparatus including a semiconductor device coupled to a decoupling device
US9349691B2 (en) * 2014-07-24 2016-05-24 International Business Machines Corporation Semiconductor device with reduced via resistance
US9406629B2 (en) * 2014-10-15 2016-08-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and manufacturing method thereof
US10163661B2 (en) * 2015-06-30 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
JP6649189B2 (ja) 2016-06-27 2020-02-19 ルネサスエレクトロニクス株式会社 半導体装置
US10032711B2 (en) * 2016-07-25 2018-07-24 International Business Machines Corporation Integrating metal-insulator-metal capacitors with air gap process flow
TWI642159B (zh) 2017-02-21 2018-11-21 華邦電子股份有限公司 封裝結構
US10692826B2 (en) 2017-09-27 2020-06-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and method for forming the same
US10319707B2 (en) * 2017-09-27 2019-06-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor component, package structure and manufacturing method thereof
US10475725B2 (en) * 2017-11-08 2019-11-12 Texas Instruments Incorporated Structure to enable higher current density in integrated circuit resistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1828884A (zh) * 2005-01-25 2006-09-06 台湾积体电路制造股份有限公司 半导体装置及其制造方法
TW201911515A (zh) * 2017-07-27 2019-03-16 台灣積體電路製造股份有限公司 半導體封裝及製作半導體封裝的方法

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