CN113284884B - 半导体封装及其制备方法 - Google Patents

半导体封装及其制备方法 Download PDF

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CN113284884B
CN113284884B CN202110108867.9A CN202110108867A CN113284884B CN 113284884 B CN113284884 B CN 113284884B CN 202110108867 A CN202110108867 A CN 202110108867A CN 113284884 B CN113284884 B CN 113284884B
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die
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redistribution layer
conductive
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CN113284884A (zh
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施信益
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本公开提供一种半导体封装及其制备方法。该半导体封装具有一第一晶粒、一第二晶粒、多个导电栓塞以及一重分布层。该重分布层具有一第一区段以及一第二区段，该第二区段与该第一区段为电性绝缘。该重分布层的该第一区段电性连接该第一晶粒到该第二晶粒，且该重分布层的该第二区段电性连接该第一晶粒到所述导电栓塞。

Description

半导体封装及其制备方法
技术领域
本申请案主张2020年2月19日申请的美国正式申请案第16/795,006号的优先权及益处，该美国正式申请案的内容以全文引用的方式并入本文中。
本公开涉及一种半导体元件及该半导体元件的制备方法，特别是涉及一种半导体封装及该半导体封装的制备方法，其中该半导体封装具有多个堆叠半导体晶粒以及多个直通模封穿孔(through molding vias)。
背景技术
当集成电路技术持续进步时，其是正在进行不断的努力以提高效能和密度。设计者为实现这些好处而探索出的一种方法，是实施堆叠式三维集成电路。三维集成电路适于考虑的一些区域是包括二或多个芯片的堆叠，而二或多个芯片的堆叠是使用相同或不同制造程序进行制造，以降低集成电路系统的占据面积(footprint)。
上文的“先前技术”说明仅是提供背景技术，并未承认上文的“先前技术”说明揭示本公开的标的，不构成本公开的先前技术，且上文的“先前技术”的任何说明均不应作为本案的任一部分。
发明内容
本公开的一实施例提供一种半导体封装。该半导体封装包括一第一晶粒、一第二晶粒、多个导电栓塞以及一重分布层。该重分布层包括一第一区段以及一第二区段，该第二区段与该第一区段电性绝缘。该重分布层的该第一区段电性连接该第一晶粒到该第二晶粒，且该重分布层的该第二区段电性连接该第一晶粒到所述导电栓塞。
在本公开的一些实施例中，该第一晶粒堆叠在该第二晶粒与所述导电栓塞上。
在本公开的一些实施例中，该重分布层的该第一区段设置在该第一晶粒与该第二晶粒之间，且该重分布层的该第二区段设置在该第一晶粒与所述导电栓塞之间。
在本公开的一些实施例中，该重分布层的该第二区段围绕该重分布层的该第一区段。
在本公开的一些实施例中，所述第二晶粒水平地配置以平行所述导电栓塞。
在本公开的一些实施例中，该半导体封装还包括：一介电层，包住该重分布层；一第一隔离材料，围绕该第一晶粒；以及一第二隔离材料，围绕该第二晶粒与所述导电栓塞。
在本公开的一些实施例中，该半导体封装还包括：一钝化层，覆盖该第二晶粒与所述导电栓塞；一导电层，穿经该钝化层，并包括一第一部分以及一第二部分，该第一部分连接到该第二晶粒，该第二部分连接到所述导电栓塞；以及多个焊料凸块(solder bumps)，贴焊在该导电层上。
本公开的另一实施例提供一种半导体封装组件的制备方法。该制备方法的步骤包括提供水平设置的多个第一晶粒；形成一重分布层以电性连接到所述第一晶粒，其中该重分布层划分成一第一区段以及一第二区段，该第二区段与该第一区段是电性绝缘；安装多个第二晶粒在该重分布层的该第一区段上；沉积一第二隔离材料在所述第二晶粒与该重分布层上；以及形成多个导电栓塞以穿经该第二隔离层，并接触该重分布层的该第二区段。
在本公开的一些实施例中，该制备方法还包括：形成至少一介电层以包住该重分布层。
在本公开的一些实施例中，该制备方法还包括：沉积一钝化层在所述第二晶粒、所述导电栓塞以及该第二隔离层上；形成一导电层以穿经该钝化层，其中该导电层包括一第一部分以及一第二部分，该第一部分电性耦接到所述第二晶粒，该第二部分与该第一部分电性绝缘，并接触所述导电栓塞；以及形成多个锡料凸块以连接到该导电层。
在本公开的一些实施例中，该制备方法还包括：执行一研磨(grinding)制程，以暴露所述第二晶粒的各导电线，其是在该钝化层沉积之前执行。
在本公开的一些实施例中，该第一隔离材料的一熔点(melting point)是大于该第二隔离材料的熔点。
在本公开的一些实施例中，所述第一晶粒之间具有一第一距离，所述第二晶粒之间具有一第二距离，且该第二距离小于该第一距离。
在本公开的一些实施例中，该第一区段设置在该重分布层的中心部位，且该第二区段围绕该第一区段。
在本公开的一些实施例中，所述第一晶粒与所述第二晶粒以该半导体封装的一中心轴而对称设置。
在本公开的一些实施例中，该制备方法还包括：在该重分布层形成之前以一第一隔离材料执行模造所述第一晶粒。
上文已相当广泛地概述本公开的技术特征及优点，而使下文的本公开详细描述得以获得较佳了解。构成本公开的权利要求标的的其它技术特征及优点将描述于下文。本公开所属技术领域中具有通常知识者应了解，可相当容易地利用下文揭示的概念与特定实施例可作为修改或设计其它结构或制程而实现与本公开相同的目的。本公开所属技术领域中具有通常知识者亦应了解，这类等效建构无法脱离后附的权利要求所界定的本公开的精神和范围。
附图说明
参阅实施方式与权利要求合并考量附图时，可得以更全面了解本申请案的揭示内容，附图中相同的元件符号是指相同的元件。
图1为依据本公开一些实施例中一种半导体封装的剖视示意图。
图2为依据本公开一些实施例中一种半导体封装的制备方法的流程示意图。
图3到图14为依据本公开一些实施例中在一种半导体封装的形成中的各个中间阶段的剖视示意图。
其中，附图标记说明如下：
10：半导体封装
30：制备方法
110：第一晶粒
112：接触垫
120：第二晶粒
122：接触垫
124：导电线
130：导电栓塞
140：重分布层
142：第一区段
144：第二区段
146：介电层
150：第一隔离材料
152：上表面
154：下表面
160：第二隔离材料
170：钝化层
180：导电层
182：第一部分
184：第二部分
190：锡料凸块
210：遮罩层
220：开孔
230：开孔
302：步骤
304：步骤
306：步骤
308：步骤
310：步骤
312：步骤
314：步骤
316：步骤
318：步骤
1102：前表面
1104：后表面
D1：第一距离
D2：第二距离
具体实施方式
本公开的以下说明伴随并入且组成说明书的一部分的图示，说明本公开的实施例，然而本公开并不受限于该实施例。此外，以下的实施例可适当整合以下实施例以完成另一实施例。
应当理解，虽然用语“第一(first)”、“第二(second)”、“第三(third)”等可用于本文中以描述不同的元件、部件、区域、层及/或部分，但是这些元件、部件、区域、层及/或部分不应受这些用语所限制。这些用语仅用于从另一元件、部件、区域、层或部分中区分一个元件、部件、区域、层或部分。因此，以下所讨论的“第一装置(firstelement)”、“部件(component)”、“区域(region)”、“层(layer)”或“部分(section)”可以被称为第二装置、部件、区域、层或部分，而不背离本文所教示。
本文中使用的术语仅是为了实现描述特定实施例的目的，而非意欲限制本发明。如本文中所使用，单数形式“一(a)”、“一(an)”，及“该(the)”意欲亦包括复数形式，除非上下文中另作明确指示。将进一步理解，当术语“包括(comprises)”及/或“包括(comprising)”用于本说明书中时，所述术语规定所陈述的特征、整数、步骤、操作、元件，及/或组件的存在，但不排除存在或增添一或更多个其他特征、整数、步骤、操作、元件、组件，及/或上述各者的群组。
图1为依据本公开一些实施例中一种半导体封装10的剖视示意图。请参考图1，半导体封装10可为一晶圆级(wafer-level)半导体封装，并包括一或多个第一晶粒110、一或多个第二晶粒120、多个导电栓塞130以及一重分布层140，而重分布层140具有一第一区段142以及至少一第二区段144，而第二区段144与第一区段142为电性绝缘，其中第一区段142电性连接所述第一晶粒110到所述第二晶粒120，且该第二区段144电性连接所述第一晶粒110到所述导电栓塞130。
水平设置的所述第一晶粒110可堆叠在所述第二晶粒120与所述导电栓塞130上，重分布层140的第一区段142设置在所述第一晶粒110与所述第二晶粒120之间，且重分布层140的第二区段144设置在所述第一晶粒110与所述导电栓塞130之间，以降低半导体封装10的一占据面积(footprint)。
在一些实施例中，第一晶粒110为一系统上芯片(system-on-chip，SoC)，其是包括一中央处理器(central processing unit，CPU)、一图形处理单元(graphics processingunit，GPU)、一动态随机存取存储器(dynamic random access memory，DRAM)控制器，或其组合。水平设置的所述第二晶粒120可为存储器晶粒，例如动态随机存取存储器(DRAM)晶粒。所述第一晶粒110具有一第一占据面积，且所述第二晶粒120具有一第二占据面积，而该第二占据面积小于该第一占据面积；因此，所述导电栓塞130可水平设置以平行所述第二晶粒120。在一些实施例中，围绕所述第二晶粒120的导电栓塞130是以等间隙(equally-spaced)架构进行配置。在一些实施例中，所述第一晶粒110之间具有一第一距离D1，且所述第二晶粒120之间具有一第二距离D2；第一距离S1大于第二距离D2，以促进散热。
半导体封装10还可包括一第一隔离材料150以及一第二隔离材料160，第一隔离材料150围绕所述第一晶粒110，第二隔离材料160围绕所述第二晶粒120与所述导电栓塞130。在一些实施例中，所述导电栓塞130是穿经第二隔离材料160并接触重分布层140的第二区段144，而所述导电栓塞130可具有一高度，是等于或大于所述第二晶粒120的高度。
在一些实施例中，半导体封装10还可包括一钝化层170、一导电层180以及多个锡料凸块190，而所述锡料凸块180电性耦接到导电层180。钝化层170覆盖所述第二晶粒120与所述导电栓塞130相对重分布层140设置的侧边。导电层180穿经钝化层170，并包括一第一部分182以及一第二部分184，第一部分182实体连接到所述第二晶粒120的各导电线(例如直通是穿孔(through silicon vias))124，第二部分184则实体连接到所述导电栓塞130。
图2为依据本公开一些实施例中一种半导体封装的制备方法30的流程示意图。图3到图14为依据本公开一些实施例中在一种半导体封装的形成中的各个中间阶段的剖视示意图。图3到图14所示的各阶段是亦示意地绘示在图2中的流程图。在下列的讨论中，图3到图14所示的各制造阶段是参考图2所述的处理步骤进行讨论。
请参考图3，依据图2中的一步骤302，提供以一第一隔离材料150模造一或多个第一晶粒110。由第一隔离材料150包住的所述第一晶粒110是水平设置。第一晶粒110具有一前表面1102以及一后表面1104，而后表面1104是相对前表面1102设置，其是经由第一隔离材料150暴露。在一些实施例中，第一晶粒110可包括多个接触垫112，连接到后表面1104。在一些实施例中，第一隔离材料150据以一上表面152以及一下表面154，上表面152与所述第一晶粒110的前表面1102为共面，下表面154与所述第一晶粒110的后表面1104为共面。以第一隔离材料150模造所述第一晶粒110的形成是包括(1)粘着所述第一晶粒110在一暂时载体(temporary carrier)上，其是借由一粘着层所执行；(2)涂敷一第一隔离材料以围绕所述第一晶粒110；以及(3)移除粘着层与暂时载体。在一些实施例中，暂时载体可包含硅、陶瓷(ceramics)、金属或其类似物，且粘着层为暂时性的，且为可剥离(strippable)或易于移除材料，举例来说，其是可使用膜(films)、胶带(tapes)、液态胶(liquid adhesives)。在一些实施例中，举例来说，第一隔离材料150可使用热固性模塑料(thermoset moldingcompounds)在一转换模压机(transfer mold press)中所形成。
请参考图4，依据图2中一步骤304，至少形成一重分布层140以连接到所述第一晶粒110的各接触垫112。重分布层140可包括多个金属层以及彼此堆叠的多个穿孔(vias)。重分布层140具有一第一区段142以及至少一第二区段144，第二区段144与第一区段142为电性绝缘。重分布层140的第二区段144可围绕重分布层140的第一区段142。换言之，重分布层140的第二区段144设置在第一区段142的一周围(periphery)。重分布层140可包含铝、铜、钨、钛、氮化钛或其类似物。
如图4所示，在一些实施例中，可形成至少一介电层146以包住重分布层140，进而减少重分布层140的腐蚀(corrosion)。在一些实施例中，介电层146还可覆盖所述第一晶粒110的后表面1104以及第一隔离材料150的下表面154。在一些实施例中，重分布层140远离所述第一晶粒110的一部分是经由介电层146暴露。在一些实施例中，介电层146的沉积温度是小于第一隔离材料150的熔点(melting point)，以避免第一隔离材料150断裂(breaking)。介电层146可包含有机材料或非有机材料(inorganic materials)，有机材料是例如聚亚酰胺(polyimide，PI)，而非有机材料是例如氮化硅或氧化硅。
请参考图5，依据图2中一步骤306，提供一或多个第二晶粒120，并安装在重分布层140的第一区段142上。据此，位在所述第一晶粒110与所述第二晶粒120之间的重分布层140的第一区段142，是当成所述第一晶粒110与所述第二晶粒120的一电性内连接。在一些实施例中，所述第二晶粒120可经由一或多个接触垫122电性连接到重分布层140，一或多个接触垫122是形成在所述第二晶粒120上。在一些实施例中，所述第一晶粒110与所述第二晶粒120是以一中心轴C而对称设置。
请参考图6，依据图2中的一步骤308，在所述第二晶粒120安装在重分布层140上之后，涂敷一第二隔离材料160以包住所述第二晶粒120。第二隔离材料160还可覆盖重分布层140与介电层146。在一些实施例中，第一隔离材料150与第二隔离材料160可具有不同组成(compositions)，以便第二隔离材料160可在相对较低温度下固化(cured)。
请参考图7，依据图2中的一步骤310，执行一研磨制程(grinding process)，以擦掉所述第二晶粒12与第二隔离材料160的一些部分。据此，暴露所述第二晶粒120的各导电线124。在一些实施例中，研磨制程包括一化学机械研磨(chemical mechanicalpolishing，CMP)制程及/或湿蚀刻制程。
请参考图8到图10，依据图2中一步骤312，形成多个导电栓塞130，以穿过第二隔离材料160，并接触重分布层140的第二区段144。所述导电栓塞130借由下列步骤所形成：提供一遮罩层210在第二隔离材料160上(如图8所示)；执行一蚀刻制程以移除第二隔离材料160未被遮罩层210覆盖的部分，以形成多个开孔220(如图9所示)；以及沉积一导电材料在所述开孔220中(如图10所示)。如图8所示，所述第二晶粒120是被遮罩层210所覆盖。在一些实施例中，举例来说，在执行蚀刻制程之后，遮罩层210是借由灰化(ashing)制程或湿式剥除(wet strip)制程而移除。在一些实施例中，导电材料可包含铜、铝、钨或其类似物，并借由使用一镀覆(electroplating)制程或一化学气相沉积(CVD)制程而沉积在所述开孔220中及在第二隔离材料160上。在一些实施例中，在导电材料沉积之后，可执行一平坦化制程，以暴露第二隔离材料160。在一些实施例中，平坦化制程包括一CMP制程及/或一湿蚀刻制程。
请参考图11，依据图2中一步骤314，沉积一钝化层170以覆盖所述第二晶粒120、所述导电栓塞130以及第二隔离材料160。在一些实施例中，钝化层170典型地以一低压CVD制程或一等离子体加强CVD制程所沉积。在钝化层170沉积之后，一平坦化制程是可选择地执行在钝化层170上以提供较佳的形貌(topography)，而平坦化制程是使用任何适合的方法，例如一回蚀(etch-back)制程或一CMP制程。
请参考图12，在钝化层170沉积之后，多个开孔230可形成在钝化层170中，以暴露所述第二晶粒120的相对应的导电线124以及所述导电栓塞130。在一些实施例中，所述开孔230的形成包括：(1)形成一光阻图案(图未示)在钝化层170上，其中光阻图案界定出一图案以蚀刻进入钝化层170；(2)执行一第三蚀刻制程，是使用光阻图案当作一遮罩，以蚀刻钝化层170，藉此形成所述开孔230在钝化层170中；(3)移除光阻图案。
请参考图13，依据图2中的一步骤316，一或多个导电材料沉积在钝化层170上以及在所述开孔230中，以形成一导电层180。导电层180可划分成一第一部分182以及一第二部分184，第一部分182实体连接到所述导电县124，而第二部分184则实体连接到所述导电栓塞130。
请参考图14，依据图2中一步骤318，多个锡料凸块190沉积在导电层180上。在一些实施例中，所述锡料凸块190是借由下列方式贴焊：初始置放一助焊剂(solder flux)(图未示)在导电层180上，然后设置所述锡料凸块190在助焊剂上，而一旦所述锡料凸块190接触助焊剂时，可执行一回焊(reflow)以回焊所述锡料凸块190与助焊剂的材料，进而实体接合所述锡料凸块190到导电层180。在一些实施例中，导电层180的第一部分182可当作是所述第二晶粒120与所述锡料凸块190的一电性内连接，而导电层180的第二部分184可当作是导电栓塞130与锡料凸块190的一电性内连接。
综上所述，由于半导体封装10的架构，所述第一晶粒110堆叠在所述第二晶粒120与所述导电栓塞130上，且所述第一晶粒110水平配置，以缩减半导体封装10的占据面积(footprint)。
本公开的一实施例提供一种半导体封装。该半导体封装包括一第一晶粒、一第二晶粒、多个导电栓塞以及一重分布层。该重分布层包括一第一区段以及一第二区段，该第二区段与该第一区段电性绝缘。该重分布层的该第一区段电性连接该第一晶粒到该第二晶粒，且该重分布层的该第二区段电性连接该第一晶粒到所述导电栓塞。
本公开的另一实施例提供一种半导体封装组件的制备方法。该制备方法的步骤包括提供水平设置的多个第一晶粒；形成一重分布层以电性连接到所述第一晶粒，其中该重分布层划分成一第一区段以及一第二区段，该第二区段与该第一区段是电性绝缘；安装多个第二晶粒在该重分布层的该第一区段上；沉积一第二隔离材料在所述第二晶粒与该重分布层上；以及形成多个导电栓塞以穿经该第二隔离层，并接触该重分布层的该第二区段。
虽然已详述本公开及其优点，然而应理解可进行各种变化、取代与替代而不脱离权利要求所定义的本公开的精神与范围。例如，可用不同的方法实施上述的许多制程，并且以其他制程或其组合替代上述的许多制程。
再者，本申请的范围并不受限于说明书中所述的制程、机械、制造、物质组成物、手段、方法与步骤的特定实施例。该技艺的技术人士可自本公开的揭示内容理解可根据本公开而使用与本文所述的对应实施例具有相同功能或是达到实质上相同结果的现存或是未来发展的制程、机械、制造、物质组成物、手段、方法、或步骤。据此，此等制程、机械、制造、物质组成物、手段、方法、或步骤是包含于本申请的权利要求内。

Claims (15)

1.一种半导体封装组件的制备方法，包括：
提供水平设置的多个第一晶粒；
形成一重分布层以电性连接到所述第一晶粒，其中该重分布层划分成一第一区段以及一第二区段，该第二区段与该第一区段是电性绝缘；
安装多个第二晶粒在该重分布层的该第一区段上；
沉积一第二隔离材料在所述第二晶粒与该重分布层上；以及
形成多个导电栓塞以穿经一第二隔离层，并接触该重分布层的该第二区段；
沉积一钝化层在所述第二晶粒、所述导电栓塞以及该第二隔离层上；
形成一导电层以穿经该钝化层，其中该导电层包括一第一部分以及一第二部分，该第一部分电性耦接到所述第二晶粒，该第二部分与该第一部分电性绝缘，并接触所述导电栓塞；以及
形成多个锡料凸块以连接到该导电层。
2.如权利要求1所述的制备方法，还包括：形成至少一介电层以包住该重分布层。
3.如权利要求1所述的制备方法，还包括：执行一研磨制程，以暴露所述第二晶粒的各导电线，其是在该钝化层沉积之前执行。
4.如权利要求1所述的制备方法，其中，所述第一晶粒之间具有一第一距离，所述第二晶粒之间具有一第二距离，且该第二距离小于该第一距离。
5.如权利要求1所述的制备方法，其中，该第一区段设置在该重分布层的中心部位，且该第二区段围绕该第一区段。
6.如权利要求1所述的制备方法，其中，所述第一晶粒与所述第二晶粒以该半导体封装组件的一中心轴而对称设置。
7.如权利要求1所述的制备方法，还包括：在该重分布层形成之前以一第一隔离材料执行模造所述第一晶粒。
8.如权利要求7所述的制备方法，其中，该第一隔离材料的一熔点大于该第二隔离材料的熔点。
9.一种根据权利要求1-8中任一项所述的半导体封装组件的制备方法制备的半导体封装，包括：
至少一第一晶粒；
至少一第二晶粒；
多个导电栓塞；以及
一重分布层，包括一第一区段以及一第二区段，该第二区段与该第一区段电性绝缘，该第一区段电性连接该第一晶粒到该第二晶粒，该第二区段电性连接该第一晶粒到所述导电栓塞。
10.如权利要求9所述的半导体封装，其中，该第一晶粒堆叠在该第二晶粒与所述导电栓塞上。
11.如权利要求9所述的半导体封装，其中，该重分布层的该第一区段设置在该第一晶粒与该第二晶粒之间，且该重分布层的该第二区段设置在该第一晶粒与所述导电栓塞之间。
12.如权利要求9所述的半导体封装，其中，该重分布层的该第二区段围绕该重分布层的该第一区段。
13.如权利要求9所述的半导体封装，其中，所述第二晶粒水平地配置以平行所述导电栓塞。
14.如权利要求9所述的半导体封装，还包括：
一介电层，包住该重分布层；
一第一隔离材料，围绕该第一晶粒；以及
一第二隔离材料，围绕该第二晶粒与所述导电栓塞。
15.如权利要求9所述的半导体封装，还包括：
一钝化层，覆盖该第二晶粒与所述导电栓塞；
一导电层，穿经该钝化层，并包括一第一部分以及一第二部分，该第一部分连接到该第二晶粒，该第二部分连接到所述导电栓塞；以及
多个焊料凸块，贴焊在该导电层上。
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US20240063178A1 (en) * 2022-08-19 2024-02-22 Intel Corporation Quasi-monolithic die architectures

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150129348A (ko) * 2014-05-12 2015-11-20 앰코 테크놀로지 코리아 주식회사 재배선층을 이용한 적층형 반도체 패키지 및 이의 제조 방법
CN106653705A (zh) * 2015-10-05 2017-05-10 联发科技股份有限公司 半导体封装结构

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8446017B2 (en) * 2009-09-18 2013-05-21 Amkor Technology Korea, Inc. Stackable wafer level package and fabricating method thereof
KR101560216B1 (ko) * 2012-12-27 2015-10-14 삼성전자 주식회사 다층형 광학 필름 및 표시 장치
US9478474B2 (en) * 2012-12-28 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for forming package-on-packages
US9768145B2 (en) * 2015-08-31 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming multi-die package structures including redistribution layers
TWI611577B (zh) 2016-03-04 2018-01-11 矽品精密工業股份有限公司 電子封裝件及半導體基板
US9831148B2 (en) * 2016-03-11 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package including voltage regulators and methods forming same
US20170366906A1 (en) * 2016-06-16 2017-12-21 Andy Lambert Hearing device with embedded die stack
US10050024B2 (en) 2016-06-17 2018-08-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US10008417B1 (en) 2017-06-12 2018-06-26 International Business Machines Corporation Vertical transport fin field effect transistors having different channel lengths
KR102491103B1 (ko) * 2018-02-06 2023-01-20 삼성전자주식회사 반도체 패키지 및 그 제조방법
WO2021048977A1 (ja) * 2019-09-12 2021-03-18 昭和電工マテリアルズ株式会社 圧縮成形用封止材及び電子部品装置
EP4067408A4 (en) * 2019-11-27 2022-12-28 Unitika Ltd. FLEXIBLE POLYAMIDE FILM

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150129348A (ko) * 2014-05-12 2015-11-20 앰코 테크놀로지 코리아 주식회사 재배선층을 이용한 적층형 반도체 패키지 및 이의 제조 방법
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