CN220774343U - 半导体封装 - Google Patents
半导体封装 Download PDFInfo
- Publication number
- CN220774343U CN220774343U CN202321513613.6U CN202321513613U CN220774343U CN 220774343 U CN220774343 U CN 220774343U CN 202321513613 U CN202321513613 U CN 202321513613U CN 220774343 U CN220774343 U CN 220774343U
- Authority
- CN
- China
- Prior art keywords
- integrated circuit
- interposer
- circuit device
- die
- heat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims description 113
- 230000017525 heat dissipation Effects 0.000 claims description 33
- 230000001070 adhesive effect Effects 0.000 claims description 27
- 239000000853 adhesive Substances 0.000 claims description 25
- 238000003892 spreading Methods 0.000 claims description 19
- 230000007480 spreading Effects 0.000 claims description 19
- 238000005538 encapsulation Methods 0.000 claims description 12
- 239000010410 layer Substances 0.000 description 100
- 238000000034 method Methods 0.000 description 79
- 230000008569 process Effects 0.000 description 68
- 239000000463 material Substances 0.000 description 37
- 239000012809 cooling fluid Substances 0.000 description 16
- 239000004020 conductor Substances 0.000 description 15
- 229910000679 solder Inorganic materials 0.000 description 15
- 229910052751 metal Inorganic materials 0.000 description 14
- 239000002184 metal Substances 0.000 description 14
- 238000001465 metallisation Methods 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- 229910052802 copper Inorganic materials 0.000 description 10
- 239000010949 copper Substances 0.000 description 10
- 229910052737 gold Inorganic materials 0.000 description 9
- 239000010931 gold Substances 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000005498 polishing Methods 0.000 description 7
- 239000000126 substance Substances 0.000 description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- 229920000642 polymer Polymers 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 229920002577 polybenzoxazole Polymers 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- LYCAIKOWRPUZTN-UHFFFAOYSA-N Ethylene glycol Chemical compound OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 3
- DNIAPMSPPWPWGF-UHFFFAOYSA-N Propylene glycol Chemical compound CC(O)CO DNIAPMSPPWPWGF-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910005540 GaP Inorganic materials 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 2
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 238000000748 compression moulding Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 150000001247 metal acetylides Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 239000011135 tin Substances 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- NEHMKBQYUWJMIP-UHFFFAOYSA-N chloromethane Chemical compound ClC NEHMKBQYUWJMIP-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000000109 continuous material Substances 0.000 description 1
- 239000002826 coolant Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000011133 lead Substances 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229920000058 polyacrylate Polymers 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
本实用新型实施例的各种实施例涉及一种半导体封装。所述半导体封装包括:中介层;第一集成电路装置,贴合至中介层,其中第一集成电路装置包括晶粒及散热结构,所述晶粒具有面朝中介层的有源表面及与有源表面相对的非有源表面,所述散热结构贴合至晶粒的非有源表面且包括自散热结构的第一表面凹陷的多个沟道,散热结构的第一表面背朝晶粒;以及包封体,设置于中介层上且在侧向上围绕晶粒及散热结构,其中包封体的顶表面与散热结构的顶表面共面。
Description
技术领域
本实用新型实施例涉及一种半导体封装。
背景技术
由于各种电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成密度的不断提高,半导体行业已经历快速发展。在很大程度上,集成密度的提高源于最小特征大小(minimum feature size)的不断减小,此使得能够将更多的组件整合至给定的面积中。随着对日益缩小的电子装置的需求的增长,出现了对更小且更具创造性的半导体晶粒封装技术的需求。
实用新型内容
在一些实施例中,本实用新型实施例提供一种半导体封装。所述半导体封装包括:中介层;第一集成电路装置,贴合至中介层,其中第一集成电路装置包括晶粒及散热结构,所述晶粒具有面朝中介层的有源表面及与有源表面相对的非有源表面,所述散热结构贴合至晶粒的非有源表面且包括自散热结构的第一表面凹陷的多个沟道,散热结构的第一表面背朝晶粒;以及包封体,设置于中介层上且在侧向上围绕晶粒及散热结构,其中包封体的顶表面与散热结构的顶表面共面。在实施例中,所述封装还包括夹置于晶粒与散热结构之间的氧化物层。在实施例中,晶粒与散热结构具有相同的宽度。
在一些实施例中,本实用新型实施例提供一种半导体封装。所述半导体封装包括:中介层;集成电路装置,接合至中介层的前侧,其中集成电路装置包括晶粒及散热结构,晶粒具有面朝中介层的有源表面及与中介层相对的非有源表面,散热结构设置于晶粒上且包括自散热结构的顶表面凹陷的多个沟道;包封体,设置于中介层上且在侧向上环绕集成电路装置;以及盖,设置于包封体及散热结构上,其中盖在所述多个沟道之上延伸。在实施例中,散热结构的顶表面与包封体的顶表面共面。在实施例中,所述封装还包括:衬底,贴合至中介层的与中介层的前侧相对的后侧;以及环形结构,设置于盖与衬底之间,环形结构在侧向上环绕中介层、包封体及集成电路装置。
附图说明
结合附图阅读以下详细说明,会最好地理解本实用新型实施例的各个方面。应注意,根据本行业中的标准惯例,各种特征并未按比例绘制。事实上,为使论述清晰起见,可任意增大或减小各种特征的尺寸。
图1是根据一些实施例的集成电路晶粒的剖视图。
图2A及图2B分别示出根据一些实施例的集成电路装置的剖视图及平面图。
图3至图5是根据一些实施例的制造集成电路装置中的中间阶段的剖视图。
图6至图18A、图19、图20A是根据一些实施例的制造集成电路封装中的中间阶段的剖视图。
图18B及图20B是根据一些实施例的制造集成电路封装中的中间阶段的平面图。
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本实用新型实施例。当然,这些仅为实例而非旨在进行限制。举例来说,在以下说明中,在第二特征之上或第二特征上形成第一特征可包括其中第一特征与第二特征被形成为直接接触的实施例,且也可包括其中在第一特征与第二特征之间可形成附加特征从而使得第一特征与第二特征可不直接接触的实施例。另外,本实用新型实施例可在各种实例中重复使用参考编号和/或字母。此种重复使用是为了简明及清晰起见,且自身并不表示所讨论的各种实施例和/或配置之间的关系。
此外,为易于说明,本文中可能使用例如“在…之下(beneath)”、“在…下方(below)”、“下部的(lower)”、“在…上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示一个元件或特征与另一(其他)元件或特征的关系。除了图中所绘示的取向以外,所述空间相对性用语还旨在囊括装置在使用或操作中的不同取向。设备可具有其他取向(旋转90度或处于其他取向),且本文所用的空间相对性描述语可同样相应地作出解释。
根据各种实施例,形成一种包括贴合至中介层的集成电路装置的封装。所述集成电路装置可包括位于集成电路晶粒之上的散热结构。所述散热结构可包括自所述散热结构的顶表面凹陷的多个微沟道,所述多个微沟道可使得冷却流体能够流通,且因此可有效地散失由封装中的集成电路晶粒及/或其他集成电路装置产生的热量。封装的散热效率可得以提高。
图1示出集成电路晶粒50的剖视图。在随后的处理中将对一或多个集成电路晶粒50进行封装以形成集成电路封装。每一集成电路晶粒50可为逻辑晶粒(例如,中央处理单元(central processing unit,CPU)、图形处理单元(graphics processing unit,GPU)、微控制器等)、存储器晶粒(例如,动态随机存取存储器(dynamic random access memory,DRAM)晶粒、静态随机存取存储器(static random access memory,SRAM)晶粒等)、电源管理晶粒(例如,电源管理集成电路(powermanagement integrated circuit,PMIC)晶粒)、射频(radio frequency,RF)晶粒、界面晶粒、传感器晶粒、微机电系统(micro-electro-mechanical-system,MEMS)晶粒、讯号处理晶粒(例如,数字讯号处理(digital signalprocessing,DSP)晶粒)、前端晶粒(例如,模拟前端(analog front-end,AFE)晶粒)、应用集成电路(application-specific integrated circuit,ASIC)、类似晶粒或其组合(例如,系统芯片(system-on-a-chip,SoC)晶粒)。集成电路晶粒50可形成于晶片中,所述晶片可包括不同的晶粒区,在后续步骤中对所述晶粒区进行单体化以形成多个集成电路晶粒50。集成电路晶粒50包括半导体衬底52、内连线结构54、晶粒连接件56及介电层58(若存在)。
半导体衬底52可为经掺杂或未经掺杂的硅衬底、或者绝缘体上半导体(semiconductor-on-insulator,SOI)衬底的有源层。半导体衬底52可包含:其他半导体材料,例如锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟;合金半导体,包括硅-锗、砷磷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟及/或砷磷化镓铟;或其组合。亦可使用例如多层式衬底(multi-layered substrate)或梯度衬底(gradientsubstrate)等其他衬底。半导体衬底52具有有源表面(例如,图1中面朝下的表面)及非有源表面(例如,图1中面朝上的表面)。装置位于半导体衬底52的有源表面处。所述装置可为有源装置(例如,晶体管、二极管等)及/或无源装置(例如,电容器、电阻器等)。非有源表面可不存在装置。
内连线结构54位于半导体衬底52的有源表面上,且用于对半导体衬底52的装置进行电性连接以形成集成电路。内连线结构54可包括一或多个介电层及位于介电层中的相应的一或多个金属化层。用于介电层的可接受的介电材料包括:氧化物,例如氧化硅或氧化铝;氮化物,例如氮化硅;碳化物,例如碳化硅;类似材料;或其组合,例如氮氧化硅、碳氧化硅、碳氮化硅、碳氮氧化硅或类似材料。亦可使用例如聚合物(例如,聚苯并恶唑(polybenzoxazole,PBO)、聚酰亚胺、苯并环丁烯(benzocyclobuten,BCB)系聚合物)或类似材料等其他介电材料。金属化层可包括导通孔及/或导电线以对半导体衬底52的装置进行内连。金属化层可由导电材料(例如,金属(例如,铜、钴、铝、金)、其组合或类似材料)形成。内连线结构54可藉由镶嵌工艺(例如,单镶嵌工艺、双镶嵌工艺或类似工艺)形成。
晶粒连接件56位于集成电路晶粒50的前侧50F处。晶粒连接件56可为进行外部连接的导电柱、接垫或类似组件。晶粒连接件56位于内连线结构54中及/或内连线结构54上。举例而言,晶粒连接件56可为内连线结构54的上部金属化层的一部分。晶粒连接件56可由金属(例如,铜、铝或类似材料)形成且可藉由例如镀覆或类似工艺形成。
介电层58可选地设置于集成电路晶粒50的前侧50F处。介电层58位于内连线结构54中及/或内连线结构54上。举例而言,介电层58可为内连线结构54的上部介电层。介电层58在侧向上包封晶粒连接件56。介电层58可为氧化物、氮化物、碳化物、聚合物、类似材料或其组合。介电层58可例如藉由旋转涂布、迭层、化学气相沉积(chemical vapordeposition,CVD)或类似工艺形成。最初,介电层58可掩埋晶粒连接件56,使得介电层58的顶表面位于晶粒连接件56的顶表面上方。在集成电路晶粒50的形成期间,晶粒连接件56由介电层58暴露出。暴露出晶粒连接件56可移除晶粒连接件56上可能存在的任何焊料区。可将移除工艺应用于各种层以移除晶粒连接件56之上的过量材料。移除工艺可为平坦化工艺,例如化学机械抛光(chemical mechanicalpolish,CMP)、回蚀、其组合或类似工艺。在平坦化工艺之后,晶粒连接件56的顶表面与介电层58的顶表面共面(在工艺变化范围内),且在集成电路晶粒50的前侧50F处被暴露出。
图2A及图2B分别是根据一些实施例的第一集成电路装置80A的剖视图及平面图。第一集成电路装置80A可包括贴合至集成电路晶粒50(参见例如图1)的散热结构60。在一些实施例中,散热结构60包括块状衬底62且可不包括金属化层、有源装置或非有源装置或类似装置。块状衬底62可由具有高导热率(thermal conductivity)的材料(例如,硅、相似于半导体衬底52的半导体材料或类似材料)形成。散热结构60亦可被称为虚设晶粒或热增强(thermal enhancement)晶粒。
在一些实施例中,散热结构60亦包括嵌入于块状衬底62中的多个条带64。所述多个条带64可沿着纵向方向(例如,进出图2A中所示的剖视图的平面的方向)延伸且自块状衬底62的顶表面被暴露出。条带64可具有与块状衬底62的顶表面共面的顶表面。条带64可形成为规则的图案,例如平面图中的矩形条带重复图案。举例而言,相邻条带64可具有介于20微米至700微米的范围内的节距P。在一些实施例中,条带64中的每一者具有介于30微米至100微米的范围内的宽度W及介于50微米至600微米的高度H1。高度H1对宽度W的比率可介于1至15的范围内。在一些实施例中,条带64具有相对于块状衬底62的顶表面实质上垂直或倾斜的直的侧壁。在一些实施例中,条带64包含聚合物材料(例如,环氧树脂、聚丙烯酸酯、聚酰亚胺或其组合)、或者可适合藉由蚀刻工艺自块状衬底62上移除的任何材料。如以下将更详细地论述般,将会移除条带64的材料以形成使得用于散热的冷却流体能够流通的沟道。出于例示目的示出条带的规则图案,且亦可使用规则或不规则的其他图案。
散热结构60可藉由直接接合或粘合层贴合至集成电路晶粒50。举例而言,在其中散热结构60藉由直接接合贴合至集成电路晶粒50的一些实施例中,散热结构60的底表面直接接合至集成电路晶粒50的非有源表面。在此种实施例中,可在散热结构60的块状衬底62及集成电路晶粒50的半导体衬底52中的一者或两者上形成接合膜66(例如,氧化硅层)以有助于接合工艺。在其中散热结构60藉由粘合层贴合至集成电路晶粒50的实施例中,接合膜66可为热界面材料。热接口材料可为聚合材料、焊料膏(solder paste)、铟焊料膏或类似材料。
图3至图5示出根据一些实施例的形成针对图2A所阐述的结构的示例性流程。图3中示出具有多个沟渠68的空白晶片60A。空白晶片60A可包括块状衬底62A,块状衬底62A是如针对图1所阐述的半导体衬底52的晶片形式且在随后的处理中将被单体化成如图2A中所示的多个块状衬底62。所述多个沟渠68可形成于块状衬底62A中。在一些实施例中,沟渠68可具有与条带64相同的图案(例如,具有宽度W及节距P),且可具有与条带64的高度H1相同的深度。沟渠68的形成可包括:在块状衬底62A的顶表面上形成经图案化掩模(未示出)(例如,包括沟渠68的图案的硬掩模),且根据经图案化掩模的图案对块状衬底62A进行蚀刻。蚀刻工艺可包括干式蚀刻,例如反应离子蚀刻(reactive ion etching,RIE)或类似工艺。在形成沟渠68之后,可藉由任何可接受的可移除工艺(例如,湿式蚀刻或干式蚀刻)来移除经图案化掩模。
在图4中,根据一些实施例,对沟渠68进行填充以在块状衬底62A中形成多个条带64。在一些实施例中,条带64是藉由化学气相沉积(chemical vapor deposition,CVD)、旋转涂布、迭层或类似工艺形成。条带64的成形材料可对沟渠68进行填充,且可在块状衬底62A的顶表面之上具有过量部分(未示出)。可实行平坦化工艺(例如,化学机械抛光(CMP)或机械研磨)以移除条带64的材料的位于块状衬底62A的顶表面之上的过量部分,留下嵌入于块状衬底62A中且自块状衬底62A的顶表面暴露出的条带64。在一些实施例中,空白晶片60A的厚度可藉由自空白晶片60A的底表面对其进行研磨来进行调整。
在图5中,形成或提供包括多个集成电路晶粒50的晶片50A,并将包括条带64的空白晶片60A贴合至晶片50A。在一些实施例中,空白晶片60A的块状衬底62A藉由晶片对晶片接合(wafer-to-waferbonding)而接合至晶片50A。举例而言,块状衬底62A的底表面可贴合至晶片50A的非有源表面(例如,半导体衬底52的非有源表面)。晶片对晶片接合可使用直接接合或使用例如如上所论述的接合膜66的粘合来实行。尽管本文未详细示出,但应理解,亦可藉由其他合适的技术来实施晶片对晶片接合。
图5进一步示出沿着切割道69对空白晶片60A、接合膜66及晶片50A进行单体化以形成各别的接合晶粒结构(例如,图2A中所示的第一集成电路装置80A)。图5示出单个切割道69以形成两个第一集成电路装置80A是出于例示目的,而实施例可包括任意数目的切割道以形成更多的各别结构(例如,图2A中所示的那些结构)。
图6至图17是根据一些实施例的制造包括第一集成电路装置80A(参见图2A)的集成电路封装100的中间阶段的剖视图。首先参考图6,图6示出中介层70。中介层70可为晶片,且可使用晶片上芯片(chip-on-wafer,CoW)技术将多个第一集成电路装置80A贴合至中介层70,且之后对其进行单体化以形成各别的封装。亦应理解,本揭露中所示出的实施例亦可应用于三维集成电路(Three-Dimensional Integrated Circuit,3DIC)封装。
在图6中,获得或形成中介层70。在一些实施例中,中介层70包括衬底72、内连线结构74及穿孔76。衬底72可为体半导体衬底、绝缘体上半导体(SOI)衬底、多层式半导体衬底或类似衬底。衬底72可包含:半导体材料,例如硅;锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟;合金半导体,包括硅-锗、砷磷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟及/或砷磷化镓铟;或其组合。亦可使用例如多层式衬底或梯度衬底等其他衬底。衬底72可为经掺杂的或未经掺杂的。在一些实施例中,尽管中介层可包括形成于衬底72的前表面(例如,图3中面朝上的表面)中及/或所述表面上的无源装置,但衬底72中不包括有源装置。
内连线结构74位于衬底72的前表面之上,且用于对衬底72的装置(若存在)及/或贴合至中介层70的装置进行电性连接。内连线结构74可包括一或多个介电层及位于所述介电层中的相应金属化层。用于介电层的可接受的介电材料包括:氧化物,例如氧化硅或氧化铝;氮化物,例如氮化硅;碳化物,例如碳化硅;类似材料;或其组合,例如氮氧化硅、碳氧化硅、碳氮化硅、碳氮氧化硅或类似材料。亦可使用例如聚合物(例如,聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)系聚合物)或类似材料等其他介电材料。金属化层可包括导通孔及/或导电线,以将任意装置内连于一起及/或内连至外部装置。金属化层可由导电材料(例如,金属(例如,铜、钴、铝、金)、其组合或类似材料)形成。内连线结构74可藉由镶嵌工艺(例如,单镶嵌工艺、双镶嵌工艺或类似工艺)形成。
在一些实施例中,晶粒连接件及介电层(未单独示出)位于中介层70的前侧70F处。具体而言,中介层70可包括与针对图1所阐述的集成电路晶粒50的晶粒连接件及介电层相似的晶粒连接件及介电层。举例而言,晶粒连接件及介电层可为内连线结构74的上部金属化层的一部分。
穿孔76延伸至内连线结构74及/或衬底72中。穿孔76电性连接至内连线结构74的金属化层。作为形成穿孔76的实例,可藉由例如蚀刻、铣削(milling)、激光技术、其组合及/或类似方法在内连线结构74及/或衬底72中形成凹槽。可例如藉由利用氧化技术在凹槽中形成薄的介电材料。可例如藉由CVD、原子层沉积(atomic layer deposition,ALD)、物理气相沉积(physical vapor deposition,PVD)、热氧化、其组合、及/或类似工艺在开口中共形地沉积薄的阻障层。阻障层可由氧化物、氮化物、碳化物、其组合或类似材料形成。可在阻障层之上及开口中沉积导电材料。导电材料可藉由电化学镀覆工艺、CVD、ALD、PVD、其组合及/或类似工艺来形成。导电材料的实例为铜、钨、铝、银、金、其组合及/或类似材料。可藉由例如CMP自内连线结构74的表面或衬底72的表面移除过量的导电材料及阻障层。阻障层的剩余部分及导电材料的剩余部分形成穿孔76。
图7示出贴合至中介层70的第一集成电路装置80A及第二集成电路装置80B,其中第二集成电路装置80B与第一集成电路装置80A统称为集成电路装置80。第二集成电路装置80B可为存储器晶粒、存储器晶粒的堆叠、集成电路晶粒(与针对图1所阐述的集成电路晶粒50相似)、或集成电路晶粒堆叠或类似装置。第一集成电路装置80A可具有与第二集成电路装置80B不同的功能。举例而言,第一集成电路装置80A可为逻辑设备,例如中央处理单元(CPU)、图形处理单元(GPU)、系统芯片(SoC)、微控制器、专用集成电路(ASIC)或类似装置。第二集成电路装置80B可为存储器装置,例如动态随机存取存储器(DRAM)装置、静态随机存取存储器(SRAM)装置、混合存储器立方(hybrid memory cube,HMC)模块、高带宽存储器(highbandwidth memory,HBM)模块或类似装置。第一集成电路装置80A与第二集成电路装置80B可以相同技术节点的工艺形成,或者可以不同技术节点的工艺形成。举例而言,第一集成电路装置80A可具有较第二集成电路装置80B更先进的工艺节点。
在图7中,集成电路装置80利用焊料接合(例如,经由导电连接件82)贴合至中介层70。可使用例如取放工具(pick-and-place tool)将集成电路装置80放置于内连线结构74上。导电连接件82可由可回焊的导电材料(例如,焊料)形成,且可还包括其他导电材料,例如铜、铝、金、镍、银、钯、锡、铅、类似材料或其组合。在一些实施例中,藉由最初透过例如蒸镀、电镀、印刷、焊料转移、植球或类似方法等方法形成焊料层来形成导电连接件82。一旦已在中介层70上形成焊料层,便可实行回焊,以便将导电连接件82造型成所期望的凸块形状。将集成电路装置80贴合至中介层70可包括将集成电路装置80放置于中介层70上且对导电连接件82进行回焊。导电连接件82在中介层70与集成电路装置80的对应晶粒连接件之间形成接头(joint),将中介层70电性连接至集成电路装置80。
可在导电连接件82周围形成底部填充胶84,且底部填充胶84位于中介层70与集成电路装置80之间。底部填充胶84可减小应力并保护因导电连接件82的回焊而产生的接头。底部填充胶84可由底部填充胶材料(例如,环氧树脂或类似材料)形成。可在集成电路装置80贴合至中介层70之后藉由毛细流动工艺(capillary flow process)形成底部填充胶84,或者可在集成电路装置80贴合至中介层70之前藉由合适的沉积方法形成底部填充胶84。可以液体形式或半液体形式施加底部填充胶84,且然后随后将其固化。端视第一集成电路装置80A与第二集成电路装置80B之间的距离而定,底部填充胶84可具有各种高度。在所示的实施例中,底部填充胶84可具有大于集成电路晶粒50的高度,且与第一集成电路装置80A的散热结构60的侧壁接触。在一些实施例中,底部填充胶84的顶表面高于条带64的底表面。在图中未示出的一些实施例中,底部填充胶84具有与散热结构60的顶表面齐平的顶表面。
在图8中,在中介层70及中介层70上的各种组件之上形成包封体90。在形成之后,包封体90对集成电路装置80及底部填充胶84进行包封。包封体90可为模制化合物(其可为聚合物、树脂、环氧树脂或类似材料)、以及基础材料中的填料粒子。填料粒子可为由SiO2、Al2O3或类似物形成的介电粒子,且可具有球形形状。此外,球形填料粒子可具有多种不同的直径。包封体90可藉由压缩模制(compression molding)、转移模制(transfer molding)或类似工艺来施加,且形成于中介层70之上以使得散热结构60及集成电路装置80被掩埋或覆盖。可以液体或半液体形式施加包封体90,且然后随后将其固化。
在图9中,对包封体90进行薄化以暴露出第一集成电路装置80A。在一些实施例中,亦可如图9中所示地暴露出第二集成电路装置80B。具体而言,薄化会移除包封体90的覆盖第一集成电路装置80A的散热结构60的顶表面的部分,藉此暴露出散热结构60。在一些实施例中,薄化亦包括移除第二集成电路装置80B的一部分及/或第一集成电路装置80A的散热结构60(包括条带64)的一部分。在薄化工艺之后,第一集成电路装置80A的散热结构60的顶表面与包封体90的顶表面共面(在工艺变化范围内)。此外,第二集成电路装置80B中的一或多者的顶表面亦可与第一集成电路装置80A的散热结构60的顶表面及包封体90的顶表面共面(在工艺变化范围内)。在一些实施例中,条带64的高度H2介于自40微米至590微米的范围内。在薄化之后,高度H2对宽度W的比率可为自1至15。在一些实施例中,高度H2对散热结构60的总厚度H3(在薄化工艺之后)的比率介于自0.1至0.77的范围内。厚度H3可介于自400微米至775微米的范围内。薄化工艺可为研磨工艺、化学机械抛光(CMP)、回蚀、其组合或类似工艺。
在图10中,可在载体衬底96或其他合适的支撑结构上放置中间结构以进行后续处理。举例而言,载体衬底96可经由释放层98贴合至第一集成电路装置80A、第二集成电路装置80B及包封体90。在一些实施例中,载体衬底96是例如具有晶片形状或面板形状或类似形状的体半导体衬底或玻璃衬底等衬底。释放层98可由聚合物系材料形成,其可在处理之后与载体衬底96一起自所述结构移除。在一些实施例中,释放层98为当受热时失去其粘合性质的环氧树脂系热释放材料,例如光热转换(light-to-heat-conversion,LTHC)释放涂层。
在图11中,对中介层70进行薄化以暴露出穿孔76。穿孔76的暴露可藉由薄化工艺(例如,研磨工艺、化学机械抛光(CMP)、回蚀、其组合或类似工艺)来完成。在所示出的实施例中,实行凹陷工艺以使衬底72的后表面凹陷,使得穿孔76在中介层70的后侧70B处突出。凹陷工艺可为例如合适的回蚀工艺、化学机械抛光(CMP)或类似工艺。在一些实施例中,用于暴露出穿孔76的薄化工艺包括CMP,且穿孔76由于在CMP或单独的凹陷蚀刻工艺期间发生的中凹(dishing)而在中介层70的后侧70B处突出。在衬底72的后表面上可选地形成绝缘层102,绝缘层102环绕穿孔76的突出部分。在一些实施例中,绝缘层102由含硅绝缘体(例如,氮化硅、氧化硅、氮氧化硅或类似材料)形成,且可藉由合适的沉积方法(例如,旋转涂布、CVD、等离子体增强CVD(plasma-enhanced CVD,PECVD)、高密度等离子体CVD(high-densityplasma CVD,HDP-CVD)或类似工艺)形成。最初,绝缘层102可掩埋穿孔76。可对各种层应用移除工艺以移除穿孔76之上的过量材料。移除工艺可为平坦化工艺,例如化学机械抛光(CMP)、回蚀、其组合或类似工艺。在平坦化之后,穿孔76的被暴露出的表面与绝缘层102的被暴露出的表面共面(在工艺变化范围内),且在中介层70的后侧70B处暴露出。在另一实施例中,会省略绝缘层102,且衬底72的被暴露出的表面与穿孔76的被暴露出的表面共面(在工艺变化范围内)。
可在穿孔76的被暴露出的表面及绝缘层102(或衬底72(当省略绝缘层102时))的被暴露出的表面上形成凸块下金属(underbump metallurgy,UBM)104。作为形成UBM 104的实例,在穿孔76的被暴露出的表面及绝缘层102(若存在)的被暴露出的表面或衬底72的被暴露出的表面之上形成晶种层(未单独示出)。在一些实施例中,晶种层是金属层,其可为单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层及位于钛层之上的铜层。可使用例如PVD或类似工艺形成晶种层。然后在晶种层上形成光刻胶并进行图案化。可藉由旋转涂布或类似工艺形成光刻胶,且可将所述光刻胶暴露于光以进行图案化。光刻胶的图案对应于UBM 104。所述图案化会形成穿过光刻胶的开口以暴露出晶种层。然后在光刻胶的开口中及晶种层的被暴露出的部分上形成导电材料。可藉由镀覆(例如,电镀(electroplating)或无电镀覆(electroless plating))或者类似工艺形成导电材料。所述导电材料可包括金属,例如铜、钛、钨、铝或类似材料。然后,移除光刻胶及晶种层的上面未形成导电材料的部分。可藉由例如使用氧等离子体或类似材料的可接受的灰化工艺(ashing process)或剥除工艺(stripping process)来移除光刻胶。一旦光刻胶被移除,便例如藉由使用可接受的蚀刻工艺来移除晶种层的被暴露出的部分。晶种层的剩余部分及导电材料的剩余部分形成UBM 104。
此外,在UBM 104上形成导电连接件106。导电连接件106可为球栅阵列(ball gridarray,BGA)连接件、焊料球、金属柱、受控塌陷芯片连接(controlled collapse chipconnection,C4)凸块、微凸块、无电镀镍钯浸金技术(electroless nickel-electrolesspalladium-immersion gold technique,ENEPIG)形成的凸块或类似组件。导电连接件106可由可回焊的导电材料(例如,焊料、铜、铝、金、镍、银、钯、锡、类似材料或其组合)形成。在一些实施例中,藉由最初透过蒸镀、电镀、印刷、焊料转移、植球或类似工艺形成焊料层来形成导电连接件106。一旦已在所述结构上形成焊料层,便可实行回焊,以便将所述材料造型成所期望的凸块形状。在一些实施例中,导电连接件106包括藉由溅镀、印刷、电镀、无电镀覆、CVD或类似工艺形成的金属柱(例如铜柱)。金属柱可不含焊料,且具有实质上垂直的侧壁。在一些实施例中,在金属柱的顶部上形成金属顶盖层(metal cap layer)。金属顶盖层可包含镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金、类似材料或其组合,且可藉由镀覆工艺来形成。
在图12中,在载体衬底120或其他合适的支撑结构上放置中间结构以进行后续处理。举例而言,载体衬底120可经由释放层122而贴合至导电连接件106及中介层70的后侧70B。举例而言,释放层122可具有大于导电连接件106的厚度,以避免导电连接件106触及载体衬底120,此可能会减少对导电连接件106的损坏。释放层122可具有与释放层98相似的材料,例如当受热时会失去其粘合性质的热释放材料,例如LTHC释放涂层。在一些实施例中,载体衬底120为具有晶片形状或面板形状或类似形状的体半导体衬底或玻璃衬底。
在图13中,实行载体剥离工艺以将载体衬底96(参见图12)自第一集成电路装置80A、第二集成电路装置80B及包封体90分离(剥离),藉此暴露出嵌入于散热结构60中的条带64。剥离包括自载体衬底96的顶侧投射光(例如,激光或紫外(ultraviolet,UV)光)以对释放层98进行局部加热。藉此,释放层98可在光的局部分布的热量下分解,且可移除载体衬底96,而中介层70的后侧70B上的释放层122可不会受影响。
在图14中,根据一些实施例,移除嵌入于散热结构60中的条带64,藉此在第一集成电路装置80A的散热结构60中形成微沟道126。在一些实施例中,微沟道126具有与条带64的形状对应的形状,例如具有宽度W、节距P及高度H2。在一些实施例中,使用合适的酸性蚀刻溶液或碱性蚀刻溶液藉由湿式蚀刻来移除条带64。如以下将更详细地论述般,微沟道126可使得冷却流体(例如水、碳氟化合物或其他合适的冷却剂)能够流通,且冷却流体可有效地将集成电路封装100中由第一集成电路装置80A及/或其他装置所产生的热量传递出去。
在图15中,实行载体剥离以将载体衬底120(参见图14)自中介层70的后侧70B分离(剥离)。剥离包括对光(例如,激光或紫外光)进行投射以对释放层122进行加热。因此,释放层122可在光的加热下分解,且可移除载体衬底120。
可以晶片级实行以上所论述的工艺,其中中介层70为晶片大小,且实行单体化工艺。举例而言,可将中间结构放置于胶带(未示出)上,且藉由沿着切割道区进行剖切来实行单体化工艺以形成如图15中所示的结构。单体化工艺可包括锯切(sawing)、切块(dicing)或类似工艺。举例而言,单体化工艺可包括对绝缘层102、包封体90、内连线结构74及衬底72进行锯切。单体化工艺将晶片大小的中介层70单体化成单独的封装。作为单体化工艺的结果,中介层70的外侧壁与包封体90的外侧壁在侧向上毗连(在工艺变化范围内)。
在图16中,使用导电连接件106将图15中所获得的单体化封装中的一或多者贴合至衬底150。衬底150可为中介层、核心衬底、无核心衬底、印刷电路板(printedcircuitboard,PCB)、封装衬底或类似组件。衬底150可包括有源装置及/或无源装置(未单独示出)。装置(例如,晶体管、电容器、电阻器、其组合及类似装置)可用于产生系统设计的结构需求及功能需求。所述装置可利用任何合适的方法形成。
衬底150亦可包括金属化层及通孔(未单独示出)以及位于金属化层及通孔之上的接合接垫152。导电连接件106可包括进行回焊以将UBM 104贴合至接合接垫152的焊料。导电连接件106将中介层70的内连线结构74的金属化层电性连接至衬底150(包括衬底150中的金属化层)。因此,衬底150电性连接至集成电路装置80。在一些实施例中,无源装置(例如,表面安装装置(surface mount device,SMD)(未单独示出))可在安装至衬底150上之前贴合至中介层70的后侧70B(例如,接合至UBM 104)。在此种实施例中,无源装置可与导电连接件106接合至衬底150的同一表面。
在一些实施例中,在中介层70与衬底150之间形成底部填充胶156,底部填充胶156环绕导电连接件106及UBM 104。可在对衬底150进行贴合之后藉由毛细流动工艺形成底部填充胶156,或者可在对衬底150进行贴合之前藉由合适的沉积方法形成底部填充胶156。底部填充胶156可为自衬底150延伸至中介层70(例如,绝缘层102)的连续材料。
出于例示目的示出了上述制造工艺,然而制造工艺并非仅限于此。根据一些实施例,亦可实施合适的结构变化及/或工艺变化。举例而言,可在对中介层70进行薄化之前(参见图10)移除条带64。在一些实施例中,如图9中所示,在对包封体90进行薄化以暴露出条带64之后,可实行条带64的移除以形成微沟道126(例如,藉由如图14中所示的移除工艺)。接下来,参考图17,可将载体衬底96贴合至包封体90及散热结构60,并藉由释放层98对微沟道126进行密封。然后,除可省略图12及图14中所示的工艺(由于条带64已被移除)以外,可实行与图11至图16中所示的工艺相似的工艺。如此一来,可得到与图16中所示的结构相似的结构。释放层98的一些残留物可能会落入微沟道126中,且可藉由在任何制造阶段进行合适的清洁工艺或者藉由流经微沟道126的冷却流体来移除所述残留物。
图18A及图18B分别示出根据一些实施例的集成电路封装100的中间结构的剖视图及平面图,其中图18A是沿着图18B中所示的截面X-X’的剖视图。如图18A中所示,使用粘合剂162将散热环160贴合至衬底150。散热环160可在侧向上环绕集成电路装置80及包封体90。接下来,使用粘合剂166将盖164贴合至第二集成电路装置80B(若被暴露出)、包封体90及/或散热环160。举例而言,如图18A中所示,粘合剂166设置于散热环160、第二集成电路装置80B及包封体90的相邻于第二集成电路装置80B的部分上。出于例示目的,粘合剂166被示出为不延伸至第一集成电路装置80A的散热结构60,且使得包封体90的相邻于第一集成电路装置80A的一部分被暴露出。在一些实施例中,粘合剂166可完全地覆盖包封体90或者在散热结构60的一部分之上延伸。如此一来,散热结构60中的微沟道126可能仍会被暴露出且并未由粘合剂166进行密封。
盖164覆盖散热结构60且包括入口/出口开口164A。盖164与粘合剂166、包封体90及散热结构60的块状衬底62一起在入口/出口开口164A之间形成空腔170,且流体可在散热结构60之上流经所述空腔。在一些实施例中,冷却流体可流经入口/出口开口164A中的一者,流入至空腔170及微沟道126中,并经由入口/出口开口164A中的另一者流出。入口/出口开口164A可设置于能够连接至空腔170的任何位置处且可具有任何合适的数量及形状。举例而言,图18B示出入口/出口开口164A的实例。入口/出口开口164A可相邻于微沟道126设置且连接至空腔170。入口/出口开口164A、空腔170及微沟道126可统称为散热路径172。
冷却流体可为水、碳氟化合物、氯碳化合物、乙二醇、丙二醇、其组合或其他合适的冷却材料。在一些实施例中,当集成电路封装100正在运作时,冷却流体可连续地流经散热路径172(包括流经散热结构60中的微沟道126),使得由第一集成电路装置80A产生的热量可藉由流动的冷却流体有效地传递出去。由第二集成电路装置80B产生的热量藉由粘合剂166、盖164及散热环160进行传递且经由衬底150散失出去。由于盖164及粘合剂166可与空腔170接触,因此由第二集成电路装置80B产生的热量的至少一部分亦可藉由冷却流体传递出去。
在一些实施例中,粘合剂162与粘合剂166由相同的材料形成。在一些实施例中,粘合剂162的材料不同于粘合剂166的材料。举例而言,粘合剂166可具有较粘合剂162更佳的密封性质以防止/减少冷却流体的泄漏。在一些实施例中,散热环160及盖164可由以下材料制成:金属或金属合金,例如铝、铜、镍、钴、其合金或其组合;或者其他材料,例如碳化硅、氮化铝、石墨及类似材料。在一些实施例中,散热环160是与盖164相同的材料。
图19示出根据一些实施例的集成电路封装200的中间结构的剖视图。集成电路封装200可包括与集成电路封装100相似的特征,其中相同的参考编号指代相同的组件。如图19中所示,根据一些实施例,集成电路封装200不具有散热环,且盖264藉由粘合剂266直接贴合至第二集成电路装置80B及包封体90。出于例示目的,粘合剂266被示出为不延伸至第一集成电路装置80A的散热结构60,且使得包封体90的相邻于第一集成电路装置80A的一部分被暴露出。在一些实施例中,粘合剂266完全覆盖包封体90或者在散热结构60的一部分之上延伸。在一些实施例中,粘合剂266由与粘合剂166相似的材料形成。在一些实施例中,尽管亦可使用及涵盖其他宽度,然而盖264具有与包封体90相同的宽度。在所示出的实施例中,尽管由第二集成电路装置80B产生的热量无法经由散热环散失至衬底150,然而所述热量可经由盖264及流经散热路径172的冷却流体传递出去,且获得紧凑的集成电路封装。
图20A及图20B分别示出集成电路封装300的中间结构的剖视图及平面图,其中图20A是沿着图20B中所示的截面Y-Y’的剖视图。在图20B中,以虚线示出微沟道126。集成电路封装300可包括与集成电路封装100相似的特征,其中相同的参考编号指代相同的组件。如图20A中所示,粘合剂366设置于散热环160上,且盖164与第一集成电路装置80A的散热结构60、第二集成电路装置80B及包封体90接触。如此一来,盖164可设置于微沟道126的顶部之上。盖164可与第一集成电路装置80A的散热结构60接触且至少部分地对微沟道126进行密封。冷却流体可经入口/出口开口164B中的一者流入至微沟道126中,且经由入口/出口开口164B中的另一者流出。参考图20B,入口/出口开口164B可延伸穿过多个微沟道126以使得冷却流体能够流经所有微沟道126。应理解,图20B中的两个矩形的入口/出口开口164B仅是用于例示目的,且亦可使用及涵盖任何数量、位置及形状的入口/出口开口164B。由于第二集成电路装置80B可与盖164直接接触,因此自第二集成电路装置80B至盖164的热传导效率可得到提高,但并非仅限于此。
根据一些实施例,提供一种包括贴合至中介层的集成电路装置的封装及其形成方法。在一些实施例中,集成电路装置包括贴合至集成电路晶粒的非有源表面的散热结构。散热结构可包括可使得冷却流体可流通的自散热结构的顶表面凹陷的多个微沟道。因此,由封装中的集成电路装置及/或其他集成电路装置产生的热量可经由可连续流经微沟道的冷却流体传递出去。封装的散热效率可得以提高。
在实施例中,一种封装包括:中介层;第一集成电路装置,贴合至中介层,其中第一集成电路装置包括晶粒及散热结构,所述晶粒具有面朝中介层的有源表面及与有源表面相对的非有源表面,所述散热结构贴合至晶粒的非有源表面且包括自散热结构的第一表面凹陷的多个沟道,散热结构的第一表面背朝晶粒;以及包封体,设置于中介层上且在侧向上围绕晶粒及散热结构,其中包封体的顶表面与散热结构的顶表面共面。在实施例中,所述封装还包括夹置于晶粒与散热结构之间的氧化物层。在实施例中,晶粒与散热结构具有相同的宽度。在实施例中,所述封装还包括第二集成电路装置,所述第二集成电路装置贴合至中介层且相邻于第一集成电路装置设置,其中第二集成电路装置在侧向上被包封体环绕且具有与包封体的顶表面共面的顶表面。在实施例中,所述封装还包括盖,所述盖使用粘合剂贴合至包封体,其中盖在散热结构中的沟道的部分之上延伸。在实施例中,盖包括延伸穿过盖的第一开口及第二开口,其中盖、粘合剂及散热结构形成自第一开口延伸至第二开口的空腔。在实施例中,盖具有与包封体相同的宽度。在实施例中,封装还包括底部填充胶,所述底部填充胶设置于中介层上且与散热结构的侧壁接触。在实施例中,沟道的底表面低于底部填充胶的顶表面。
在实施例中,一种封装包括:中介层;集成电路装置,接合至中介层的前侧,其中集成电路装置包括晶粒及散热结构,晶粒具有面朝中介层的有源表面及与中介层相对的非有源表面,散热结构设置于晶粒上且包括自散热结构的顶表面凹陷的多个沟道;包封体,设置于中介层上且在侧向上环绕集成电路装置;以及盖,设置于包封体及散热结构上,其中盖在所述多个沟道之上延伸。在实施例中,散热结构的顶表面与包封体的顶表面共面。在实施例中,所述封装还包括:衬底,贴合至中介层的与中介层的前侧相对的后侧;以及环形结构,设置于盖与衬底之间,环形结构在侧向上环绕中介层、包封体及集成电路装置。在实施例中,盖与集成电路装置的散热结构及包封体接触。在实施例中,盖与包封体具有相同的宽度。在实施例中,盖还包括穿过盖的开口。
在实施例中,提供一种用于形成封装的方法。所述方法包括:将集成电路装置贴合至中介层,其中集成电路装置包括第一晶粒及第一散热结构,第一晶粒具有面朝中介层的有源表面及与有源表面相对的非有源表面,所述第一散热结构包括贴合至第一晶粒的非有源表面的半导体衬底,第一散热结构包括多个条带,所述多个条带嵌入于半导体衬底中且自半导体衬底的顶表面暴露出,其中所述多个条带包含不同于半导体衬底的材料;在中介层上设置包封体,包封体在侧向上环绕第一晶粒及第一散热结构,包封体在所述多个条带之上延伸;实行薄化工艺以移除包封体的一部分且暴露出所述多个条带;以及移除所述多个条带以在第一散热结构中形成沟道。在实施例中,薄化工艺包括:移除半导体衬底的一部分及所述多个条带的一部分。在实施例中,藉由将第一晶片与第二晶片接合且然后锯切第一晶片及第二晶片来形成集成电路装置,其中第一晶片包括多个晶粒且第二晶片包括多个散热结构,其中第一晶粒是所述多个晶粒中的一者,其中第一散热结构是所述多个散热结构中的一者。在实施例中,移除所述多个条带包括湿式蚀刻工艺。在实施例中,所述方法还包括:在移除所述多个条带之后,将盖贴合至包封体的顶表面,所述盖在沟道之上具有第一开口及第二开口。
以上概述了若干实施例的特征,以使所属领域中的技术人员可更好地理解本实用新型实施例的各个方面。所属领域中的技术人员应理解,其可容易地使用本实用新型实施例作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的和/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到,这些等效构造并不背离本实用新型实施例的精神及范围,而且他们可在不背离本实用新型实施例的精神及范围的条件下对其作出各种改变、替代及变更。
Claims (10)
1.一种半导体封装,其特征在于,包括:
中介层;
第一集成电路装置,贴合至所述中介层,其中所述第一集成电路装置包括晶粒及散热结构,所述晶粒具有面朝所述中介层的有源表面及与所述有源表面相对的非有源表面,所述散热结构贴合至所述晶粒的所述非有源表面且包括自所述散热结构的第一表面凹陷的多个沟道,所述散热结构的所述第一表面背朝所述晶粒;以及
包封体,设置于所述中介层上且在侧向上围绕所述晶粒及所述散热结构,其中所述包封体的顶表面与所述散热结构的顶表面共面。
2.根据权利要求1所述的半导体封装,其特征在于,所述晶粒与所述散热结构具有相同的宽度。
3.根据权利要求1所述的半导体封装,其特征在于,还包括第二集成电路装置,所述第二集成电路装置贴合至所述中介层且相邻于所述第一集成电路装置设置,其中所述第二集成电路装置在侧向上被所述包封体环绕且具有与所述包封体的所述顶表面共面的顶表面。
4.根据权利要求1所述的半导体封装,其特征在于,还包括盖,所述盖使用粘合剂贴合至所述包封体,其中所述盖在所述散热结构中的所述多个沟道的多个部分之上延伸。
5.根据权利要求4所述的半导体封装,其特征在于,所述盖包括延伸穿过所述盖的第一开口及第二开口,其中所述盖、所述粘合剂及所述散热结构形成自所述第一开口延伸至所述第二开口的空腔。
6.根据权利要求4所述的半导体封装,其特征在于,所述盖具有与所述包封体相同的宽度。
7.一种半导体封装,其特征在于,包括:
中介层;
集成电路装置,接合至所述中介层的前侧,其中所述集成电路装置包括晶粒及散热结构,所述晶粒具有面朝所述中介层的有源表面及与所述中介层相对的非有源表面,所述散热结构设置于所述晶粒上且包括自所述散热结构的顶表面凹陷的多个沟道;
包封体,设置于所述中介层上且在侧向上环绕所述集成电路装置;以及
盖,设置于所述包封体及所述散热结构上,其中所述盖在所述多个沟道之上延伸。
8.根据权利要求7所述的半导体封装,其特征在于,所述散热结构的所述顶表面与所述包封体的顶表面共面。
9.根据权利要求7所述的半导体封装,其特征在于,还包括:
衬底,贴合至所述中介层的与所述中介层的所述前侧相对的后侧;以及
环形结构,设置于所述盖与所述衬底之间,所述环形结构在侧向上环绕所述中介层、所述包封体及所述集成电路装置。
10.根据权利要求7所述的半导体封装,其特征在于,所述盖还包括穿过所述盖的开口。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/856,689 | 2022-07-01 | ||
US17/856,689 US20240006270A1 (en) | 2022-07-01 | 2022-07-01 | Package with Improved Heat Dissipation Efficiency and Method for Forming the Same |
Publications (1)
Publication Number | Publication Date |
---|---|
CN220774343U true CN220774343U (zh) | 2024-04-12 |
Family
ID=89433497
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202321513613.6U Active CN220774343U (zh) | 2022-07-01 | 2023-06-14 | 半导体封装 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20240006270A1 (zh) |
CN (1) | CN220774343U (zh) |
TW (1) | TW202403989A (zh) |
-
2022
- 2022-07-01 US US17/856,689 patent/US20240006270A1/en active Pending
-
2023
- 2023-02-15 TW TW112105330A patent/TW202403989A/zh unknown
- 2023-06-14 CN CN202321513613.6U patent/CN220774343U/zh active Active
Also Published As
Publication number | Publication date |
---|---|
US20240006270A1 (en) | 2024-01-04 |
TW202403989A (zh) | 2024-01-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11694943B2 (en) | Semiconductor device including heat dissipation structure and fabricating method of the same | |
US9685411B2 (en) | Integrated circuit dies having alignment marks and methods of forming same | |
US11830866B2 (en) | Semiconductor package with thermal relaxation block and manufacturing method thereof | |
US11282791B2 (en) | Semiconductor device having a heat dissipation structure connected chip package | |
US20230387057A1 (en) | Integrated circuit package and method | |
US9391028B1 (en) | Integrated circuit dies having alignment marks and methods of forming same | |
KR20130054115A (ko) | 반도체 패키지 및 반도체 소자 패키징 방법 | |
US20230014913A1 (en) | Heat Dissipation Structures for Integrated Circuit Packages and Methods of Forming the Same | |
US20230378015A1 (en) | Integrated circuit package and method | |
US20220359360A1 (en) | Multi-chip system-in-package | |
CN220774343U (zh) | 半导体封装 | |
CN221102070U (zh) | 封装体 | |
TWI838124B (zh) | 具有改善的散熱效率的封裝及其形成方法 | |
CN220543895U (zh) | 具有改善的散热效率的封装 | |
US20240145342A1 (en) | Package with Heat Dissipation Structure and Method for Forming the Same | |
US20240162109A1 (en) | Package with Improved Heat Dissipation Efficiency and Method for Forming the Same | |
US20230402339A1 (en) | Molding Structures for Integrated Circuit Packages and Methods of Forming the Same | |
US20240128148A1 (en) | Integrated Circuit Packages and Methods of Forming the Same | |
CN220400576U (zh) | 器件封装及半导体封装 | |
US11715646B2 (en) | Semiconductor structure and method for forming the same | |
US20240088093A1 (en) | Integrated Circuit Packages and Methods of Forming the Same | |
US20240006268A1 (en) | Package structure and method of fabricating the same | |
US20240014095A1 (en) | Semiconductor package and method | |
TW202418515A (zh) | 封裝體及其製造方法 | |
US20230402346A1 (en) | Heat dissipation structures for integrated circuit packages and methods of forming the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GR01 | Patent grant | ||
GR01 | Patent grant |