TWI838124B - 具有改善的散熱效率的封裝及其形成方法 - Google Patents
具有改善的散熱效率的封裝及其形成方法 Download PDFInfo
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- TWI838124B TWI838124B TW112105383A TW112105383A TWI838124B TW I838124 B TWI838124 B TW I838124B TW 112105383 A TW112105383 A TW 112105383A TW 112105383 A TW112105383 A TW 112105383A TW I838124 B TWI838124 B TW I838124B
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- semiconductor device
- package
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- heat dissipation
- forming
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Abstract
在實施例中,提供一種封裝。所述封裝包括:半導體裝置;包封體,在側向上環繞半導體裝置;以及散熱結構,設置於半導體裝置及包封體之上,其中散熱結構包括多個柱及在所述多個柱的側壁之上延伸的多孔層。
Description
本發明的實施例是有關於一種具有改善的散熱效率的封裝及其形成方法。
由於各種電子組件(例如,電晶體、二極體、電阻器、電容器等)的積體密度的不斷提高,半導體行業已經歷快速發展。在很大程度上,積體密度的提高源於最小特徵大小(minimum feature size)的迭代減小,此使得能夠將更多的組件整合至給定的面積中。隨著對日益縮小的電子裝置的需求的增長,出現了向更小且更具創造性的半導體晶粒封裝技術發展的趨勢。
本發明的實施例提供一種封裝包括:半導體裝置;包封體,在側向上環繞半導體裝置;以及散熱結構,設置於半導體裝置及包封體之上,其中散熱結構包括多個柱及在所述多個柱的側壁
之上延伸的多孔層。
本發明的實施例提供一種封裝包括:半導體裝置,包括第一表面;包封體,相鄰於半導體裝置而設置,包封體包括與半導體裝置的第一表面共面的第二表面;以及散熱結構,貼合至半導體裝置的第一表面及包封體的第二表面,其中散熱結構包括多個柱及在所述柱之上延伸的多孔層。
本發明的實施例提供一種形成封裝的方法包括:形成在側向上環繞半導體裝置的包封體;以及在半導體裝置及包封體之上設置散熱結構,其中散熱結構包括多個柱、多個溝槽及沿所述柱的側壁及頂表面延伸的多孔層。
50:積體電路晶粒
50F:前側
52:半導體基底
54:內連線結構
56:晶粒連接件
58、312、316、320:介電層
60、60A、60B:半導體裝置
61:有效側
62:非有效側
64、74:載體基底
66、76:釋放層
70:包封體
70A:第一側
70B:第二側
72、96、330:導電性連接件
78:接合膜
80、580:散熱結構
82、88、94:基底
84、584:溝槽
85、585:柱
86、586:多孔層
90:環結構
92、98:底部填充膠
100、300、500、600:半導體封裝
100D:裝置區
100S:劃片區
200:散熱系統
202:罐
204:冷卻流體
206:馬達
210:冷凝器
302:重佈線結構
314、318:金屬化圖案
324:UBM
485:聚合物層
485A:微粒子
486:層
502:經圖案化罩幕
504:晶種層
506:開口
D:深度
P:節距
W:寬度
X-X’:截面
結合附圖閱讀以下詳細說明,會最佳地理解本揭露的各個態樣。應注意,根據本行業中的標準慣例,各種特徵並非按比例繪製。事實上,為使論述清晰起見,可任意增大或減小各種特徵的尺寸。
圖1是根據一些實施例的積體電路晶粒的剖視圖。
圖2至圖8、圖9A以及圖10至圖12是根據一些實施例的半導體封裝的製造中的中間階段的剖視圖。
圖9B及圖9C是根據一些實施例的半導體封裝的製造中的中間階段的平面圖。
圖13是根據一些實施例的散熱系統的剖視圖。
圖14至圖17是根據一些實施例的半導體封裝的製造中的中間階段的剖視圖。
圖18、圖19、圖20A、圖21A及圖22A是根據一些實施例的散熱結構的製造中的中間階段的剖視圖。
圖20B、圖21B及圖22B是根據一些實施例的散熱結構的聚合物層或多孔層的放大圖。
圖23至圖27是根據一些實施例的半導體封裝的製造中的中間階段的剖視圖。
以下揭露內容提供用於實施本發明的不同特徵的諸多不同實施例或實例。以下闡述組件及佈置的具體實例以簡化本揭露。當然,該些僅為實例且不旨在進行限制。舉例而言,以下說明中將第一特徵形成於第二特徵之上或第二特徵上可包括其中第一特徵與第二特徵被形成為直接接觸的實施例,且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵進而使得第一特徵與第二特徵可不直接接觸的實施例。另外,本揭露可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的,而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外,為易於說明,本文中可能使用例如「位於......之下(beneath)」、「位於......下方(below)」、「下部的(lower)」、「位於......上方(above)」、「上部的(upper)」及類似用語等空間相對
性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。設備可具有其他定向(旋轉90度或處於其他定向),且本文中所使用的空間相對性闡述語可同樣相應地進行解釋。
根據各種實施例,根據一些實施例,提供一種具有改善散熱效率及能力的半導體封裝。在一些實施例中,所述半導體封裝包括設置於半導體裝置之上的散熱結構以及圍繞半導體裝置的包封體。散熱結構包括用於提供高的表面積以提高散熱效率的多孔層(porous layer)。所述半導體封裝亦可被設計成在冷卻流體(cooling fluid)中進行操作。
圖1是積體電路晶粒50的剖視圖。在隨後的處理中,將對一或多個積體電路晶粒50進行封裝以形成積體電路封裝。每一積體電路晶粒50可為邏輯晶粒(例如,中央處理單元(central processing unit,CPU)、圖形處理單元(graphics processing unit,GPU)、微控制器等)、記憶體晶粒(例如,動態隨機存取記憶體(dynamic random access memory,DRAM)、靜態隨機存取記憶體(static random access memory,SRAM)晶粒等)、電源管理晶粒(例如,電源管理積體電路(power management integrated circuit,PMIC)晶粒)、射頻(radio frequency,RF)晶粒、介面晶粒、感測器晶粒、微機電系統(micro-electro-mechanical-system,MEMS)晶粒、訊號處理晶粒(例如,數位訊號處理(digital signal processing,
DSP)晶粒)、前端晶粒(例如,類比前端(analog front-end,AFE)晶粒)、應用專用積體電路(application-specific integrated circuit,ASIC)晶粒、類似晶粒或其組合(例如,系統晶片(system-on-a-chip,SoC)晶粒)。可將積體電路晶粒50形成於晶圓中,所述晶圓可包括在隨後的步驟中被單體化以形成多個積體電路晶粒50的不同晶粒區。積體電路晶粒50包括半導體基底52、內連線結構54、晶粒連接件56及介電層58(若存在)。
半導體基底52可為經摻雜或未經摻雜的矽基底,或者可為絕緣體上半導體(semiconductor-on-insulator,SOI)基底的有效層(active layer)。半導體基底52可包含:其他半導體材料,例如鍺;化合物半導體,包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦;合金半導體,包括矽鍺、磷砷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦及/或磷砷化鎵銦;或者其組合。亦可使用其他基底,例如多層式基底(multi-layered substrate)或梯度基底(gradient substrate)。半導體基底52具有有效側(active side)(例如,在圖1中面朝上的表面)及非有效側(inactive side)(例如,在圖1中面朝下的表面)。半導體基底52的有效側處具有裝置。所述裝置可為主動裝置(例如,電晶體、二極體等)、電容器、電阻器等。非有效側可不具有裝置。
內連線結構54位於半導體基底52的有效側上,且用於對半導體基底52的裝置進行電性連接以形成積體電路。內連線結構54可包括一或多個介電層以及位於介電層中的相應金屬化層。
用於介電層的可接受的介電材料包括:氧化物,例如氧化矽或氧化鋁;氮化物,例如氮化矽;碳化物,例如碳化矽;類似材料;或者其組合,例如氮氧化矽、碳氧化矽、碳氮化矽、碳氮氧化矽或類似材料。亦可使用其他介電材料,例如聚合物,所述聚合物為例如聚苯並噁唑(polybenzoxazole,PBO)、聚醯亞胺、苯並環丁烯(benzocyclobutene,BCB)系聚合物或類似聚合物。金屬化層可包括導通孔(conductive via)及/或導線(conductive line)以對半導體基底52的裝置進行內連。金屬化層可由例如金屬(例如銅、鈷、鋁、金、其組合或類似金屬)等導電材料形成。內連線結構54可藉由例如單鑲嵌製程(single damascene process)、雙鑲嵌製程(dual damascene process)或類似製程等鑲嵌製程來形成。
積體電路晶粒50的前側50F處具有晶粒連接件56。晶粒連接件56可為與外部進行連接的接墊、導電柱、接墊上導電柱(conductive pillars on pads)或類似元件。晶粒連接件56位於內連線結構54中及/或位於內連線結構54上。舉例而言,晶粒連接件56可包括作為內連線結構54的上部金屬化層的至少一部分。晶粒連接件56可由金屬(例如,銅、鋁或類似金屬)形成,且可藉由例如鍍覆(plating)或類似製程來形成。
積體電路晶粒50的前側50F處可選地設置有介電層58。介電層58(若存在)位於內連線結構54中及/或位於內連線結構54上。舉例而言,介電層58可為內連線結構54的上部介電層,且可包封晶粒連接件56的至少一部分。在一些實施例中,介電層
58是氧化物、氮化物、碳化物、聚合物、類似材料或其組合。介電層58可例如藉由旋轉塗佈(spin coating)、疊層(lamination)、化學氣相沈積(chemical vapor deposition,CVD)或類似製程來形成。
儘管圖1中僅示出共面的晶粒連接件56與介電層58,然而晶粒連接件56可突出於介電層58之上、與介電層58共面或者由介電層58覆蓋。晶粒連接件56可在介電層58之後形成。舉例而言,介電層58中可形成有用於晶粒連接件56的開口,且晶粒連接件56形成於所述開口中及介電層58上。作為另外一種選擇,可首先形成晶粒連接件56,且隨後形成介電層58以用於包封晶粒連接件56。在此種實施例中,介電層58可具有位於晶粒連接件56的頂表面上方的頂表面。在一些實施例中,晶粒連接件56藉由例如化學機械研磨(chemical mechanical polish,CMP)、機械磨製(mechanical grinding)、回蝕(etch-back)、其組合或類似製程等移除製程而經由介電層58暴露出,然而亦可在積體電路晶粒50的形成中省略所述移除製程,且可在半導體封裝的製造中實行所述移除製程。
圖2至圖11是根據一些實施例的半導體封裝100的製造中的中間階段的剖視圖。半導體封裝100可為倒裝晶片封裝(flip-chip package),其可包括利用導電性連接件而貼合至基底的一或多個半導體裝置。在一些實施例中,在半導體裝置的非有效側之上形成散熱結構或者將散熱結構貼合至半導體裝置的非有效側,
以提供具有改善的散熱效率及能力的半導體封裝100。
根據一些實施例,半導體封裝100的製造包括將一或多個半導體裝置貼合至載體基底64或其他適合的支撐結構,以供後續處理。舉例而言,在圖2中,在載體基底64上放置半導體裝置60A及半導體裝置60B,然而亦可使用任何數量的半導體裝置60A及半導體裝置60B。在一些實施例中,半導體裝置60A及半導體裝置60B的有效側61背對載體基底64,且半導體裝置60A及半導體裝置60B的非有效側62面對載體基底64。在一些實施例中,半導體裝置60A及半導體裝置60B可為圖1中闡述的積體電路晶粒50、積體電路晶粒50的堆疊或者包括積體電路晶粒50的封裝。在一些實施例中,半導體裝置60A及半導體裝置60B彼此相似。作為另外一種選擇,半導體裝置60A可具有與半導體裝置60B不同的功能。舉例而言,半導體裝置60A可為邏輯裝置,例如中央處理單元(CPU)、圖形處理單元(GPU)、系統晶片(SoC)、微控制器、應用專用積體電路(ASIC)或類似裝置,而半導體裝置60B可為記憶體裝置,例如動態隨機存取記憶體(DRAM)裝置、靜態隨機存取記憶體(SRAM)裝置、混合記憶體立方體(hybrid memory cube,HMC)模組、高頻寬記憶體(high bandwidth memory,HBM)模組或類似裝置。可在同一技術節點的製程中形成半導體裝置60A與半導體裝置60B,或者可在不同技術節點的製程中形成半導體裝置60A與半導體裝置60B。舉例而言,半導體裝置60A的製程節點可較半導體裝置60B更先進。在一些實施例中,半導體裝置
60A與半導體裝置60B具有不同的大小,例如不同的高度及/或底面積。
根據一些實施例,藉由釋放層66將半導體裝置60A及半導體裝置60B貼合至載體基底64。載體基底64可為呈晶圓形狀、面板形狀或類似形狀的塊狀半導體基底或玻璃基底。釋放層66可由可在處理之後與載體基底64一起自所述結構移除的聚合物系材料形成。在一些實施例中,釋放層66是在被加熱時失去其黏合性質的環氧樹脂系熱釋放材料,例如光熱轉換(light-to-heat-conversion,LTHC)釋放塗層。
在圖3中,根據一些實施例,在載體基底64之上以及半導體裝置60A及半導體裝置60B之上形成包封體70。舉例而言,半導體裝置60A及半導體裝置60B的有效側61可由包封體70掩埋或覆蓋。包封體70可為模製化合物,所述模製化合物可包括聚合物系材料(例如樹脂、環氧樹脂或類似材料)以及位於所述聚合物系材料中的填料粒子(filler particle)。填料粒子可為SiO2、Al2O3或類似材料的介電粒子,且可具有球形形狀。此外,填料粒子可具有多種不同的直徑。可以液體或半液體形式施加包封體70,且隨後對其進行固化,例如藉由壓縮模製(compression molding)、轉移模製(transfer molding)或類似製程來施加包封體70。
在圖4中,根據一些實施例,對包封體70進行薄化以暴露出半導體裝置60A及半導體裝置60B。舉例而言,薄化會移除包封體70的覆蓋半導體裝置60A及半導體裝置60B的頂表面
的部分。在一些實施例中,薄化亦會移除半導體裝置60A及/或半導體裝置60B的部分。在薄化之後,半導體裝置60A及半導體裝置60B的有效側61(例如,頂表面)可彼此共面(在製程變化內)以及與包封體70的第一側70A(例如,頂表面)共面(在製程變化內)。薄化製程可為機械磨製、化學機械研磨(CMP)、回蝕、其組合或類似製程。
在圖5中,在半導體裝置60A及半導體裝置60B的有效側61之上(例如,在晶粒連接件56之上)形成導電性連接件72。導電性連接件72可為受控塌陷晶片連接(controlled collapse chip connection,C4)凸塊、微凸塊、無電鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique,ENEPIG)形成的凸塊、金屬柱或類似組件。導電性連接件72可包括可迴流的導電材料,例如焊料,且亦可包括銅、鋁、金、鎳、銀、鈀、錫、鉛、類似材料或其組合。在一些實施例中,藉由最初透過蒸鍍、電鍍、印刷、焊料轉移、植球或類似方法形成焊料層來形成導電性連接件72。一旦已在所述結構上形成焊料層,便可實行迴焊以便將所述材料造型成所期望的凸塊形狀。
在圖6中,可將中間結構放置於載體基底74或其他適合的支撐結構上,以供後續處理。舉例而言,可藉由釋放層76將半導體裝置60A及半導體裝置60B的有效側61以及包封體70的第一側70A貼合至載體基底74。在一些實施例中,釋放層76具有較導電性連接件72大的厚度,以避免導電性連接件72觸及載
體基底74,此可防止或減少對導電性連接件72的損壞。在一些實施例中,載體基底74為呈晶圓形狀、面板形狀或類似形狀的塊狀半導體基底或玻璃基底。釋放層76可具有與釋放層66相似的材料,例如在被加熱時可能失去其黏合性質的熱釋放材料(例如LTHC釋放塗層)。
在圖7中,實行載體剝離(carrier debonding)以自半導體裝置60A及半導體裝置60B的非有效側62以及包封體70的第二側70B拆離(剝離)載體基底64(參見圖6)。剝離包括自載體基底64的頂側投射例如雷射光或紫外(ultraviolet,UV)光等光,以用於局部地加熱釋放層66。因此,釋放層66可在光的局部分佈熱量下分解,且載體基底64可被移除,而位於包封體70的第二側70B之上的釋放層76可不受影響。
在圖8中,根據一些實施例,在半導體裝置60A及半導體裝置60B的非有效側62以及包封體70的第二側70B之上提供或形成接合膜78。接合膜78可為用於提供黏合特性的黏合層或用於提供能夠形成熔融接合(fusion bond)的氧化物介面的氧化物層(例如,氧化矽)。在其中接合膜是黏合層的一些實施例中,接合膜78包含熱介面材料(thermal interface material,TIM)。TIM可為聚合材料、焊料膏、銦焊料膏或類似材料。在其中接合膜78是氧化物層的一些實施例中,氧化物層包含氧化矽、氮氧化矽、能夠形成熔融接合的其他氧化物或者其組合。在一些實施例中,藉由CVD、物理氣相沈積(physical vapor deposition,PVD)、旋轉塗佈
或類似製程來形成氧化物層。
圖9A至圖9C示出根據一些實施例在接合膜78之上提供或形成散熱結構80。圖9B及圖9C示出半導體封裝100的裝置區100D及劃片區(scribe region)100S的中間階段的俯視圖,其中圖9B示出其中散熱結構80包括呈平行定向的多個溝槽84(未示出的多孔層86)的實例,而圖9C示出其中散熱結構80包括以柵格圖案(grid pattern)佈置的多個溝槽84(未示出的多孔層86)的實例。圖9A示出沿圖9B或圖9C中所示截面X-X’的剖視圖。
散熱結構80可包括基底82及多孔層86,基底82具有多個溝槽84及柱85,多孔層86沿基底82的頂表面延伸且延伸至溝槽84中(例如,在柱85之上延伸)。在圖18至圖22B中將詳細論述散熱結構80的製造製程。
在一些實施例中,基底82由例如Cu、Al、Ni、Co、Ti、W、其合金、石墨、石墨烯、其組合或類似材料等金屬材料形成。在一些實施例中,基底82由半導體材料(例如,矽)或與針對圖1所示半導體基底52闡述的半導體材料相似的半導體材料形成。溝槽84可具有任何形狀,且可具有規則或不規則的圖案。舉例而言,圖9B示出裝置區100D中的溝槽84的示例性圖案,裝置區100D由劃片區100S環繞。溝槽84可具有條帶狀形狀(strip-like shape),且沿第一方向(例如,圖9B中的垂直方向)延伸。在一些實施例中,溝槽84可具有條帶狀形狀,且如圖9C中所示佈置成柵格圖案,其中一些溝槽84沿第一方向(例如,圖9C中的垂
直方向)延伸,而一些溝槽84沿第二方向(例如,圖9C中的水平方向)延伸。在一些實施例中,儘管圖9A中所示溝槽84僅部分地延伸穿過基底82,然而溝槽84延伸穿過基底82並暴露出接合膜78。
多孔層86形成於散熱結構80的基底82之上,例如沿基底82的頂表面及溝槽84的表面(例如,在柱85之上)延伸。以下參照圖18至圖21B提供形成多孔層86的實例性方法。多孔層86可包含Cu、Al、Ni、Co、Ti、W、Si或其組合。在一些實施例中,多孔層86由與基底82相同的材料形成。多孔層86可具有約5微米至約50微米的厚度(例如,約10微米),且在一些實施例中,多孔層86可為共形的。根據一些實施例,多孔層86具有0.1微米至5微米的平均孔徑(average pore size)。在一些實施例中,多孔層86具有2244平方毫米至22242平方毫米的表面積,其可較具有溝槽84但不具有多孔層86的基底82的表面積大2.6倍至26.2倍。
在圖10中,實行載體剝離以自導電性連接件72以及包封體70的第一側70A拆離(剝離)載體基底74(參見圖8)。在其中釋放層76包含LTHC材料的實施例中,剝離包括自載體基底74的頂側投射例如雷射光或紫外(UV)光等光,以用於加熱釋放層76。因此,釋放層76可在光的熱量下分解,且載體基底74可被移除。
接下來,參照圖11,根據一些實施例,使用導電性連接
件72將中間結構貼合至基底88。應注意,可以晶圓層級實行圖1至圖10中所論述的製程,其中包封體70是晶圓大小的。因此,可實行單體化製程以沿劃片區100S(參見圖9B或圖9C)將晶圓大小的封裝單體化成分開的封裝(例如,圖11中示出一個分開的封裝結構)。基底88可包括主動裝置及/或被動裝置(未分開示出)。可使用例如電晶體、電容器、電阻器、其組合及類似裝置等裝置來產生系統的設計的結構性要求及功能性要求。在基底88是中介層的一些實施例中,基底88可包括位於半導體基底(例如,矽)上的內連線層以及可與內連線層的金屬化圖案連接並延伸穿過中介層的半導體基底的穿孔(through via)。
單體化製程可包括鋸切(sawing)、切割(dicing)或類似製程。舉例而言,單體化製程可包括對散熱結構80、接合膜78及包封體70進行鋸切。作為單體化製程的結果,散熱結構80的外側壁及包封體70的外側壁在側向上相連(在製程變化內)。在一些實施例(未示出)中,可在貼合基底88之後實行單體化製程。舉例而言,可將晶圓大小的封裝結構貼合至基底88,且然後實行單體化製程。在此種實施例中,單體化製程包括將基底88與散熱結構80、接合膜78及包封體70一起進行鋸切。作為單體化製程的結果,散熱結構80的外側壁、接合膜78的外側壁、包封體70的外側壁及基底88的外側壁在側向上相連(在製程變化內)。
在一些實施例中,在基底88之上設置環結構(ring structure)90。環結構90可在側向上環繞包封體70。在一些實施
例中,環結構90可由金屬或金屬合金(例如,鋁、銅、鎳、鈷、其合金或其組合)或者其他材料(例如碳化矽、氮化鋁、石墨及類似材料)製成。環結構90可減少基底88的翹曲(warpage)。可使用例如黏合層(未示出)將環結構90貼合至基底88。
在一些實施例中,在包封體70與基底88之間形成環繞導電性連接件的底部填充膠92。底部填充膠92可具有線性側壁或彎曲側壁。底部填充膠92可由底部填充材料(例如環氧樹脂或類似材料)形成。可在貼合基底88之後藉由毛細流動製程(capillary flow process)來形成底部填充膠92,或者可在貼合基底88之前藉由適合的沈積方法來形成底部填充膠92。底部填充膠92可為自基底88延伸至包封體70的連續材料。可以液體或半液體形式施加底部填充膠92,且隨後對其進行固化。底部填充膠92可為導電性連接件72提供保護,並可防止產生由導電性連接件72的迴焊而導致的接頭(joint)。
在圖12中,根據一些實施例,使用導電性連接件96將基底88貼合至基底94。基底94可為PCB,或者可為與基底88相似且具有更大大小的基底。導電性連接件96可為球柵陣列(ball grid array,BGA)凸塊,或者可為與導電性連接件72相似且具有更大大小的連接件。在一些實施例中,在基底88與基底94之間形成環繞導電性連接件96的底部填充膠98。底部填充膠98可具有線性側壁或彎曲側壁。底部填充膠98可由與底部填充膠92的材料相似的材料形成,且可以與底部填充膠92的方式相同的方式
形成。
藉由將散熱結構80安裝於半導體裝置60A及半導體裝置60B的非有效側62之上,半導體封裝100可具有改善的散熱效率及能力。舉例而言,散熱結構80可提供更大的表面積,且容許冷卻氣體或冷卻流體流過,以將自半導體裝置60A及半導體裝置60B產生的熱量耗散出去。具體而言,多孔層86可增加散熱結構80的表面積。增加散熱結構80的表面積可每單位時間容許更多的冷卻氣體或冷卻流體有效地接觸散熱結構80,以使得可改善散熱結構80與冷卻氣體或冷卻流體之間的熱轉移速率。因此,半導體封裝100的散熱能力及效率增強,且半導體封裝100的效能及可靠性亦可改善。
圖13示出在散熱系統200中進行操作的半導體封裝100的示例性實施例。散熱系統200可包括罐(tank)202,罐202允許半導體封裝100及冷卻流體204設置於其中。冷卻流體204可包括水、氟碳化合物(fluorocarbon)、氯碳化合物(chlorocarbon)、其他適合的液體冷卻劑或其組合。在一些實施例中,將冷卻流體204容納於罐202中,且將半導體封裝100浸漬於冷卻流體204中。因此,冷卻流體204可流過散熱結構80(包括穿透過多孔層86的孔隙(pore)),以將熱量自由多孔層86引起的增大的表面積傳導出去。散熱結構80及散熱系統200可因此有效地耗散由半導體裝置60A及半導體裝置60B產生的熱量。在一些實施例中,散熱系統200亦包括馬達206,馬達206被配置成使冷卻流體204進
行循環並引起冷卻流體的對流(convection),此可進一步提高冷卻流體204流過多孔層86的孔隙的效率,且可因此減少或避免在散熱結構80上發生膜沸騰(film boiling)。在一些實施例中,散熱系統200亦包括用於收集冷卻流體204的蒸汽並將其轉換回液態的冷凝器(condenser)210。亦可存在電性連接部(未示出)及其他元件(例如,管路(piping)等)(未示出)。
圖14至圖17是根據一些實施例的半導體封裝300的製造中的中間階段的剖視圖。半導體封裝300可相似於半導體封裝100,其中相同的參考編號指代相同的元件。在一些實施例中,半導體封裝300是在包封體70之上形成有重佈線結構302以使半導體封裝300具有緊湊大小的封裝。
半導體封裝300的製造相似於半導體封裝100的製造。舉例而言,如圖14中所示的製造半導體封裝300的處理假定事先實行了圖2至圖4中所示處理。因此,在以上參照圖2至圖4論述的處理之後,處理可繼續進行至圖14。參照圖14,根據一些實施例,在半導體裝置60A及半導體裝置60B的有效側61以及包封體70的第一側70A之上形成重佈線結構302。在一些實施例中,重佈線結構302可包括介電層312、介電層316及介電層320;以及金屬化圖案314及金屬化圖案318。金屬化圖案亦可被稱為重佈線層(redistribution layer)或重佈線線(redistribution line)。重佈線結構302被示出為具有兩層金屬化圖案314與318的實例。然而,可形成更多或更少的介電層及金屬化圖案。
在一些實施例中,為了形成重佈線結構302,在半導體裝置60A及半導體裝置60B以及包封體70的第一側70A之上形成介電層312。可藉由旋轉塗佈、疊層、CVD、類似製程或其組合來形成介電層312。介電層312可由例如PBO、聚醯亞胺、BCB或類似材料等可使用微影罩幕(lithography mask)來圖案化的感光性材料形成。所述圖案化會形成暴露出半導體裝置60A及半導體裝置60B的導電特徵的開口。可藉由可接受的製程(例如當介電層312為感光性材料時藉由將介電層312曝光並顯影,或者藉由使用例如非等向性蝕刻來進行蝕刻)來進行所述圖案化。
然後形成金屬化圖案314。金屬化圖案314包括導電元件,所述導電元件沿介電層312的主表面延伸並延伸穿過介電層312以實體耦合至及電性耦合至半導體裝置60A及半導體裝置60B。作為形成金屬化圖案314的實例,在介電層312之上及在延伸穿過介電層312的開口中形成晶種層(未示出)。在一些實施例中,晶種層可為單層或者包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層包括鈦層及位於鈦層之上的銅層。可利用例如PVD或類似製程來形成晶種層。然後,在晶種層上形成光阻並對光阻進行圖案化。可形成光阻,且可將光阻暴露於光以進行圖案化。光阻的圖案對應於金屬化圖案314。所述圖案化會形成穿過光阻的開口以暴露出晶種層。然後,在光阻的開口中及在晶種層的被暴露出的部分上形成導電材料。可藉由鍍覆(例如電鍍或無電鍍覆)或類似製程來形成導電材料。導電材料可包括金屬,如銅、鈦、
鎢、鋁或類似金屬。導電材料與晶種層的下伏部分的組合形成金屬化圖案314。移除光阻以及晶種層上未形成導電材料的部分。可藉由例如使用氧電漿或類似材料的可接受的灰化製程(ashing process)或剝離製程(stripping process)來移除光阻。一旦光阻被移除,便例如利用可接受的蝕刻製程(例如,濕法蝕刻(wet etching)或乾法蝕刻(dry etching))來移除晶種層的被暴露出的部分。
可在介電層312及金屬化圖案314上分別以與介電層312及金屬化圖案314相似的方式形成介電層316、金屬化圖案318,且介電層316、金屬化圖案318可分別由與介電層312及金屬化圖案314相似的材料形成。在金屬化圖案318及介電層316上形成介電層320。可以與介電層312相似的方式形成介電層320,且介電層320可由與介電層312相同的材料形成。形成UBM 324以用於外部連接。UBM 324具有位於介電層320的主表面上且沿所述主表面延伸的凸塊部分,且具有延伸穿過介電層320以實體耦合至及電性耦合至金屬化圖案318的通孔部分。因此,UBM 324電性耦合至半導體裝置60。UBM 324可包含與金屬化圖案314相同的材料。
在重佈線結構302的UBM 324上形成導電性連接件330。導電性連接件330可為球柵陣列(BGA)連接件、焊料球、金屬柱、受控塌陷晶片連接(C4)凸塊、微凸塊、無電鍍鎳鈀浸金技術(ENEPIG)形成的凸塊或類似元件。導電性連接件330可包含導電材料,例如焊料、銅、鋁、金、鎳、銀、鈀、錫、鉛、類似材料
或其組合。在一些實施例中,導電性連接件330包含與導電性連接件72或導電性連接件96的材料相同的材料,且是以與導電性連接件72或導電性連接件96相似的方式形成。
在形成重佈線結構302及導電性連接件330之後,實行與圖8至圖11中所示處理相似的處理。舉例而言,在圖15中,利用如參照圖8所述的製程及/或材料,藉由釋放層76來將載體基底74貼合至重佈線結構302及導電性連接件330,且在半導體裝置60A及半導體裝置60B的非有效側62以及包封體70的第二側70B之上形成接合膜78。在圖16中,利用如參照圖9所述的製程及/或材料,將散熱結構80貼合至接合膜78或形成於接合膜78之上。在一些實施例中,省略基底88,且在拆離載體基底之後將導電性連接件330直接貼合至基底94。然後,在重佈線結構302與基底94之間形成環繞導電性連接件330的底部填充膠98。圖17中示出示例性的所得結構。可以晶圓層級形成重佈線結構302。因此,在如圖11中所示的單體化製程之後,如圖17中所示的半導體封裝300是經單體化的半導體封裝中的一者。作為單體化製程的結果,重佈線結構302的外側壁與包封體70的外側壁在側向上相連(在製程變化內)。在一些實施例中,散熱結構80為半導體封裝300提供改善的散熱效率及能力。半導體封裝300能夠在散熱系統200中進行操作。
圖18、圖19、圖20A、圖21A及圖22A示出根據一些實施例的製造散熱結構80的製程中的中間階段的剖視圖,其中圖
20B、圖21B及圖22B分別示出圖20A、圖21A及圖22A中的聚合物層或多孔層86的放大圖。圖18至圖22B中所示製造製程示出在中間結構(例如,半導體封裝100、半導體封裝300或類似結構)之上形成散熱結構80;然而,可獨立於半導體封裝100來製造散熱結構80並將其貼合至半導體封裝100。
在圖18中,根據一些實施例,如圖7中所示,將處於塊狀狀態(bulk state)的基底82貼合至半導體封裝100的中間結構的接合膜78。半導體封裝100用於例示性目的,且可替代其他組件,例如半導體封裝300。在圖19中,溝槽84相對於基底82的頂表面凹陷。可藉由銑切製程(milling process)、蝕刻製程、雷射技術、其組合或類似技術來形成溝槽84。在一些實施例中,參照圖19,溝槽84中的每一者可具有範圍介於2微米至3000微米的寬度W及範圍介於1微米至1000微米的深度D。相鄰的溝槽84可具有範圍介於20微米至5000微米的節距(pitch)P。
參照圖20A,在基底82的頂表面之上及溝槽84的表面之上形成聚合物層485。舉例而言,可藉由浸塗製程(dip coating process)、溶膠-凝膠浸塗製程(sol-gel dip coating process)或其他適合的塗佈或沈積製程來形成聚合物層485。舉例而言,可藉由溶劑來承載微粒子或奈米粒子(統稱為微粒子485A)(例如微球或呈其他形狀的粒子),或者可藉由溶劑中的溶膠-凝膠製程來形成微粒子或奈米粒子(統稱為微粒子485A)。然後可將基底82及柱85浸入至具有微粒子485A的溶劑中並將其移除。當被移除時,微粒
子485A保留於基底82及柱85上。在乾燥製程期間,移除基底82及柱85上的剩餘溶劑,藉此留下如圖20A及圖20B中所示的微粒子485A,其中微粒子485A統稱為聚合物層485。在一些實施例中,微粒子485A具有約0.1微米至約5微米的平均粒徑。
在一些實施例中,聚合物層485與基底82的柱85共形。參照圖20B,聚合物層485可具有由微粒子485A聚集而成的鬆散結構(loose structure)。因此,聚合物層485可包括微粒子485A中的相鄰者之間的空間或通道,且可用作用於隨後形成多孔層(參見例如圖22A及圖22B的多孔層86)的模板(template)。在一些實施例中,聚合物層485包含聚苯乙烯、聚乙烯、聚乙二醇、聚丙烯酸酯、聚氧化烯(polyoxyalkylene)、聚胺基甲酸酯、聚丙烯醯胺、或包括其聚合物的共聚物、或者其組合、或者類似材料。在一些實施例中,可對聚合物層485進行燒結。所述燒結可使聚合物層485的微粒子485A部分地熔化,以使得可擴大多孔層86中的孔隙之間的通道。舉例而言,可在80度至200度下將聚合物層485燒結0.1小時至10小時。
參照圖21A及圖21B,在聚合物層485之上形成層486。可在微粒子485A的表面之上形成層486,從而填充或部分地填充微粒子485A中的相鄰者之間的空間或通道。可藉由電鍍、無電鍍覆、CVD或類似製程來形成層486。在其中使用電鍍的一些實施例中,可首先藉由原子層沈積(atomic layer deposition,ALD)或PVD來沈積晶種層,且在晶種層之上形成經鍍覆金屬材料。在一
些實施例中,晶種層可為單層或者包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層包括鈦層及位於鈦層之上的銅層。在此種實施例中,經鍍覆金屬材料(例如,銅)與下伏的晶種層的組合形成多孔層86的材料。
接下來,參照圖22A及圖22B,根據一些實施例,移除聚合物層485,從而在溝槽84及柱85的表面之上留下多孔層86。可藉由退火、氧電漿或有機溶劑來移除聚合物層485。在一些實施例中,有機溶劑是可選擇性地溶解聚合物層485的有機溶劑,例如甲醇、乙醇、丙醇、異丙醇、異丁醇、二乙酯、甲基乙基醚、乙酸乙酯、己烷、環己烷、氯仿、丙酮、苯、甲苯、其組合或類似材料。因此,可利用有機溶劑將聚合物層485萃取掉,從而留下多孔層86。
圖23至圖25示出根據一些實施例的半導體封裝500的製造中的中間階段的剖視圖。半導體封裝500可相似於半導體封裝100,且具有散熱結構580,其中相同的參考編號指代相同的元件。半導體封裝500的製造相似於半導體封裝100的製造。舉例而言,如圖23中所示製造半導體封裝500的處理假定事先實行了圖2至圖7中所示處理。因此,在以上參照圖2至圖7論述的處理之後,處理可繼續進行至圖23。
參照圖23,根據一些實施例,在半導體裝置60A及半導體裝置60B的有效側61以及包封體70的第一側70A之上形成經圖案化罩幕502。若在後續製程中使用電鍍製程,則可在經圖案
化罩幕502之前可選地形成晶種層504,且可在晶種層504之上形成經圖案化罩幕502。晶種層504可為單層或者包括由不同材料形成的多個子層(例如鈦層及位於鈦層之上的銅層)的複合層。經圖案化罩幕502可包括與隨後形成的柱的形狀對應的開口506。在一些實施例中,經圖案化罩幕502包含光阻材料。可藉由微影製程來對光阻材料進行圖案化。在一些實施例中,經圖案化罩幕502可包括與圖9B及圖9C中所示溝槽84的圖案相似的圖案。
在圖24中,根據一些實施例,在經圖案化罩幕502的開口506(參見圖23)中形成多個柱585。在一些實施例中,柱585包含與基底82的材料相似的材料。可藉由電鍍、無電鍍覆、CVD、PVD或其組合來形成柱585。在其中藉由電鍍來形成柱585的一些實施例中,在晶種層504的被暴露出的部分之上沈積經鍍覆金屬材料(例如,銅)。晶種層504以及位於晶種層504之上的經鍍覆金屬材料可形成柱585。在其中藉由如CVD或PVD等沈積製程來形成導電柱的一些實施例中,可省略晶種層504。在形成柱585之後,可移除經圖案化罩幕502以及晶種層504(若存在)的被暴露出的部分,從而留下在柱585之間形成的溝槽584。溝槽584可延伸穿過柱585(包括晶種層504(若存在)),且可暴露出半導體裝置60A及半導體裝置60B的非有效側62以及包封體70的第一側70A。可藉由乾法蝕刻或濕法蝕刻來移除經圖案化罩幕502以及晶種層504(若存在)的被暴露出的部分。
接下來,在圖25中,沿柱585及溝槽584的表面形成
多孔層586,藉此形成散熱結構580。多孔層586可與半導體裝置60A及半導體裝置60B的非有效側62以及包封體70的第一側70A接觸。多孔層586可包含與多孔層86的材料相似的材料,且可以相似的方式形成。接下來,半導體封裝500的製造可繼續進行:實行與圖10至圖12中針對半導體封裝100示出的製程相似的製程,且半導體封裝500的所得結構示出於圖26中。在一些實施例中,製造散熱結構580的製程可整合至製造半導體封裝300的製程中,且半導體封裝600的所得結構示出於圖27中。
根據一些實施例,提供一種具有改善的散熱效率及能力的半導體封裝。在一些實施例中,所述封裝包括設置於半導體裝置之上的散熱結構及圍繞半導體裝置的包封體。散熱結構包括多個溝槽及沿所述溝槽延伸的多孔層,以使得散熱結構可提供容許冷卻流體接觸的增加的表面積。因此,所述半導體封裝的散熱效率及能力得到改善,且所述半導體封裝的效能亦得到改善。在一些實施例中,亦提供容許所述半導體封裝在其中進行操作的散熱系統。所述半導體封裝亦可被設計成在液體中進行操作,例如浸漬於所述散熱系統中所容納的冷卻流體中並在其中進行操作。
在實施例中,一種封裝包括:半導體裝置;包封體,在側向上環繞半導體裝置;以及散熱結構,設置於半導體裝置及包封體之上,其中散熱結構包括多個柱及在所述多個柱的側壁之上延伸的多孔層。在實施例中,多孔層包含Cu、Al、Ni、Co、Ti、W、Si或其組合。在實施例中,所述多個柱包含Cu、Al、Ni、Co、Ti、
W、Si、石墨、石墨烯或其組合。在實施例中,多孔層與所述多個柱為相同的材料。在實施例中,多孔層包括0.1微米至5微米的孔徑。在實施例中,所述封裝更包括接合膜,所述接合膜設置於半導體裝置與散熱結構之間以及包封體與散熱結構之間。在實施例中,接合膜是氧化物層,且在平面圖中與包封體交疊。在實施例中,半導體裝置與多孔層實體地接觸。在實施例中,所述多個柱藉由接合膜而貼合至半導體裝置及包封體,其中接合膜包括氧化物層。在實施例中,所述多個柱包括與半導體裝置實體地接觸的晶種層。
在實施例中,一種封裝包括:半導體裝置,包括第一表面;包封體,相鄰於半導體裝置而設置,包封體包括與半導體裝置的第一表面共面的第二表面;以及散熱結構,貼合至半導體裝置的第一表面及包封體的第二表面,其中散熱結構包括多個柱及在所述柱之上延伸的多孔層。在實施例中,所述封裝更包括重佈線結構,所述重佈線結構設置於半導體裝置的與半導體裝置的第一表面相對的第三表面之上,其中重佈線結構在包封體的與包封體的第二表面相對的第四表面之上延伸,其中重佈線結構包括與半導體裝置實體地接觸的介電層。在實施例中,散熱結構的側壁與重佈線結構的側壁在側向上相連。在實施例中,多孔層與半導體裝置的第一表面及包封體的第二表面實體地接觸。在實施例中,多孔層與所述柱由相同的材料形成。
在實施例中,一種形成封裝的方法包括:形成在側向上環繞半導體裝置的包封體;以及在半導體裝置及包封體之上設置
散熱結構,其中散熱結構包括多個柱、多個溝槽及沿所述柱的側壁及頂表面延伸的多孔層。在實施例中,所述方法更包括在設置散熱結構之後對包封體及散熱結構進行單體化。在實施例中,設置散熱結構包括:在半導體裝置及包封體之上形成接合膜;將基底貼合至接合膜;在將基底貼合至接合膜之後,在基底中形成所述多個溝槽,藉此在所述多個溝槽中的相鄰溝槽之間形成所述多個柱;以及在所述柱的側壁及頂表面之上形成多孔層。在實施例中,設置散熱結構包括:形成散熱結構;以及在形成散熱結構之後,將散熱結構貼合至半導體裝置及包封體。在實施例中,設置散熱結構包括:在半導體裝置及包封體之上形成晶種層;在晶種層之上形成罩幕層,其中罩幕層包括暴露出晶種層的部分的多個開口;在晶種層的被暴露出的部分之上形成導電材料,其中導電材料及晶種層形成所述多個柱;移除罩幕層以及晶種層的未由導電材料覆蓋的部分;以及形成多孔層。
以上概述了若干實施例的特徵,以使熟習此項技術者可更佳地理解本揭露的各態樣。熟習此項技術者應理解,他們可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到,此種等效構造並不背離本揭露的精神及範圍,而且他們可在不背離本揭露的精神及範圍的條件下對其作出各種改變、代替及變更。
60A、60B:半導體裝置
61:有效側
62:非有效側
70:包封體
70A:第一側
70B:第二側
72、96:導電性連接件
78:接合膜
80:散熱結構
82、88、94:基底
84:溝槽
85:柱
86:多孔層
90:環結構
92、98:底部填充膠
100:半導體封裝
Claims (10)
- 一種封裝,包括:半導體裝置;包封體,在側向上環繞所述半導體裝置;以及散熱結構,設置於所述半導體裝置及所述包封體之上,其中所述散熱結構包括多個柱及在所述多個柱的側壁之上延伸的多孔層。
- 如請求項1所述的封裝,其中所述多孔層包括0.1微米至5微米的孔徑。
- 如請求項1所述的封裝,更包括接合膜,所述接合膜設置於所述半導體裝置與所述散熱結構之間以及所述包封體與所述散熱結構之間。
- 如請求項1所述的封裝,其中所述多個柱藉由接合膜而貼合至所述半導體裝置及所述包封體,其中所述接合膜包括氧化物層。
- 如請求項1所述的封裝,其中所述多個柱包括與所述半導體裝置實體地接觸的晶種層。
- 一種封裝,包括:半導體裝置,包括第一表面;包封體,相鄰於所述半導體裝置而設置,所述包封體包括與所述半導體裝置的所述第一表面共面的第二表面;以及散熱結構,貼合至所述半導體裝置的所述第一表面及所述包 封體的所述第二表面,其中所述散熱結構包括多個柱及在所述多個柱之上延伸的多孔層。
- 如請求項6所述的封裝,更包括重佈線結構,所述重佈線結構設置於所述半導體裝置的與所述半導體裝置的所述第一表面相對的第三表面之上,其中所述重佈線結構在所述包封體的與所述包封體的所述第二表面相對的第四表面之上延伸,其中所述重佈線結構包括與所述半導體裝置實體地接觸的介電層。
- 一種形成封裝的方法,所述方法包括:形成在側向上環繞半導體裝置的包封體;以及在所述半導體裝置及所述包封體之上設置散熱結構,其中所述散熱結構包括多個柱、多個溝槽及沿所述多個柱的側壁及頂表面延伸的多孔層。
- 如請求項8所述的方法,其中設置所述散熱結構包括:在所述半導體裝置及所述包封體之上形成接合膜;將基底貼合至所述接合膜;在將所述基底貼合至所述接合膜之後,在所述基底中形成所述多個溝槽,藉此在所述多個溝槽中的相鄰溝槽之間形成所述多個柱;以及在所述多個柱的所述側壁及所述頂表面之上形成所述多孔層。
- 如請求項8所述的方法,其中設置所述散熱結構包括: 在所述半導體裝置及所述包封體之上形成晶種層;在所述晶種層之上形成罩幕層,其中所述罩幕層包括暴露出所述晶種層的部分的多個開口;在所述晶種層的被暴露出的所述部分之上形成導電材料,其中所述導電材料及所述晶種層形成所述多個柱;移除所述罩幕層以及所述晶種層的未由所述導電材料覆蓋的部分;以及形成所述多孔層。
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