US20210257335A1 - Semiconductor package and method of manufacturing the same - Google Patents

Semiconductor package and method of manufacturing the same Download PDF

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Publication number
US20210257335A1
US20210257335A1 US16/795,006 US202016795006A US2021257335A1 US 20210257335 A1 US20210257335 A1 US 20210257335A1 US 202016795006 A US202016795006 A US 202016795006A US 2021257335 A1 US2021257335 A1 US 2021257335A1
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Prior art keywords
dies
layer
segment
die
redistribution layer
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US16/795,006
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English (en)
Inventor
Shing-Yih Shih
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Nanya Technology Corp
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Nanya Technology Corp
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Priority to US16/795,006 priority Critical patent/US20210257335A1/en
Assigned to NANYA TECHNOLOGY CORPORATION reassignment NANYA TECHNOLOGY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SHIH, SHING-YIH
Priority to TW110100999A priority patent/TWI763246B/zh
Priority to CN202110108867.9A priority patent/CN113284884B/zh
Publication of US20210257335A1 publication Critical patent/US20210257335A1/en
Priority to US17/520,526 priority patent/US11605612B2/en
Abandoned legal-status Critical Current

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Definitions

  • the semiconductor package includes a first die, a second die, a plurality of conductive plugs and a redistribution layer.
  • the redistribution layer includes a first segment and a second segment electrically isolated from the first segment. The first segment of the redistribution layer electrically connects the first die to the second die, and the second segment of the redistribution layer electrically connects the first die to the conductive plugs.
  • the first segment of the redistribution layer is surrounded by the second segment of the redistribution layer.
  • the second dies are arranged horizontally to parallel the conductive plugs.
  • the semiconductor package further includes a passivation layer, a conductive layer and a plurality of solder bumps; the passivation layer covers the second die and the conductive plugs, and the conductive layer penetrates through the passivation layer and includes a first portion connected to the second die and a s second portion connected to the conductive plugs.
  • the plurality of solder bumps are mounted on the conductive layer.
  • Another aspect of the present disclosure provides a method of manufacturing a semiconductor package assembly.
  • the method includes steps of providing a plurality of first dies arranged horizontally; forming a redistribution layer on the first dies and the first insulative material, wherein the redistribution layer is divided into a first segment and a second segment electrically isolated from the first segment; mounting a plurality of second dies on the first segment of the redistribution layer; depositing a second insulative layer on the second dies and the redistribution layer; and forming a plurality of conductive plugs penetrating through the second insulative material and contacting the second segment of the redistribution layer.
  • the method further includes a step of forming at least one dielectric layer to encase the redistribution layer.
  • the method further includes steps of depositing a passivation layer on the second dies, the conductive plugs and the second insulating layers; forming a conductive layer penetrating through the passivation layer, wherein the conductive layer comprises a first portion electrically coupled to the second dies and a second portion electrically isolated from the first portion and contacting the conductive plugs; and forming a plurality of solder bumps connected to the conductive layer.
  • the method further includes a step of performing a grinding process to expose conductive lines of the second dies before the deposition of the passivation layer.
  • a melting point of the first insulative material is greater than that of the second insulative material.
  • the first dies and the second dies are symmetric with respect to a central axis of the semiconductor package.
  • the method further includes a step of molding the first dies with a first insulative material before the formation of the redistribution layer.
  • FIG. 1 is a cross-sectional view of a semiconductor package in accordance with some embodiments of the present disclosure.
  • FIG. 2 is a flow diagram illustrating a method of manufacturing a semiconductor package in accordance with some embodiments of the present disclosure.
  • FIGS. 3 through 14 illustrate cross-sectional views of intermediate stages in the formation of a semiconductor package in accordance with some embodiments of the present disclosure.
  • first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are merely used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.
  • FIG. 1 is a cross-sectional view of a semiconductor package 10 in accordance with some embodiments of the present disclosure.
  • the semiconductor package 10 can be a wafer-level semiconductor package and includes one or more first dies 110 , one or more second dies 120 , a plurality of conductive plugs 130 and a redistribution layer 140 including a first segment 142 and at least one second segment 144 electrically isolated from the first segment 142 , wherein the first segment 142 electrically connects the first dies 110 to the second dies 120 , and the second segment 144 electrically connects the first dies 110 to the conductive plugs 130 .
  • the first dies 110 arranged horizontally can be stacked on the second dies 120 and the conductive plugs 130 , the first segment 142 of the redistribution layer 140 is disposed between the first dies 110 and the second dies 120 , and the second segment 144 of the redistribution layer 140 is disposed between the first dies 110 and the conductive plugs 130 to reduce a footprint of the semiconductor package 10 .
  • the first die 110 is a system-on-chip (SoC) that includes a central processing unit (CPU), a graphics processing unit (GPU), a dynamic random access memory (DRAM) controller, or any combination thereof
  • SoC system-on-chip
  • the second dies 120 arranged horizontally can be memory dies, such as dynamic random access memory (DRAM) dies.
  • the first dies 110 have a first footprint, and the second dies 120 have a second footprint smaller than the first footprint; therefore, the conductive plugs 130 can arranged horizontally parallel to the second dies 120 .
  • the conductive plugs 130 surrounding the second dies 120 are arranged in an equally-spaced configuration.
  • the first dies 110 have a first distance D 1 therebetween, and the second dies 120 have a second distance D 2 therebetween; the first distance D 1 is greater than the second distance D 2 to facilitate heat dissipation.
  • the semiconductor package 10 can further includes a first insulative layer 150 surrounding the first dies 110 and a second insulative layer 160 surrounding the second dies 120 and the conductive plugs 130 .
  • the conductive plugs 130 penetrating through the second insulative layer 160 and contacting the second segment 144 of the redistribution layer 140 can have a height s equal to or greater than that of the second dies 120 .
  • the semiconductor package 10 further includes a passivation layer 170 , a conductive layer 180 and a plurality of solder bumps 190 electrically coupled to the conductive layer 180 .
  • the passivation layer 170 covers sides of the second dies 120 and the conductive plugs 130 opposite to where the redistribution layer 140 is disposed.
  • the conductive layer 180 penetrates through the passivation layer 170 and includes a first portion 182 physically connected to conductive lines (such as through silicon vias) 124 of the second dies 120 and a second portion 184 physically connected to the conductive plugs 130 .
  • FIG. 2 is a flow diagram illustrating a method 30 of manufacturing a semiconductor package in accordance with some embodiments of the present disclosure
  • FIGS. 3 through 14 illustrate cross-sectional views of intermediate stages in the formation of a semiconductor package in accordance with some embodiments of the present disclosure.
  • the stages shown in FIGS. 3 to 14 are also illustrated schematically in the flow diagram in FIG. 2 .
  • the fabrication stages shown in FIGS. 3 to 14 are discussed in reference to the process steps shown in FIG. 2 .
  • first dies 110 molded with a first insulative layer 150 are provided according to a step 302 in FIG. 2 .
  • the first dies 110 encased by the first insulative layer 150 are arranged horizontally.
  • the first die 110 has a front surface 1102 and a back surface 1104 opposite to the front surface 1102 , which are exposed through the first insulative material 150 .
  • the first die 110 can include a plurality of conductive pads 112 connected s to the back surface 1104 .
  • the first insulative material 150 has a top surface 152 coplanar with the front surfaces 1102 of the first dies 110 and a bottom surface 154 coplanar with the back surfaces 1104 of the first dies 110 .
  • the formation of the first dies 110 molded with the first insulating layer 150 includes (1) adhering the first dies 110 on a temporary carrier by an adhesive layer, (2) applying a first insulating material to surround the first dies 110 , and (3) removing the adhesive layer and the temporary carrier.
  • the temporary carrier may include silicon, ceramics, metal, or the like, and the adhesive layer is a temporary and any strippable or easily removed material may be used, for example, films, tapes, liquid adhesives.
  • the first insulating layer 150 may be formed using thermoset molding compounds in a transfer mold press, for example.
  • a redistribution layer 140 is at least formed to connect to the contact pads 112 of the first dies 110 according to a step 304 in FIG. 2 .
  • the redistribution layer 140 can include a plurality of metal layers and a plurality of vias stacked one above the other.
  • the redistribution layer 140 includes a first segment 142 and at least one second segment 144 electrically isolated from the first segment 142 .
  • the first segment 142 of the redistribution layer 140 can be surrounded by the second segment 144 of the redistribution layer 140 .
  • the second segment 144 of the redistribution layer 140 is disposed at a periphery of the first segment 142 .
  • the redistribution layer 140 may include aluminum, copper, tungsten, titanium, titanium nitride, or the like.
  • At least one dielectric layer 146 can be formed to encase the redistribution layer 140 to reduce corrosion of the redistribution layer 140 .
  • the dielectric layer 146 can further cover the back surfaces 1104 of the first dies 110 and the bottom surface 154 of the first insulative layer 150 .
  • a portion of the redistribution layer 140 away from the first dies 110 is exposed through the dielectric layer 146 .
  • the deposition temperature of the dielectric layer 146 is less than the melting point of the first insulative layer 150 to prevent the first insulative layer 150 from breaking.
  • the dielectric layer 146 may include organic material such as polyimide (PI) or inorganic materials such as silicon nitride or silicon oxide.
  • one or more second dies 120 are provided and mounted on the first segment 142 of the redistribution layer 140 according to a step 306 in FIG. 2 . Accordingly, the first segment 142 of the redistribution layer 140 between the first dies 110 and the second dies 120 serves as an electrical interconnection to the first dies 110 and the second dies 120 .
  • the second dies 120 can be electrically connected to the redistribution layer 140 through one or more contact pads 122 formed on the second dies 120 .
  • the first dies 110 and the second dies 120 are symmetric with respect to a central axis C.
  • a second insulative layer 160 is applied to encase the second dies 120 according to a step 308 in FIG. 2 .
  • the second insulative layer 160 may further cover the redistribution layer 140 and the dielectric layer 146 .
  • the first insulative material 150 and the second insulative material 160 may have different compositions so that the second insulative layer 160 can be cured at relatively lower temperature.
  • a grinding process is performed to polish away portions of the second dies 120 and the second insulative layer 160 according to a step 310 in FIG. 2 . Accordingly, conductive lines 124 of the second dies 120 are exposed.
  • the grinding process includes a chemical mechanical polishing (CMP) process and/or wet etching process.
  • CMP chemical mechanical polishing
  • a plurality of conductive plugs 130 are formed to penetrate the second insulative layer 160 and contact the second segment 144 of the redistribution layer 140 according to a step 312 in FIG. 2 .
  • the conductive plugs 130 are formed by providing a mask layer 210 on the second insulative layer 160 (as shown in FIG. 8 ), performing an etching process to remove portions of the second insulative layer 160 that are not covered by the mask layer 210 to form a plurality of openings 220 (as shown in FIG. 9 ), and depositing a conductive material in the openings 220 (as shown in FIG. 10 ).
  • the second dies 120 are covered by the mask layer 210 .
  • the mask layer 210 is removed, for example, by an ashing process or a wet strip process.
  • the conductive material may include copper, aluminum, tungsten or the like and is deposited in the openings 220 and over the second insulative layer 160 by using an electroplating process or a CVD process.
  • a planarizing process can be performed to expose the second insulative layer 160 after the deposition of the conductive material.
  • the planarizing process includes a CMP process and/or a wet etching process.
  • a passivation layer 170 is deposited to cover the second dies 120 , the conductive plugs 130 and the second insulative material 160 according to a step 314 in FIG. 2 .
  • the passivation layer 170 is typically deposited with a low-pressure CVD process or a plasma-enhanced CVD process.
  • a plurality of openings 230 can be formed in the passivation layer 170 to expose respective conductive lines 124 of the second dies 120 and the conductive plugs 130 .
  • the formation of the openings 230 includes (1) forming a photoresist pattern (not shown) on the passivation layer 170 , wherein the photoresist pattern defines a pattern to be etched into the passivation layer 170 , (2) performing a third etching process, using the photoresist pattern as a mask, to etch the passivation layer 170 and thereby form the openings 230 in the passivation layer 170 , (3) removing the photoresist pattern.
  • one or more conductive materials are deposited over the passivation layer 170 and in the openings 230 to from a conductive layer 180 according to a step 316 in FIG. 2 .
  • the conductive layer 180 can be divided into a first portion 182 physically connected to the conductive lines 124 and a second portion 184 physically connected to the conductive plugs 130 .
  • solder bumps 190 are disposed on the conductive layer 180 according to a step 318 in FIG. 2 .
  • the solder bumps 190 are mounted by initially placing a solder flux (not shown) on the conductive layer 180 , then disposing the solder bumps 190 on the solder flux, and once the solder bumps 190 are in contact with the solder flux, a reflow may be performed to reflow the material of the solder bumps 190 and the solder flux to physically bond the solder bumps 190 to the conductive layer 180 .
  • the first portion 182 of the conductive layer 180 serves as an electrical interconnection to the second dies 120 and the solder bumps 190
  • the second portion 184 of the conductive layer 180 serves as an electrical interconnection to the conductive plug 130 and the solder bump 190 .
  • the first dies 110 are stacked on the second dies 120 and the conductive plugs 130 , and the first dies 110 are arranged horizontally to reduce the footprint of the semiconductor package 10 .
  • the semiconductor package comprises at least one first die, at least one second die, a plurality of conductive plugs and a redistribution layer.
  • the redistribution layer comprises a first segment and a second segment electrically isolated from the first segment. The first segment of the redistribution layer electrically connects the first die to the second die, and the second segment of the redistribution layer electrically connects the first die to the conductive plugs.
  • One aspect of the present disclosure provides a method of manufacturing a semiconductor package assembly.
  • the method comprises steps of providing a plurality of first dies arranged horizontally; forming a redistribution layer on the first dies and the first insulative material, wherein the redistribution layer is divided into a first segment and a second segment electrically isolated from the first segment; mounting a plurality of second dies on the first segment of the redistribution layer; depositing a second insulative layer on the second dies and the redistribution layer; and forming a plurality of conductive plugs penetrating through the second insulative material and contacting the second segment of the redistribution layer.

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CN113284884B (zh) 2024-03-29
US11605612B2 (en) 2023-03-14

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