CN102047418B - 具有带凹槽的环状通孔的裸片堆叠 - Google Patents

具有带凹槽的环状通孔的裸片堆叠 Download PDF

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CN102047418B
CN102047418B CN2009801191893A CN200980119189A CN102047418B CN 102047418 B CN102047418 B CN 102047418B CN 2009801191893 A CN2009801191893 A CN 2009801191893A CN 200980119189 A CN200980119189 A CN 200980119189A CN 102047418 B CN102047418 B CN 102047418B
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substrate
nude film
conductive
annular via
trough
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CN102047418A (zh
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戴维·普拉特
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Micron Technology Inc
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Micron Technology Inc
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Abstract

包括裸片的裸片堆叠和形成所述裸片堆叠的方法提供用于在多种电子系统中使用的结构，其中所述裸片具有带凹导电槽的环状通孔。在一实施例中，裸片堆叠包括在裸片的顶部上的导电柱，所述导电柱被插入到另一裸片的所述凹导电槽中。

Description

具有带凹槽的环状通孔的裸片堆叠
相关申请案
本专利申请案主张2008年4月22日申请的第12/107,576号美国申请案，所述申请案以引用的方式并入本文中。
技术领域
实例实施例大体上涉及电子装置和系统的集成电路制造的技术领域。
背景技术
随着微电子学中的焦点正逐渐改变以包括对封装的更多强调，可通过使用系统级封装(SiP)方法而在封装中获得附加价值。对于功能整合中的发展趋势来说，SiP方法可被认为是主要可行的解决方案。SiP方法包括将若干裸片放置到一个封装中，所述裸片被并排放置或放置于彼此顶部上。然而，小型化趋势可或多或少地减小对并排的裸片的使用。因此，额外方法可增强所述趋势以最小化裸片面积，同时提供高速和可靠的接口。
附图说明
在附图的诸图中以实例而未限制的方式说明了一些实施例。
图1是横截面图，其说明裸片堆叠的一部分的一实例实施例，所述裸片通过使用具有凹导电槽的环状通孔和导电柱而连接；
图2是横截面图，其说明底部裸片的一部分的一实例实施例，所述底部裸片包括具有凹导电槽的环状通孔；
图3是横截面图，其说明中间裸片的一部分的一实例实施例，所述中间裸片包括具有凹导电槽的环状通孔和导电柱；
图4是横截面图，其说明在形成环状开口之后的处理中的裸片的一实例实施例；
图5是图4的处理中的裸片的俯视图；
图6是在将钝化层形成于环状开口的侧壁上之后的图4的处理中的裸片的横截面图；
图7是在形成导电通孔和平面末端部分之后的图6的处理中的裸片的横截面图；
图8是在形成凹导电槽之后的图7的处理中的裸片的横截面图；
图9是在将圆柱形导电柱形成于通孔的平面末端部分上之后的图8的处理中的裸片的横截面图；
图10是高级流程图，其说明在一实例实施例中用于形成具有凹导电槽的环状通孔的方法；
图11是高级流程图，其说明在一实例实施例中用于使用具有凹导电槽的环状通孔和导电柱来堆叠裸片的方法；
图12是流程图，其说明在一实例实施例中用于形成具有凹导电槽的环状通孔的方法；以及
图13是横截面图，其说明形成裸片的一部分的结构的一实例实施例，所述裸片包括具有凹导电槽和圆柱形柱的通孔；以及
图14是框图，其说明包括通过图11的方法而形成的电子封装的系统的一实例实施例。
具体实施方式
将描述用于借助于具有凹导电槽的环状通孔和所形成的导电柱来进行裸片堆叠的实例结构和方法的实施例。在以下描述中，出于解释的目的而陈述了大量具有实例专有细节的实例以提供对实例实施例的透彻理解。然而，所属领域的技术人员将明白，可在无这些实例专有细节的情况下实践本实例。
实例实施例可包括将导电环状TSV(在此项技术中，TSV是穿硅通孔的首字母缩写，下文中将用其来表示穿衬底通孔)形成于衬底的底表面上，所述导电环状TSV经配置以具有由环状通孔的内壁包围的凹部分。所述方法可包括形成导电层以覆盖环状通孔的凹部分并使所述凹部分排齐以形成凹导电槽。所述方法可进一步包括形成延伸出环状通孔的平面末端部分的导电圆柱形柱(例如，在位于邻近堆叠裸片的前侧上的结合垫结构的顶部上)。
图1是横截面图，其说明裸片堆叠100的一部分的一实例实施例，所述裸片通过使用具有凹导电槽的环状通孔和导电柱而连接。堆叠100可包括：底部裸片110，其包括导电凹槽115；一个或一个以上中间裸片120，其包括导电凹槽115以及导电柱125；以及顶部裸片130，其包括形成于结合垫135上的导电柱125。导电柱125和导电凹槽115可经配置以大小匹配且能够配合在一起而在邻近裸片之间(例如，底部裸片110与中间裸片120之间、中间裸片120彼此之间或中间裸片120与顶部裸片130之间)形成稳定的导电耦合。在一实例实施例中，堆叠可由底部裸片110与顶部裸片130组成。
在一些实例实施例中，裸片110、120或130可包括半导体晶片。所述半导体晶片可包括(但不限于)硅。所述裸片还可包括电子装置(例如，DRAM、SDRAM、PCRAM、快闪存储器、成像器等)。导电柱可由铜制成且导电凹槽可由凸块下材料(UBM)(例如，镍/钯/金合金)制成。还可将其它导电材料用于制造导电柱或导电凹槽。
本申请案中所呈现的裸片堆叠方法提供优于现有技术的若干优势。举例来说，导电凹槽115和导电柱125可提供互锁特征，当从裸片堆叠工艺将堆叠裸片移到后续工艺(例如，回焊、下部填充等)时，所述互锁特征可提高对准稳定性。所述方法的另一优势可包括实现由凹槽115和导电柱125可能完成的接近零结合线裸片堆叠。
图2是横截面图，其说明底部裸片的一部分200的一实例实施例，所述底部裸片包括具有凹导电槽210的环状通孔。部分200可为图1的底部裸片110的一部分。部分200可包括：衬底206(例如，硅晶片)；导电环状TSV 230；以及凹导电(例如，UBM)层210，其形成UBM槽。在实例实施例中，部分200还可包括背侧钝化部204和结合垫208。UBM槽可通过环状通孔的内壁而形成于衬底206的底表面上。环状TSV 230可包括平面末端部分235。环状TSV 230和平面末端部分235可包括铜。衬底的顶表面可为底部裸片110的有效表面(包括集成的电子装置)。
图3是横截面图，其说明中间裸片的一部分300的一实例实施例，所述中间裸片包括具有凹导电槽210的环状通孔和导电柱310。部分300可为图1的中间裸片120的一部分。部分300可包括衬底206、导电环状TSV 230、UBM槽、背侧钝化部204和结合垫208。另外，部分300可包括形成于平面末端部分235上的导电(例如，铜)圆柱形柱310(下文中还称作导电柱)。在实例实施例中，导电柱310可相对于衬底的平面而为垂直的。导电柱310可大小经设计以配合到UBM槽中，因此当通过将导电柱定位于UBM槽中来堆叠时实现底部裸片110与中间裸片120之间的导电耦合。在一实例实施例中，导电柱310可与凹导电槽210对准。
图4是横截面图，其说明在形成环状开口420之后的处理中的裸片400的一实例实施例。在实例实施例中，可通过从衬底的环形区域移除(例如，使用干蚀刻、湿蚀刻等的蚀刻)衬底材料(例如，硅)来形成环状开口420。可使用涂布于衬底410的顶表面(包括结合垫层440)上的光致抗蚀剂层430来图案化环形区域(见图5中的环形区域520)。可使用光刻将光致抗蚀剂图案化成具有环形开口。光致抗蚀剂可在TSV蚀刻工艺期间充当临时蚀刻掩模。可已通过将导电材料(例如，铜)镀敷于衬底410上而形成结合垫层440。衬底的TSV蚀刻可形成具有大约50-150微米的典型深度的环状开口420。
图5中描绘图4的处理中的裸片的俯视图，在图5中，展示了覆盖衬底410的顶表面的光致抗蚀剂层430。在图5中还展示的是除去光致抗蚀剂层430的环形区域520。
图6是在将钝化层610形成于环状开口420的侧壁上之后的图4的处理中的裸片的横截面图。根据实例实施例，可通过使用(例如)脉冲沉积层(PDL)工艺而将钝化材料(例如，氧化铝)沉积于环状开口的表面(侧壁和底部区域620)上而形成钝化层610。在下一步骤中，可从所有水平表面移除钝化层610。可通过(例如)间隔物蚀刻来执行从底部区域620和顶表面移除钝化层610，所述间隔物蚀刻可优先从水平表面移除沉积物。
可如图7中所示用导电材料来填充环状开口以形成垂直部分730和平面末端部分720。侧壁钝化层610可防止在所建构的封装或装置的操作期间电流经由侧壁而从金属通孔泄漏到衬底410。在一实例实施例中，环状开口的填充可以沉积导电材料(例如，铜)的薄种子层而开始，其可促进形成金属通孔的下一步骤。
可通过将导电材料(例如，铜)沉积(例如，电镀)于所要区域上而执行金属通孔的形成。所要区域可包括结合垫和环状开口的表面区域。可经由光刻图案化工艺来界定所要区域。电镀铜可形成实心金属通孔。在形成实心金属通孔之后，可从衬底表面移除(例如，剥离)种子层和光致抗蚀剂层750(在光刻图案化工艺中沉积)。在一实例实施例中，可在形成种子层之前沉积阻挡层。阻挡层可防止电镀铜扩散到衬底中。还可从未通过电镀工艺覆盖的区域移除阻挡层。
图8是在形成凹导电槽840之后的图7的处理中的裸片的横截面图。在将金属通孔形成于衬底的顶表面上之后，将凹导电槽840形成于背侧表面上。实现凹导电槽840可涉及使用(例如)背侧研磨工艺而从背表面(与平面末端部分720相对)将衬底薄化。为在背侧研磨工艺期间使衬底免受任何损坏，可使用粘附层820将临时载体810(例如，玻璃或硅晶片)粘附到衬底的顶表面。
背侧研磨可使衬底410具有通常50-150微米的厚度。背侧研磨可继续下去，直到衬底材料大体上与金属通孔的底部分齐平。然而，为形成凹导电槽840，必须暴露环状金属通孔的高度的一些部分(例如，10-15微米)。此可通过(例如)使用整体湿蚀刻或干蚀刻来选择性地移除衬底材料以相对于金属通孔而制成衬底材料凹部并形成由环状金属通孔的内侧壁包围的开口而实现。
在形成凹导电槽之前的下一步骤可为将背侧钝化层830形成于整个凹表面上(除了将形成凹导电槽的区域之外)。此区域由数字参考850描绘，在所述区域中需要暴露金属通孔(通过移除环状TSV的侧壁钝化部)以便使凹导电槽840与金属通孔成导电接触。在一实例实施例中，可通过使用(例如)可经由光刻工艺来图案化的光敏旋涂电介质聚合物层来执行将背侧钝化层830沉积于所选区域上。
可通过将导电材料(例如，UBM)选择性地沉积于未由背侧钝化层830覆盖的区域上而执行凹导电槽840的形成。在此阶段处所处理的裸片可包括由导电金属通孔和UBM槽(即，凹导电槽840)形成的TSV且其可用作底部裸片。
图9是在形成延伸出通孔的平面末端部分的圆柱形导电柱920之后的图7的处理中的裸片的横截面图。如图1中所示的中间裸片120可包括图9中所示的具有参考数字920的导电柱。在一实例实施例中，可在形成金属通孔之后实现导电柱920的形成。形成导电柱920的过程可先将厚掩模层910首先形成于衬底的顶表面(包括环状通孔的平面末端部分)上，且接着从其上将形成导电柱920的区域选择性地移除厚掩模层910。掩模层910的厚度可等于导电柱920的高度。可选择导电柱920的高度以使得导电柱可配合到UBM槽840中。在一实例实施例中，导电柱920可与金属通孔对准。
在从被考虑用于形成导电柱920的区域(例如，小于环状通孔内部的中心部分区域的区域)选择性地移除掩模层910之后，可通过将导电层(例如，铜、焊料材料等)选择性地沉积(例如，电镀)于通过选择性地移除掩模层910而形成的洞内部来形成导电柱920。在下一步骤中，可选择性地移除掩模层910以暴露导电柱920。从图9的处理中的裸片形成中间裸片可能需要在图8的论述下所清楚表达的过程。
图10是高级流程图，其说明在一实例实施例中用于形成具有凹导电槽的环状通孔的方法1000。所述方法1000在操作1010处开始，在操作1010中可将导电环状通孔形成于衬底410的底表面上，所述导电环状通孔经配置以形成由环状通孔730的内壁包围的凹部分。所述方法还可包括在操作1020处形成用以覆盖所述凹部分的导电层以配置凹导电槽840(如图8中所示)。
图11是高级流程图，其说明在一实例实施例中用于使用具有凹导电槽的环状通孔和导电柱来堆叠裸片的方法1100。所述方法1100可在操作1102处开始，在操作1102中可配置第一裸片110(见图1)。所述配置可包括形成结构组件，所述结构组件包括：A.形成环状穿衬底通孔(TSV)，其包括形成覆盖衬底206的第一表面的一部分的平面末端部分235，其中环状TSV的部分从衬底206的第二表面延伸；B.形成非导电层(例如，背侧钝化层204)，以覆盖衬底的第二表面的包围环状TSV的部分并留下在环状TSV内部的凹部分；以及C.将凸块下层210沉积于凹部分上以将UBM槽配置于第一裸片110的底表面上，其中第一裸片110的底表面与衬底206的第二表面相同。
在操作1104处，可配置第二裸片(例如，图1的中间裸片120)。第二裸片的配置可包括形成大体上与上文关于第一裸片所论述的结构组件相同的结构组件(除了进一步将延伸出平面末端部分235的导电圆柱形柱310安置于第二裸片的顶表面上之外)。在一实例实施例中，导电柱310可大小经设计以配合到由第一裸片的UBM层210形成的凹导电槽中。
图12是流程图，其说明在一实例实施例中用于形成具有凹导电槽的环状通孔的方法1200。所述方法在操作1210处开始，在操作1210中从衬底410的第一表面来蚀刻衬底410以形成环状开口420。在操作1220处，可将第一钝化层610沉积于环状开口420的侧壁上。在操作1230处，可用第一导电材料(例如，铜)来填充环状开口420以使得形成金属通孔730。所述金属通孔730可包括平面末端部分720，所述平面末端部分720覆盖衬底410的第一表面(例如，顶表面)的一部分且在第一表面上从环状开口420的外边缘向外延伸。
在操作1240处，可通过从衬底410的第二表面(包括由环状通孔730包围的区域)移除衬底材料(例如，背侧研磨和蚀刻)而将衬底410薄化到金属通孔730的一部分从衬底410的第二表面延伸出的程度。可从金属通孔的暴露末端的内壁和内部分850移除(例如，蚀刻掉)第一钝化层610(操作1250)。在操作1260处，可将第二钝化层830沉积于衬底410的第二表面的包围金属通孔730的暴露末端的内部分的一部分上，以使得可形成由金属通孔730的内壁包围的凹区域。在操作1270处，可将第二导电材料(例如，UBM)层涂布于凹区域的表面上以形成导电UBM槽。
图13是横截面图，其说明形成裸片的一部分的结构1300的一实例实施例，所述裸片包括具有凹导电槽1350和圆柱形柱1330的通孔1310。可将通孔1310形成为实心圆柱形通孔1310，其包括与结合垫1360和柱1330成导电接触的平面末端部分1320。通孔1310可包括由形成UBM槽1340的UBM层1350覆盖的凹部分。背侧钝化层1370可经图案化并用以充当用于进入到实心圆柱形通孔1310中的凹部分的蚀刻掩模。还可将背侧钝化层1370用作绝缘层。在一实例实施例中，柱1330可经大小设计以配合到大体上类似于UBM槽1340的UBM槽中。在实例实施例中，衬底410可为包括电子电路的裸片的部分。所述电子电路可包括DRAM、SDRAM、PCRAM、快闪存储器、成像器等。
图14是框图，其说明系统1400的一实例实施例，所述系统1400包括通过图11的方法形成的电子封装。根据实例实施例，系统1400可表示大型计算机、桌上型或膝上型计算机、个人数字助理(PDA)、蜂窝式电话等。系统1400可包括耦合到总线1450的一个或一个以上处理器1410、一个或一个以上RAM 1420、若干输入/输出装置1430和一个或一个以上存储装置1440。在一实例实施例中，RAM 1420可包括SRAM、DRAM、PCRAM或快闪存储器。存储装置1440可包括硬盘、压缩盘(CD)或数字多功能盘(DVD)。在实例实施例中，处理器1410或RAM 1420可包括由借助于如图1中所示的具有凹导电槽的环状通孔堆叠而成的裸片组成的电子封装。
已描述用于借助于具有凹导电槽的环状通孔和导电柱进行裸片堆叠的裸片槽结构和方法。尽管已描述了特定实施例，但将明显的是，可对这些实施例作出各种修改和改变。因此，将以说明性意义而非限制性意义来看待说明书和图式。
提供本发明的摘要以遵守需要允许读者快速确定技术性揭示内容的性质的摘要的37C.F.R.§1.72(b)。在理解其将不用以解释或限制权利要求书的情况下将其提交。另外，在上述“具体实施方式”中，可看到，出于简化本发明的目的而在单个实施例中将各种特征分组在一起。本发明的此方法将不被解释为限制权利要求书。因此，所附权利要求书在此并入“具体实施方式”中，其中每一权利要求作为单独实施例而具独立性。

Claims (33)

1.一种用于裸片堆叠的设备，其包含：
衬底，其包括在所述衬底的底表面上、包围所述衬底的一部分的导电环状通孔，所述导电环状通孔具有由所述环状通孔的内壁包围的凹部分；
导电层，其覆盖所述凹部分而被配置为导电槽。
2.根据权利要求1所述的设备，其中所述衬底包括硅，所述导电环状通孔包括铜，且所述导电层包括凸块下材料。
3.根据权利要求1所述的设备，其中所述环状通孔包括覆盖所述衬底的顶表面的一部分的平面末端部分。
4.根据权利要求3所述的设备，其进一步包括从所述环状通孔的所述平面末端部分延伸出的导电圆柱形柱。
5.根据权利要求4所述的设备，其中所述导电圆柱形柱相对于所述衬底的平面是垂直的。
6.根据权利要求1所述的设备，其中所述衬底是裸片的一部分且所述衬底的所述顶表面是所述裸片的有效表面。
7.根据权利要求6所述的设备，其中所述裸片的所述有效表面包括集成电子装置。
8.一种用于裸片堆叠的方法，其包含：
将导电环状通孔形成为包围衬底的一部分，所述导电环状通孔形成于衬底的底表面上，所述导电环状通孔具有由所述环状通孔的内壁包围的凹部分；以及
形成覆盖所述凹部分的导电层以形成导电槽。
9.根据权利要求8所述的方法，其中所述导电环状通孔的所述形成包括形成覆盖所述衬底的顶表面的一部分的平面末端部分。
10.根据权利要求9所述的方法，其进一步包括将从所述衬底延伸出的导电圆柱形柱形成于所述环状通孔的所述平面末端部分上。
11.一种电子封装，其包含：
第一裸片，其包括：
衬底，其具有包围所述衬底的一部分的环状穿衬底通孔(TSV)，并且所述环状穿衬底通孔包括覆盖所述衬底的第一表面的一部分的平面末端部分；
非导电层，其覆盖所述衬底的第二表面的包围所述环状穿衬底通孔的部分；以及
凸块下层，其在所述第二表面处安置于所述环状穿衬底通孔中的凹部分中，所述凸块下层被配置为所述第一裸片的底表面上的导电槽，其中所述第一裸片的所述底表面为所述衬底的所述第二表面；以及
第二裸片，其在所述电子封装中相对于所述第一裸片而布置，所述第二裸片具有形成于所述第二裸片的顶表面上的导电圆柱形柱，其中所述导电圆柱形柱大小经设计以配合到所述第一裸片的所述导电槽中。
12.根据权利要求11所述的电子封装，其进一步包括安置于所述衬底与所述环状穿衬底通孔的所述平面末端部分之间的导电垫。
13.根据权利要求11所述的电子封装，其中所述衬底包括硅。
14.根据权利要求11所述的电子封装，其中所述第一裸片或所述第二裸片中的至少一者包括集成电子装置。
15.根据权利要求11所述的电子封装，其中所述环状穿衬底通孔包括铜。
16.根据权利要求11所述的电子封装，其中所述非导电层包括背侧钝化层。
17.根据权利要求11所述的电子封装，其中所述第一裸片和所述第二裸片经堆叠以使得所述第二裸片的所述导电圆柱形柱配合到所述第一裸片的所述导电槽中，从而在所述第二裸片的所述导电圆柱形柱与所述第一裸片的所述导电槽之间形成导电连接。
18.根据权利要求17所述的电子封装，其进一步包括顶部裸片，其中所述顶部裸片包括金属柱，所述金属柱大小经设计以配合到所述第二裸片的环状通孔中的导电槽中，以使得所述金属柱安置到所述第二裸片的所述导电槽中以在所述金属柱与所述第二裸片的所述导电槽之间形成导电连接。
19.根据权利要求17所述的电子封装，所述电子封装包括一个或一个以上额外裸片，所述一个或一个以上额外裸片通过所述额外裸片中的一者的安置于所述第二裸片的环状通孔中的导电槽中的导电圆柱形柱而连接到所述堆叠。
20.一种用于制造电子封装的方法，其包含：
配置第一裸片，其包括：
形成包围衬底的一部分的环状穿衬底通孔(TSV)，所述环状穿衬底通孔具有覆盖衬底的第一表面的一部分的平面末端部分且具有所述环状穿衬底通孔的暴露于所述衬底的第二表面处的部分；
形成非导电层，所述非导电层覆盖所述衬底的所述第二表面的包围所述环状穿衬底通孔的部分且在所述第二表面处使在所述环状穿衬底通孔内部的凹部分未被覆盖；以及
将凸块下层沉积于所述凹部分上，从而将导电槽形成于所述第一裸片的底表面上，所述第一裸片的所述底表面为所述衬底的所述第二表面；以及
在所述电子封装中相对于所述第一裸片而配置第二裸片，其包括将导电圆柱形柱形成于所述第二裸片的顶表面上，以使得所述导电圆柱形柱大小经设计以配合到所述第一裸片的所述导电槽中。
21.根据权利要求20所述的方法，其进一步包括将所述第一裸片和所述第二裸片配置于堆叠中，以使得所述第二裸片的所述导电圆柱形柱配合到所述第一裸片的所述导电槽中，以在所述第二裸片的所述导电圆柱形柱与所述第一裸片的所述导电槽之间形成导电连接。
22.根据权利要求21所述的方法，其进一步包括将顶部裸片安置于所述第一裸片与所述第二裸片的所述堆叠上，以使得所述顶部裸片的金属柱安置于所述第二裸片的环状通孔中的导电槽中，以在所述金属柱与所述第二裸片的所述导电槽之间形成导电连接。
23.根据权利要求21所述的方法，其中所述方法包括通过将一个或一个以上额外裸片中的一者的导电圆柱形柱安置于所述第二裸片的环状通孔中的导电槽中而将所述额外裸片连接到所述堆叠。
24.一种用于制造电子封装的方法，所述方法包含：
从衬底的第一表面蚀刻所述衬底以形成包围所述衬底的一部分环状开口；将第一钝化层形成于所述环状开口的侧壁上；
用第一导电材料填充所述环状开口以使得形成金属通孔，所述金属通孔包括平面末端部分，所述平面末端部分覆盖所述衬底的所述第一表面的一部分且在所述第一表面上从所述环状开口的外边缘向外延伸；
通过从所述衬底的包括由所述金属通孔包围的区域的第二表面移除衬底材料而将所述衬底薄化到所述金属通孔的一部分从所述经薄化的衬底的所述第二表面延伸出的程度；
在所述经薄化的衬底的所述第二表面处从所述金属通孔的暴露末端的内壁和内部分移除所述第一钝化层；
将第二钝化层形成于所述衬底的所述第二表面的包围所述金属通孔的所述暴露末端的所述内部分的一部分上，以使得形成由所述金属通孔的内壁包围的凹区域；以及
将第二导电材料层涂布于所述凹区域上以形成导电槽。
25.根据权利要求24所述的方法，其进一步包括形成导电圆柱形柱，所述导电圆柱形柱从所述衬底的所述第一表面垂直延伸出且大小经设计以配合到所述导电槽中。
26.根据权利要求25所述的方法，其中所述导电圆柱形柱的所述形成包括：将所述柱形成于所述金属通孔的所述平面末端部分上。
27.根据权利要求24所述的方法，其中在所述衬底的所述第一表面的涂布有导电垫的区域上执行对所述衬底的蚀刻，其中所述环状开口与所述导电垫同心。
28.根据权利要求24所述的方法，其中将所述第一钝化层形成于所述环状开口的侧壁上包括：将所述第一钝化层形成于所述环状开口的整个表面上且接着从所述环状开口的底表面移除所述第一钝化层。
29.根据权利要求24所述的方法，其中所述第一导电材料包括铜，所述第二导电材料包括凸块下材料，且所述衬底材料包括硅。
30.一种包含电子封装的系统，其包含：
处理器，其包括通过堆叠多个裸片而形成的所述电子封装，其中所述多个裸片中的至少一个裸片包括形成于环状通孔上的凹导电槽，所述环状通孔形成于所述至少一个裸片的衬底上并且包围所述衬底的一部分；以及
存储器，其包括至少一个随机存取存储器封装。
31.根据权利要求30所述的系统，其中所述多个裸片中的至少一个裸片包括大小经设计以配合到所述凹导电槽中的导电圆柱形柱。
32.根据权利要求30所述的系统，其中所述至少一个随机存取存储器封装是通过堆叠多个裸片而形成的，其中所述多个裸片中的至少一个裸片包括形成于环状通孔上的凹导电槽。
33.根据权利要求30所述的系统，其中所述多个裸片中的至少一个裸片包括大小经设计以配合到所述凹导电槽中的导电圆柱形柱。
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