JP4179186B2 - 配線基板およびその製造方法および半導体装置 - Google Patents
配線基板およびその製造方法および半導体装置 Download PDFInfo
- Publication number
- JP4179186B2 JP4179186B2 JP2004049132A JP2004049132A JP4179186B2 JP 4179186 B2 JP4179186 B2 JP 4179186B2 JP 2004049132 A JP2004049132 A JP 2004049132A JP 2004049132 A JP2004049132 A JP 2004049132A JP 4179186 B2 JP4179186 B2 JP 4179186B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon substrate
- insulating
- substrate
- connecting portion
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6616—Vertical connections, e.g. vias
- H01L2223/6622—Coaxial feed-throughs in active or passive substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
前記絶縁部の環状の絶縁膜は、前記接続部の側周に形成された絶縁膜と前記シリコン基板の前記配線層が形成されている側の面で連続する同一層の絶縁膜で形成されている
ことを最も主要な特徴とする。
Claims (9)
- 実装基板にハンダバンプで接続され、前記実装基板に接続される面とは反対面側に集積回路チップを実装するもので、
前記集積回路チップの少なくとも一部の配線層がシリコン基板に形成され、前記配線層と前記ハンダバンプに接続するもので該シリコン基板を貫通する導電性の接続部を備え、
前記接続部の側周に形成された絶縁膜と、
前記接続部の側方に前記シリコン基板の一部を介して前記接続部を囲むように形成された絶縁部を備え、
前記絶縁部は、前記接続部の側周に形成された絶縁膜と前記シリコン基板の前記配線層が形成されている側の面で連続する同一層の絶縁膜で形成されている
配線基板。 - 前記絶縁部は、前記接続部の側方に前記シリコン基板の一部を介して前記接続部の側方を囲む環状の絶縁部からなる
ことを特徴とする請求項1記載の配線基板。 - 前記絶縁部は、前記接続部の側方に前記シリコン基板の一部を介して前記接続部の側方を囲む複数の環状の絶縁部が同心円状に形成されている
ことを特徴とする請求項1記載の配線基板。 - 前記絶縁部は、
前記接続部の側方に前記シリコン基板の一部を介して前記接続部の側方を囲む環状の絶縁部と、
前記環状の絶縁部とは別に前記接続部の側方を囲むように配置された複数の柱状の絶縁部とからなる
ことを特徴とする請求項1記載の配線基板。 - 一面側を実装基板にハンダバンプで接続し、前記実装基板に接続される面とは反対面側に集積回路チップを実装するもので、前記集積回路チップの少なくとも一部の配線層をシリコン基板に形成し、前記配線層と前記ハンダバンプに接続して該シリコン基板を貫通する導電性の接続部を形成する配線基板の製造方法において、
前記接続部を形成するための穴を前記シリコン基板に形成する際に、前記穴の側方に前記シリコン基板の一部を介して前記穴の側方を囲むように凹部を形成する工程と、
前記穴および前記凹部の各内面を含む前記シリコン基板表面に絶縁膜および前記接続部を形成するための導電性膜を順に形成する工程と、
前記シリコン基板上に形成された余剰な前記導電性膜および前記絶縁膜を研磨によって除去する工程とを備え、
さらに前記シリコン基板の裏面を研磨によって除去して、前記接続部および前記絶縁部を前記シリコン基板表面より露出させる工程
を備えたことを特徴とする配線基板の製造方法。 - 前記凹部は、前記穴の側方に前記シリコン基板の一部を介して囲む環状の溝で形成される
ことを特徴とする請求項5記載の配線基板の製造方法。 - 前記凹部は、前記穴の側方に前記シリコン基板の一部を介して囲む複数の同心円状の溝で形成される
ことを特徴とする請求項5記載の配線基板の製造方法。 - 前記凹部は、前記穴の側方に前記シリコン基板の一部を介して囲む環状の溝と、前記環状の溝とは別に前記穴の側方を囲むように配置された複数の穴とにより形成される
ことを特徴とする請求項5記載の配線基板の製造方法。 - 配線基板の一面側にハンダバンプで実装基板が接続され、前記実装基板を接続した側とは反対面側に集積回路チップが実装されていて、
前記配線基板は、
前記集積回路チップの少なくとも一部の配線層がシリコン基板に形成され、前記配線層と前記ハンダバンプに接続するもので該シリコン基板を貫通する導電性の接続部を備え、
前記接続部の側周に形成された絶縁膜と、
前記接続部の側方に前記シリコン基板の一部を介して前記接続部を囲むように少なくとも環状の絶縁膜からなる絶縁部を備え、
前記絶縁部の環状の絶縁膜は、前記接続部の側周に形成された絶縁膜と前記シリコン基板の前記配線層が形成されている側の面で連続する同一層の絶縁膜で形成されている
半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004049132A JP4179186B2 (ja) | 2004-02-25 | 2004-02-25 | 配線基板およびその製造方法および半導体装置 |
TW094104906A TWI251926B (en) | 2004-02-25 | 2005-02-18 | Wiring substrate, manufacturing method thereof, and semiconductor device |
US11/064,495 US8035234B2 (en) | 2004-02-25 | 2005-02-23 | Wiring substrate, manufacturing method thereof, and semiconductor device |
KR1020050015388A KR101139650B1 (ko) | 2004-02-25 | 2005-02-24 | 배선 기판, 그 제조 방법, 및 반도체 장치 |
US11/969,273 US7665209B2 (en) | 2004-02-25 | 2008-01-04 | Method manufacturing wiring substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004049132A JP4179186B2 (ja) | 2004-02-25 | 2004-02-25 | 配線基板およびその製造方法および半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005243763A JP2005243763A (ja) | 2005-09-08 |
JP4179186B2 true JP4179186B2 (ja) | 2008-11-12 |
Family
ID=34858233
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004049132A Expired - Fee Related JP4179186B2 (ja) | 2004-02-25 | 2004-02-25 | 配線基板およびその製造方法および半導体装置 |
Country Status (4)
Country | Link |
---|---|
US (2) | US8035234B2 (ja) |
JP (1) | JP4179186B2 (ja) |
KR (1) | KR101139650B1 (ja) |
TW (1) | TWI251926B (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7933935B2 (en) * | 2006-10-16 | 2011-04-26 | Oracle International Corporation | Efficient partitioning technique while managing large XML documents |
US7821107B2 (en) * | 2008-04-22 | 2010-10-26 | Micron Technology, Inc. | Die stacking with an annular via having a recessed socket |
US8413324B2 (en) * | 2009-06-09 | 2013-04-09 | Ibiden Co., Ltd. | Method of manufacturing double-sided circuit board |
JP5357706B2 (ja) * | 2009-11-10 | 2013-12-04 | パナソニック株式会社 | 半導体実装構造体 |
US20110291287A1 (en) * | 2010-05-25 | 2011-12-01 | Xilinx, Inc. | Through-silicon vias with low parasitic capacitance |
TWI573203B (zh) * | 2012-02-16 | 2017-03-01 | 索泰克公司 | 製作包含有具導電貫孔間置結構之半導體構造之方法及其相關構造與元件 |
US9123738B1 (en) | 2014-05-16 | 2015-09-01 | Xilinx, Inc. | Transmission line via structure |
CN113122026B (zh) | 2014-08-29 | 2023-01-17 | 欧励隆工程炭公司 | 控制炭黑孔隙率的方法 |
JP6744202B2 (ja) * | 2016-12-06 | 2020-08-19 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5477933A (en) * | 1994-10-24 | 1995-12-26 | At&T Corp. | Electronic device interconnection techniques |
JP3425573B2 (ja) * | 1999-05-19 | 2003-07-14 | Necエレクトロニクス株式会社 | 半導体装置 |
US6388208B1 (en) * | 1999-06-11 | 2002-05-14 | Teradyne, Inc. | Multi-connection via with electrically isolated segments |
JP2001102479A (ja) | 1999-09-27 | 2001-04-13 | Toshiba Corp | 半導体集積回路装置およびその製造方法 |
JP2002198374A (ja) * | 2000-10-16 | 2002-07-12 | Sharp Corp | 半導体装置およびその製造方法 |
DE10127952A1 (de) * | 2001-06-08 | 2002-12-19 | Infineon Technologies Ag | Laterale PIN-Diode und Verfahren zur Herstellung derselben |
JP3910387B2 (ja) * | 2001-08-24 | 2007-04-25 | 新光電気工業株式会社 | 半導体パッケージ及びその製造方法並びに半導体装置 |
US6750516B2 (en) * | 2001-10-18 | 2004-06-15 | Hewlett-Packard Development Company, L.P. | Systems and methods for electrically isolating portions of wafers |
JP4198906B2 (ja) * | 2001-11-15 | 2008-12-17 | 株式会社ルネサステクノロジ | 半導体装置および半導体装置の製造方法 |
US6606237B1 (en) * | 2002-06-27 | 2003-08-12 | Murata Manufacturing Co., Ltd. | Multilayer capacitor, wiring board, decoupling circuit, and high frequency circuit incorporating the same |
JP2005086036A (ja) | 2003-09-09 | 2005-03-31 | Fujitsu Ltd | 配線板 |
US7276787B2 (en) * | 2003-12-05 | 2007-10-02 | International Business Machines Corporation | Silicon chip carrier with conductive through-vias and method for fabricating same |
-
2004
- 2004-02-25 JP JP2004049132A patent/JP4179186B2/ja not_active Expired - Fee Related
-
2005
- 2005-02-18 TW TW094104906A patent/TWI251926B/zh not_active IP Right Cessation
- 2005-02-23 US US11/064,495 patent/US8035234B2/en active Active
- 2005-02-24 KR KR1020050015388A patent/KR101139650B1/ko active IP Right Grant
-
2008
- 2008-01-04 US US11/969,273 patent/US7665209B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
TW200531252A (en) | 2005-09-16 |
KR101139650B1 (ko) | 2012-05-14 |
US7665209B2 (en) | 2010-02-23 |
KR20060042148A (ko) | 2006-05-12 |
US20050184401A1 (en) | 2005-08-25 |
JP2005243763A (ja) | 2005-09-08 |
US8035234B2 (en) | 2011-10-11 |
TWI251926B (en) | 2006-03-21 |
US20080127489A1 (en) | 2008-06-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4995551B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
JP4937842B2 (ja) | 半導体装置およびその製造方法 | |
KR101139650B1 (ko) | 배선 기판, 그 제조 방법, 및 반도체 장치 | |
JP4035034B2 (ja) | 半導体装置およびその製造方法 | |
US10651158B2 (en) | Method of forming a semiconductor device having through silicon vias | |
KR20090076832A (ko) | 반도체 장치 및 그 제조 방법 | |
JP2011258687A (ja) | 半導体装置およびその製造方法 | |
US20200075552A1 (en) | Multi-wafer stack structure and forming method thereof | |
JP4696152B2 (ja) | 半導体装置の製造方法および半導体装置 | |
JP2019140145A (ja) | 半導体装置およびその製造方法 | |
JP2008135553A (ja) | 基板積層方法及び基板が積層された半導体装置 | |
WO2017038108A1 (ja) | 半導体装置、及び半導体装置の製造方法 | |
JP4764710B2 (ja) | 半導体装置とその製造方法 | |
US10651374B2 (en) | Semiconductor device, and method for manufacturing the same | |
JP5118614B2 (ja) | 半導体装置の製造方法 | |
JP2009135193A (ja) | シリコンスルーホールを有する半導体チップ装置及びその製造方法 | |
JP7056910B2 (ja) | 半導体装置およびその製造方法 | |
JP2013058525A (ja) | 半導体装置、及びその製造方法 | |
JP2005033105A (ja) | 半導体装置及びその製造方法、回路基板並びに電子機器 | |
JP2012134526A (ja) | 半導体装置 | |
TW201312665A (zh) | 一種晶圓級的封裝結構及其製備方法 | |
JP5751131B2 (ja) | 半導体装置及びその製造方法 | |
CN110828317B (zh) | 封装基板结构与其接合方法 | |
JP2008159950A (ja) | 半導体装置 | |
JP2022102371A (ja) | 半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20071218 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080213 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080408 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080609 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20080805 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20080818 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110905 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120905 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130905 Year of fee payment: 5 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |