WO2005122706A2

WO2005122706A2 - Method of aligning semiconductor device and semiconductor structure thereof

Info

Publication number: WO2005122706A2
Application number: PCT/KR2005/000853
Authority: WO
Inventors: Joon-Mo Kang
Original assignee: Joon-Mo Kang
Priority date: 2004-05-31
Filing date: 2005-03-24
Publication date: 2005-12-29
Also published as: WO2005122706A3

Abstract

The invention relates to a method of aligning semiconductor devices in die stacking and a semiconductor structure fabricated by the method. In stacking a die on a wafer, for example, a first semiconductor device on the wafer and a second semiconductor device on the die are aligned by a magnetic force between at least a first magnetic body belonging to the wafer and at least a second magnetic body belonging to the die. After the alignment, the die is made not to move by the magnetic force between the magnetic bodies to maintain the alignment which is necessary for the fabrication of a semiconductor structure.

Description

Description METHOD OF ALIGNING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STRUCTURE THEREOF Technical Field

[1] The invention relates to a method of aligning semiconductor devices and a semiconductor structure thereof. More particularly, the present invention relates to a method of aligning semiconductor devices in die-to-wafer or die-to-die stacking, or a method of aligning a semiconductor device to a chip support. The present invention relates also to a semiconductor structure fabricated by the same method. Background Art

[2] A vertical integration of semiconductor devices has the advantages of improving system performances by reducing the wiring length between the devices, reducing the area occupied by the devices, and reducing the manufacturing cost by fabricating different kind of devices separately and integrating the devices thereafter.

[3] Applying the vertical integration, a SoC (System on Chip) that semiconductor devices are integrated in a single chip can be realized. Semiconductor devices for the integration include memory devices such as DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory) or EPROM (Electrically Programmable Read Only Memory), logic devices such as FPGA (Field Programmable Gate Array), communication devices such as RFIC (Radio Frequency Integrated Circuit), sensor devices such as CCD (Charge Coupled Device), photonic devices such as photo diode, and microprocessors.

[4] For a method of achieving the vertical integration of semiconductor devices, a wafer is stacked on another wafer, which is referred to as wafer-to-wafer stacking. For other methods of the vertical integration, separated dies are stacked on a wafer, which is referred to as die-to-wafer stacking, or a separated die is stacked on another die, which is referred to as die-to-die stacking.

[5] While a method of wafer-to-wafer stacking can stack many dies at a same time, this method has a problem that the product yield of stacked devices decreases geometrically with increasing number of stacked layers.

[6] In die-to- wafer or die-to-die stacking, known good dies (KGD), which have passed electrical or optical tests, are selected and stacked. Therefore, the aforementioned yield decrease can be avoided. On the other hand, these methods have the disadvantage of a long processing time.

[7] In all of the above stacking methods, an aligning step between two semiconductor devices which have been formed respectively on two substrates (wafer or die) to be stacked is important because the product yield of stacked devices and the productivity of stacking process are decided according to the accuracy and speed of aligning. Especially, as the pitch of inter-device interconnects such as vias, bonding pads or solder bumps which connect the vertically stacked devices gets smaller, a higher aligning accuracy is required.

[8] FIGS. 1 and 2 show cross-sectional views illustrating aligning methods according to the prior arts. Aligning methods according to the prior arts will be described with reference to the drawings.

[9] As shown in FIG. 1, align marks 3, 4 are formed on an upper substrate 1 and on a lower substrate 2, respectively. Although not shown, the substrates 1, 2 contain semiconductor devices. The two substrates 1, 2 are put over an infrared (IR) light source 5. The positions of the two align marks 3, 4 are known by detecting a transmitted infrared image through an objective 6. The semiconductor devices are aligned by moving either the upper substrate 1 or the lower substrate 2 until the two align marks 3, 4 are aligned. While aligning methods using infrared light are simple because infrared light can transmit semiconductor substrates, these methods have a limit to be applied to devices with dense metal wiring because infrared light cannot transmit metal. Another disadvantage of infrared light is its longer wavelength compared to visible or ultraviolet light, which results in lower resolving power than that obtained with visible or ultraviolet light.

[10] FIG. 2 shows cross-sectional views illustrating aligning stages according to another prior art. Detailed description of each stage is as follows. At stage-1, after aligning an upper objective 6 and a lower objective 7, an upper substrate 1 is moved so that an align mark 3 of the upper substrate 1 is aligned to the center of the lower objective 7, and once aligned, data about an aligned position of the upper substrate 1 are saved. Next, at stage-2, a lower substrate 2 is moved so that an align mark 4 of the lower substrate 2 is aligned to the center of the upper objective 6. Next, at stage-3, according to the saved data the upper substrate 1 is moved again to the aligned position at stage- 1, and then both the upper substrate 1 and the lower substrate 2 are alined to the center of the upper and lower objectives 6, 7. Here, semiconductor devices on the two substrates 1, 2 are automatically aligned to each other because the two objectives 6, 7 have been already aligned. In the method shown in FIG. 2, light of a short wavelength can be used because light does not need to transmit the substrates. While this method can achieve a fine alignment with light of a short wavelength, this method is more complicated than the method shown in FIG. 1 because it requires two aligning steps.

[11] In the aforementioned aligning methods according to the prior arts, align marks are used. To make the align marks come within a predetermined zone, a stage which supports a substrate is controlled to move. The stage can be controlled to move either manually, or automatically with the help of image processing. The method by an automated stage is suitable for mass production because of its high speed and little deviation according to individual users. When a required aligning accuracy is less than 1 μ m, the aligning speed by an automated stage is about 1 minute per aligning Therefore, while such an aligning speed does not cause a problem in wafer-to-waier stacking when compared to the fabrication speed of other processes, a serious drop of productivity is expected with that aligning speed in die-to-waier or a die-to-die stacking.

[12] Another issue in stacking semiconductor devices lor a vertical integration is fixing wafers or dies preliminarily after aligning semiconductor devices so as to maintain the alignment until next processes. While two stacked waters in waler-to-waler stacking can be fixed preliminarily by clamping, tew methods are available to fix preliminarily dies to a wafer in die-to-wafer stacking, or to fix a die to another die in die-to-die stacking. Although a bonding method by epoxy or the like is currently used tor die fixing, this method is not a preliminary tixing In die-to-water or die-to-die stacking, the lack of preliminary die tixing is an obstacle to apply various interconnecting methods such as interconnecting through bonding pads or interconnecting through solder bumps.

[13] A die (or dies) can be stacked also on a chip support, which will be reterred to as 'die to chip support stacking' hereinafter, in semiconductor packaging process such as flip chip bonding. Here, a higher aligning accuracy is also required as the number of bumps used for joining a semiconductor device on a die to a chip support increases per unit area, in other words as the bump pitch decreases. Aligning methods according to the prior arts have a limit to improve the aligning accuracy without sacrificing the productivity. Disclosure of Invention Technical Problem

[14] As described above, the speed of aligning semiconductor devices according to the prior arts is too slow to apply in die stacking which requires a high aligning accuracy.

[15] Another technical problem of the prior arts in die stacking is the lack of methods to maintain the alignment of semiconductor devices until next processes Technical Solution

[16] To solve the above problems, it is an object ot the present invention to provide an aligning method which enables a fast alignment between semiconductor devices in die- to-wafer or die-to-die stacking, or a fast alignment between a semiconductor device and a chip support in die to chip support stacking, and after the alignment, further tixes the aligned die (or dies) preliminarily so as to maintain the alignment until next processes

[17] It is another object of the present invention to provide a semiconductor structure fabricated by the above method.

[18] According to one embodiment ot the present invention to achieve the above tirst objet, a method of aligning a first semiconductor device on a wafer and a second semiconductor device on a die in die-to-wafer stacking is characterized in that the first semiconductor device on the water and the second senuconductor device on the die are aligned by a magnetic force between at least a first magnetic body belonging to the wafer and at least a second magnetic body belonging to the die

[19] According to another embodiment of the present invention to achieve the above first objet, a method ot aligning a first semiconductor device on a first die and a second semiconductor device on a second die in die-to-die stacking is characterized in that the first semiconductor device on the first die and the second semiconductor device on the second die are aligned by a magnetic force between at least a first magnetic body belonging to the tirst die and at least a second magnetic body belonging to the second

[20] According to another embodiment of the present invention to achieve the above first objet, a method of aligning a semiconductor device on a die to a chip support in die to chip support stacking is characterized in that the semiconductor device on the die is aligned to the chip support by a magnetic force between at least a first magnetic body belonging to the chip support and at least a second magnetic body belonging to

[21 ] According to another embodiment of the present invention to achieve the above second objet, a senuconductor structure comprises a substrate, a die stacked on the substrate, a plurality ot interconnects between the substrate and the die, and at least a first magnetic body belonging to the substrate which interacts with at least a second magnetic body belonging to the die for aligning the interconnects.

[22] According to another embodiment ot the present invention to achieve the above second objet, a senuconductor structure comprises a substrate having first bonding pads thereon, a die stacked on the substrate and having second bonding pads joined to the first bonding pads, and at least a first magnetic body belonging to the substrate which interacts with at least a second magnetic body belonging to the die tor aligning the first bonding pads and the second bonding pads. Description of Drawings

[23] The above-mentioned objects and advantages ot the present invention will be more clearly understood when considered in conjunction with the accompanying drawings, in which

[24] FIG. 1 represents a cross-sectional view illustrating a method of aligning semi- conductor devices according to the prior art; [25] FIG. 2 represents cross-sectional views illustrating another method of aligning semiconductor devices according to the prior art; [26] FIGS. 3 through 17 are drawings illustrating methods of forming magnetic bodies and aligning semiconductor devices by the magnetic bodies according to one embodiment of the present invention; [27] FIGS. 18 and 19 are cross-sectional views illustrating another method of forming magnetic bodies, and a subsequent method of aligning semiconductor devices; [28] FIGS. 20 through 25 are cross-sectional views illustrating yet another method of forming magnetic bodies, and a subsequent method of aligning semiconductor devices; [29] FIGS. 26 through 28 are cross-sectional views illustrating a method of aligning semiconductor devices by magnetic bodies according to another embodiment of the present invention; [30] FIG. 29 is a cross-sectional view illustrating a method of aligning a semiconductor device to a chip support by magnetic bodies according to another embodiment of the present invention; [31] FIGS. 30 through 32 are cross-sectional views illustrating a method of aligning semiconductor devices with the aid of an external magnetic field; [32] FIGS. 33 and 34 are cross-sectional views illustrating an example of stacking plural semiconductor devices on another semiconductor device; [33] FIGS. 35 through 37 are cross-sectional views illustrating an example of electrical connection between semiconductor devices in die-to- wafer stacking; [34] FIGS. 38 through 42 are cross-sectional views illustrating a method of forming bumps; [35] FIGS. 43 through 45 are cross-sectional views illustrating another method of forming bumps; [36] FIGS. 46 through 49 are cross-sectional views illustrating the fabrication of a semiconductor structure using magnetic bodies according to another embodiment of the present invention; [37] FIGS. 50 through 52 are cross-sectional views illustrating methods of preventing melted solders from being merged during the fabrication of a semiconductor structure; [38] FIGS. 53 through 55 are cross-sectional views illustrating the fabrication of another semiconductor structure using magnetic bodies; [39] FIGS. 56 and 57 are cross-sectional views illustrating the fabrication of another semiconductor structure using magnetic bodies according to another embodiment of the present invention; [40] FIGS. 58 and 59 are cross-sectional views illustrating an application example of the present invention. Best Mode

[41] Hereinafter, method of aligning semiconductor devices according to embodiments of the present invention will be described in detail with reference to the attached drawings. It should be noted, however, that the embodiments of the present invention are provided so that this disclosure will be through and complete, and will fully convey the scope of invention to those skilled in the art. Accordingly, in the drawings, the relative size and shape of members may be exaggerated for clarity and like reference characters refer to the same members.

[42] FIGS. 3 through 17 are cross-sectional, plan and perspective views illustrating one embodiment of the present invention, which describes methods of forming magnetic bodies and aligning semiconductor devices by the magnetic bodies in die-to-wafer stacking. Referring to these drawings, one embodiment of the present invention will be explained in detail.

[43] ^;'J3Referring to FIG. 3, a film of magnetic material 110 is formed on a wafer 100 having first semiconductor devices 102. A magnetic material generally means a ferromagnetic material. Metals such as Fe, Ni and Co which can be easily magnetized correspond to magnetic materials. For the film of magnetic material 110, besides the above metals, an alloy containing one or more of the above metals with Al or Mn can be used. To obtain a high magnetic force, the film of magnetic material 110 can be formed of an alloy of a rare earth metal such as Nd or Sm. Ceramic materials such as ferrite can be used also for the film of magnetic film 110. Examples of a method to form the film of magnetic film 1 10 include sputtering, chemical vapor deposition (CVD), plating, laser ablation or the like. For a glue layer to enhance the adhesion of the film of magnetic material 110 to the wafer 100 or for a diffusion barrier layer of magnetic material into the wafer 100, a layer of Ti, TiN, Ta, TaN or the like can be deposited prior to the formation of the film of magnetic material 110. In forming the film of magnetic material 1 10 by plating, a seed layer such as Cu or Ni is formed prior to a plating process. Another method to form the film of magnetic material 110 is to use magnetic powder dispersed in a resin such as polyimide or benzocyclobutene (BCB). Here, the resin containing magnetic powder is spread on the wafer 100 by a method such as spin coating, and next the resin is cured.

[44] Next, as shown in FIG. 4, at least a first magnetic body 110a is formed on each of the first semiconductor devices 102 by patterning the film of magnetic material 110 using lithography and etching processes. As shown in FIG. 5, magnetic bodies can be in a shape of disk 1 10b, ring 1 10c, rod 1 lOd or the like when seen from a plan view. The magnetic force induced by the magnetic bodies 1 10a is proportional to the size of the magnetic bodies 110a. Especially, as the area of the magnetic bodies 110a seen from a plan view becomes larger the magnetic force increases, but the aligning accuracy by the magnetic bodies 1 10a decreases. Therefore, it is preferred that the size of the magnetic bodies 1 10a is determined according to a required aligning accuracy. The shape, number and size of the magnetic bodies 110a can be modified in variety by those skilled in the art, and therefore the detailed description thereof will be omitted.

[45] The position of the first magnetic bodies 110a can be either within the area of the first semiconductor devices 102 (inside or upper side of the boundary denoted as dashed lines in FIG. 4) or out of the device area as shown in FIG. 6 in case that enough spaces between first semiconductor devices 104 are available. When the first magnetic bodies 1 10a are formed out of the device area, it is preferred that the magnetic bodies 110a are not positioned on portions 90 of the wafer 100 to be sacrificed in the course of die separation process such as sawing or the like. In that case, after the separation of dies, the first magnetic bodies 110a are still on dies although positioned out of the area of the first semiconductor device 104.

[46] Referring to FIG. 7, a protecting layer 120 is formed around the first magnetic bodies 1 10a. The protecting layer 120 is necessary especially when an easily oxidized material such as NdFeB forms the first magnetic bodies 1 10a. The protecting layer 120 is formed of an inorganic insulating material such as silicon oxide or silicon nitride, or of an organic insulating material such as epoxy or benzocyclobutene. After the formation of the protecting layer 120 by depositing an inorganic material using CVD, a planarization process such as chemical mechanical polishing (CMP) can be performed to reduce the step height resulted from the first magnetic bodies 110a so as to facilitate following processes.

[47] FIGS. 8 through 10 show a method of forming magnetic bodies by a damascene process. Referring to FIG. 8, engraved structures 92 such as trenches which define magnetic body regions are formed on the first semiconductor devices 102. Next, as shown in FIG 9, a film of magnetic material 112 is formed in the engraved structures 92 and on the semiconductor devices 102. Here, for a glue layer to enhance the adhesion of the film of magnetic material 112 to the wafer 100, or for a diffusion barrier, a layer of Ti, TiN, Ta, TaN or the like can be deposited prior to the formation of the film of magnetic material 112. Thereafter, a portion of the film of magnetic material 112 outside of the engraved structures 92 is removed by chemical mechanical polishing or etch back. In this manner, as shown in FIG. 10, first magnetic bodies 1 12a are formed in the engraved structures 92. Here, to protect the first magnetic bodies 112a, a protecting layer can be formed further on the first magnetic bodies 112a and on the first semiconductor devices 102.

[48] FIGS. 11 and 12 illustrate another method of forming magnetic bodies. First, as shown in FIG. 1 1, a seed layer 94 is formed on the wafer 100, and thereon a photoresist pattern 96 having openings 98 which expose portions of the seed layer 94 is formed. Here, the openings 98 define magnetic body regions. After filling the openings 98 with a magnetic material by plating, the photoresist pattern 96 and a portion of the seed layer 94 formed outside of the magnetic body regions are removed successively. Then, as shown in FIG. 12, first magnetic bodies 114a are formed on the first semiconductor devices 102.

[49] For two semiconductor devices to be stacked, at least a first magnetic body is formed on a first semiconductor device, for example the first magnetic bodies 110a on the semiconductor devices 102 in FIG. 7. Next, at least a second magnetic body is to be formed on a second semiconductor device to be aligned and stacked to the first semiconductor device 102.

[50] Referring to FIG. 13, by applying the aforementioned method to a wafer 200 having second semiconductor devices 202, at least a second magnetic body 210a is formed on each of the second semiconductor devices 202, followed by the formation of a protecting layer 220. The position of the second magnetic body 210a is such that the first magnetic body 1 10a of FIG. 7, for example, faces the second magnetic body 210a when the first semiconductor device 102 and the second semiconductor device 202 are aligned in stacking. For a method of forming second magnetic bodies, the aforementioned methods of forming first magnetic bodies can be applied identically, therefore the repeated description thereof will be excluded.

[51] After forming magnetic bodies on two semiconductor devices to be stacked, magnetic bodies on at least one semiconductor device are magnetized before aligning. Magnetization is achieved by applying an external magnetic field to magnetic bodies using a magnetizer or the like. An external magnetic field can be applied either to a whole wafer or to a die separated from a wafer.

[52] Referring to FIG. 14, in case that both magnetic bodies 110a, 210a formed on two semiconductor devices are magnetized, the magnetization of the magnetic bodies 110a, 210a is such that the facing surfaces of the first magnetic body 1 10a and the second magnetic body 210 have different magnetic polarities so as to induce an attractive force during aligning.

[53] In two semiconductor devices to be stacked, one semiconductor device is separated as a die from a wafer. In die-to-wafer stacking, it is preferred that a semiconductor device having a smaller die size is separated as a die. By doing so, during stacking, there is no space restriction in using all the good semiconductor devices of a wafer, which have passed electrical or optical tests. In this embodiment, between the first semiconductor device 102 in FIG. 7 and the second semiconductor device 202 in FIG. 13, the second semiconductor devices 202 having a smaller size are separated as dies from the wafer 200.

[54] Referring to FIGS. 15 and 16, after separating a die 250 from the wafer 200 of FIG. 13 through back grinding and sawing, the die 250 is moved close to the first semiconductor device 102 on the wafer 100 of FIG. 7 so that an attractive magnetic force (F) between the first magnetic body 110a and the second magnetic body 210a has an effect. By the attractive force (F), two magnetic bodies 110a, 210a are aligned facing each other, and the die 250 is attached to the wafer 100 as shown in FIG. 16. The position where the first and second magnetic bodies 110a, 210a are facing each other becomes automatically the position where the first semiconductor device 102 and the second semiconductor device 202 are aligned because, in designing stage, the first and second magnetic bodies 110a, 210a have been laid out so as to face each other when the first semiconductor device 102 and the second semiconductor device 202 are aligned. Here, moving the die 250 close to the wafer 100 can be achieved by an apparatus having functions of picking up a separated die, moving it mechanically and placing it in a predetermined position like pick and place equipment. Currently, it takes about 1 sec for pick and place equipment to pick up a die and place it within an error range of 30 μ m from a predetermined point.

[55] FIG. 17 is a perspective view illustrating another method of making dies 250 containing second magnetic bodies 210a and a wafer 100 containing first magnetic bodies 1 10a close to each other. First, the dies 250 are arranged in positions where the alignment and attachment of dies can be induced by magnetic forces. Next, the wafer 100 is moved close to the dies 250 in such a way that the first magnetic bodies 1 10a and the second magnetic bodies 210a can face each other. Then, by forces between the first magnetic bodies 110a and the second magnetic bodies 210a, the dies 250 are attached to the wafer 100 achieving the alignment. By applying this method of moving the wafer 100 close to the arranged dies 250, a large number of dies can be attached to a wafer achieving the alignment at one time.

[56] FIGS. 18 and 19 are cross-sectional views illustrating another method of forming magnetic bodies and a subsequent method of aligning semiconductor devices.

[57] Referring to FIG. 18, by thinning the backside of a wafer containing second semiconductor devices 202 using back grinding or chemical mechanical polishing, a thinned wafer 200' is obtained. Next, a protecting layer 222 made of an insulating material is formed on the backside of the thinned wafer 200' and at least a second magnetic body 212a is formed on the backside of each of the second semiconductor devices 202. As shown in FIG 19, a die 252 is separated from the thinned wafer 200', and moved close to the first semiconductor device 102 on the wafer 100 of FIG. 7 so that a magnetic force (F) between the first magnetic body 1 10a and the second magnetic body 212a can induce the alignment of the first and the second semiconductor devices 102, 202 and the attachment of the die 252 to the wafer 100. A magnetic body formed on the backside of a die as above example has the advantage of stacking the die without flipping.

[58] FIGS. 20 through 25 are cross-sectional views illustrating another method of forming magnetic bodies and aligning semiconductor devices. In the aforementioned methods, magnetic bodies are formed either on the tront side or backside of a wafer after the fabrication of semiconductor devices According to the present method, magnetic bodies are formed during the fabrication of senuconductor devices.

[59] FIG. 20 illustrates an example ot second magnetic bodies 213a formed during the fabrication of second semiconductor devices 202 on a wafer 200. If the second magnetic bodies 213a are formed in the wafer 200 as shown, then after backside thinning and die separation, the second magnetic bodies 213 can induce a magnetic force necessary tor aligning both in the upper and the lower directions, which can be useful in stacking semiconductor devices not only on the upper side but also beneath the lower side of a die

[60] Forming magnetic bodies during the fabrication of semiconductor devices is preferably achieved after finishing high temperature processes such as transistor formation process. Although magnetic bodies are formed during the fabrication of semiconductor devices and therefore formed in a wafer, unlike FIG 20 magnetic bodies can be exposed in the lower surface of a wafer, or can be closer to the lower surface thereof, so as to induce a larger magnetic force in the lower direction. For example, referring to FIGS. 21 and 22, after forming isolation oxide films 50, source regions 52s, 54s, drain regions 52d, 54d, gate electrodes 56 and spacers 58 which constitute transistors, an interlayer insulating film 60 is deposited thereon and planaπzed. Next, an engraved structure 70 having a shape of hole or trench is formed down to the inside of a wafer 200 passing through the interlayer insulating film 60. After the deposition of an insulating liner 80 in the engraved structure 70 and on the interlayer insulating film 60, the engraved structure 70 is filled with a magnetic material. To fill the engraved structure 70 with a magnetic material, plating ot a metallic magnetic material can be performed atter the formation ot a diffusion barrier layer and a seed layer on the insulating liner 80. Another method of tilling the engraved structure 70 is using magnetic powder After dispersing magnetic powder in a liquid material such as SOG (spin on glass) or benzocyclobutene (BCB), the liquid containing magnetic powder is spread on the water 200 to fill the engraved structure 70. Finally, the liquid is cured to have a solid form By removing the magnetic material, and also conductive films such as seed layer in case of plating, outside of the engraved structure 70 using chemical mechanical polishing or etch back, a second magnetic body 214a passing through the interlayer insulating film 60 and extending to the inside of the wafer 200 is formed as shown in FIG. 22 Further, after the formation ot transistors and magnetic bodies, proc [61] FIGS. 26 through 28 are cross-sectional views illustrating another embodiment of the present invention, which describes a method of aligning semiconductor devices by magnetic bodies in die-to-die stacking. In this embodiment, the methods of forming magnetic bodies in the aforementioned embodiment are applied identically and same reference characters refer to the same members as in the aforementioned embodiment. Therefore the repeated description thereof will be excluded.

[62] Referring to FIG. 26, a first die i50 containing a first semiconductor device 102 and at least a first magnetic body i f 0a is separated from the wafer f 00 of FIG. 7 through back grinding and sawing, and then fixed on a support (not shown). A second die 260 containing a second semiconductor device 202 and having at least a second magnetic body 210a on the upper side thereof is flipped so that the first magnetic body i 10a and the second magnetic body 2i0a can face each other. Thereafter the second die 260 is moved close to the first die 150 so that a magnetic force (F) between the first magnetic body i 10a and the second magnetic body 210a can induce the alignment of the first and the second semiconductor devices 102, 202 and the attachment of the second die 260 to the first die 150.

[63] Referring FIGS. 27 and 28, in case that a second magnetic body 212a is formed on the backside of a second die 262 as shown in FIG. 27 or a second magnetic body 214a is formed in a second die 264 and exposed to the backside thereof as shown in FIG. 28, the second die 262, 264 is moved close to the aforementioned first die 150 without flip so that a magnetic force (F) can induce the alignment of the first and the second semiconductor devices 102, 202 and the attachment of the second die 262, 264 to the first die 150. In die-to-die stacking, moving a die close to another die can be performed also by an apparatus having functions of picking up a separated die, moving it mechanically and placing it in a predetermined position like pick and place equipment.

[64] In die-to-die stacking, dies are stacked directly as described in the aforementioned embodiment. When a chip support is inserted between two stacked dies, aligning semiconductor devices on the dies and the chip support is required. Likewise, in packaging of semiconductor devices, when a die containing a semiconductor device is stacked and bonded to a chip support as in flip chip bonding, aligning the semiconductor device to the chip support is required.

[65] FIG. 29 is a cross-sectional view illustrating another embodiment of the present invention, which describes a method of aligning a semiconductor device to a chip support in die to chip support stacking. In this embodiment, the methods of forming magnetic bodies in the aforementioned embodiments are applied identically and the repeated description thereof will be excluded. Referring to FIG. 29, a die 256 containing a semiconductor device 206 and at least a second magnetic body 216a is moved close to a chip support 160 containing at least a first magnetic body i62a so that a magnetic force (F) can induce the alignment ot the senuconductor device 206 and the attachment of the die 256 to the chip support 160. The chip support 160 can be made of glass, polymer such as benzocyclobutene, ceramic such as alumina, or silicon substrate. Although not shown, metal wiring parts such as contact pads or vias are formed in the chip support 160 Although FIG 29 illustrates only a case that the second magnetic body 216a is formed in the die 256 and exposed to the back side of the die 256, the second magnetic body can be tormed also on the front side ot the die 256, similarly to FIG. 26, or on the thinned back side of the die 256, similarly to FIG. 27 In the same manner, the first magnetic body 162a can be formed either on the chip support 160 as shown, or in the chip support 160 To move the die 256 close to the chip support 160, an apparatus having functions ot picking up a separated die, moving it mechanically and placing it in a predetermined position like pick and place equipment can be used

[66] 66FIGS 30 through 32 are cross-sectional views illustrating a method of aligning semiconductor devices with the aid ot an external magnetic field In the aforementioned embodiments, an increase of magnetic force between magnetic bodies can result in faster processes of die transporting and die placing since the tolerance of position where a die can be moved close and placed is increased. As a method to increase a magnetic force between magnetic bodies, an external magnetic field can be used

[67] Referring to FIG 30, after installing a coil 290 around a wafer f 00, a current is passed through the coil 290, then even larger magnetic force (F) between a first magnetic body f 10a on the wafer 100 and a second magnetic body 210a on a die 250 is induced by adding a magnetic field originating from the coil 290

[68] When a method of applying an external magnetic field is used just before aligning semiconductor devices, it is not always necessary to magnetize the magnetic bodies 110a, 210a in advance. Referring to FIG. 31, the die 250 having the second magnetic body 210a in an un-magnetized state is first placed upon the wafer fOO containing the first magnetic bodies f f 0a also in an un-magnetized state. Thereafter, by applying a current through the coil 290, a magnetic field is induced and the magnetic bodies 110a, 210a are magnetized by the magnetic field. Then an attractive force (F) is generated between the magnetic bodies 1 fOa, 2f0a, which causes the die 250 on the water 100 to move to an aligning position

[69] While, in FIGS 30 and 31, the coil 290 which induces an external magnetic field is installed around the wafer 100, a coil 292 can be installed also around the die 250 as shown in FIG 32.

[70] Although a case of die stacking to a wafer has been taken as an example in the above to describe the application of an external magnetic field, in case of die-to-die stacking or die to chip support stacking an external magnetic field can be applied also with the same principle as above.

[71] FIGS. 33 and 34 are cross-sectional views illustrating an example of stacking plural semiconductor devices on another semiconductor device.

[72] Referring to FIG. 33, after fabricating second semiconductor devices 202 and second magnetic bodies 214a in a wafer (not shown) according to the aforementioned method, a die 264 is separated. Similarly, after fabricating third semiconductor devices 302 and third magnetic bodies 310a in another wafer (not shown) a die 350 is separated. Both the second semiconductor device 202 and the third semiconductor device 302 are to be stacked on a first semiconductor device 106 of another wafer 100. Hereinafter, the die 264 containing the second semiconductor device is referred to as second die and the die 350 containing the third semiconductor device 302 is referred to as third die. First magnetic bodies i f 6a, f fob are also formed on the wafer f 00. Here, one of the first magnetic bodies 1 16a is to interact mainly with the second magnetic body 214a formed in the second die 264, and the other of the first magnetic bodies i 16b is to interact mainly with the third magnetic body 3i0a formed in the third die 350. Thereafter, the second die 264 is moved close to the first semiconductor device 106 on the wafer 100, then by a magnetic force between the first magnetic body 116a and the second magnetic body 214a the second die 264 is attached to the wafer 100 with the alignment of the first and the second semiconductor devices 106, 202. Next, the third die 350 is moved close to the first semiconductor device i06 so that a magnetic force between the first magnetic body 1 16b and the third magnetic body 310a can induce the alignment of the first and the third semiconductor devices 106, 302 and the attachment of the third die 350 to the wafer fOO.

[73] FIG. 34 illustrates a method of stacking plural semiconductor devices on another semiconductor device in die-to-die stacking. A first die 154 containing the first semiconductor device 106 is separated from the wafer 100 of FIG. 33 and fixed on a support (not shown). The second die 264 is moved close to the first die 154, then by a magnetic force between the first magnetic body 1 16a and the second magnetic body 214a the second die 264 is attached to the first die 154 with the alignment of the first and the second semiconductor devices 106, 202. Next, the third die 350 is moved close to the first die 154 so that a magnetic force between the first magnetic body i 16b and the third magnetic body 3i0a can induce the alignment of the first and the third semiconductor devices i06, 302 and the attachment of the third 350 die. Although not shown, using the aforementioned method, plural dies can be stacked on a chip support. In stacking plural dies, an external magnetic field can be applied also to increase a magnetic force between magnetic bodies. Although only two semiconductor devices are stacked on another semiconductor device in the above examples, more than two semiconductor devices can be stacked on another semiconductor device using the same method.

[74] 74FIGS. 35 through 37 illustrate an example of electrical connection between semiconductor devices after stacking dies on a wafer by the aforementioned aligning method.

[75] Referring to FIG. 35, an insulating material 360 such as polyimide, benzocyclobutene or epoxy is spread on a wafer 100 containing first semiconductor devices i02 and first magnetic bodies 1 10a, and dies 250 containing a second semiconductor device 202 and a second magnetic body 210a are attached by the aforementioned aligning method. Then, the dies 250 are fixed firmly by curing the insulating material 360. Next, via holes 370 are formed on the upper side of the dies 250. Here, the via holes 370 are extending to landing pads 108 in the first semiconductor devices 102 passing through the second semiconductor devices 202 and the insulating material 360. Although not shown, the landing pads 108 are connected to wiring metals of the first semiconductor devices 102.

[76] Referring to FIG. 36, after depositing a layer of insulating liner (not shown) formed of silicon oxide or silicon nitride on the resultant structure, an etch back process of the layer of insulating liner is performed so that the upper side of the landing pads 180 can be exposed. Next, by filling the via holes 370 with a metal, first vias 382 surrounded by an insulating liner 380 are formed as shown.

[77] Thereafter, as shown in FIG. 37, second vias 392 surrounded by an insulating liner 390 are formed in the dies 250 extending to landing pads 208 of the second semiconductor devices 202. Finally, the first semiconductor devices 102 and the second semiconductor devices 202 are electrically connected by forming wiring metals 396 on the second semiconductor devices 202 which join the first vias 382 to the second vias 392.

[78] When a semiconductor structure is fabricated according to the aforementioned aligning method, two stacked semiconductor devices, or a semiconductor device and a chip support, can be electrically connected through interconnects formed therebetween. FIGS. 38 through 42 illustrate a method of forming bumps as an example of interconnect fabrication.

[79] Referring to FIG. 38, magnetic bodies 420 are formed on the upper side of a wafer 400 having contact pads 410 thereon. Here, the upper side should be understood as a view in the drawing, and therefore in an actual wafer it can be either the upper (or front) side or the lower (or back) side. Although not shown, the wafer 400 contains semiconductor devices, and the contact pads 410 are connected to wiring metals of the semiconductor devices. When a protecting layer 422 is formed further after forming the magnetic bodies 420, the upper side of the contact pads 4f 0 is exposed using lithography and etching processes as shown in FIG. 39. Hereinafter, examples that the protecting layer 422 is not formed will be illustrated for simplicity.

[80] Referring to FIG. 40, an UBM (Under Bump Metal) layer 430 is formed on the entire surface of the wafer 400 where the contact pads 4f0 and the magnetic bodies 420 are formed, and thereon a photoresist pattern 440 having openings 442 which expose portions of the UBM layer 430 is formed. Here, the openings 442 define bump regions. The UBM layer 430 can be made of Ti, Ta, Cr, Ni, Cu, Pd, Au or a composite thereof by a method of sputtering or plating.

[81] After forming a bump material in the openings 442 of the photoresist pattern 440 by plating, the photoresist pattern 440 and a portion of the UBM layer 430 outside the bump regions are removed successively. Then, as shown in FIG. 41, bumps 450 which are protruded with respect to the upper surface of the wafer 400 are formed. For bumps of stud type which do not require a reflow process after the formation thereof, a preferred bump material is Cu or Au. For bumps which require a shaping process through a reflow as solder bumps, a bump material can be selected from the group consisting of Pb, Sn, Cu, Ni, Ag, Bi, In or alloys thereof. As shown in FIG. 42, in case of solder bumps, a round shape of bumps 450' can be obtained by reflowing the bumps 450.

[82] FIGS. 43 through 45 are cross-sectional views illustrating another method of forming solder bumps. Referring to FIG. 43 first, a photoresist pattern 460 having openings 462 which expose contact pads 413 is formed on a wafer 400 having magnetic bodies 420 thereon. Next, the openings 462 are filled with solder paste 470 as shown in FIG. 44. Finally, as shown in FIG. 45, round shaped solder bumps 470' are formed after removing the photoresist pattern 460 and reflowing the paste 470. The present method of forming the solder bumps 470' is preferred to apply when a metal capable of wetting solder, such as Cu, constitutes the contact pads 413, or the upper surface of the contact pads 413 is coated with the metal.

[83] For the fabrication of the aforementioned bumps of stud type made of Cu or Au, another fabrication method using a ball bonder can be used. After forming a ball at the end of Cu or Au wire, the ball is bonded to a contact pad of a wafer or a die. Thereafter the wire is cut, so that a bump is formed on the contact pad.

[84] Although only a case that bumps are formed on a wafer has been described in the aforementioned examples, bumps can be formed on a package substrate such as chip support by the same method.

[85] FIGS. 46 through 49 illustrate a method of fabricating a semiconductor structure using magnetic bodies according to another embodiment of the present invention. In the present embodiment, as a joining means for a semiconductor structure, interconnects made of solder bump are used. [86] Referring to FIG. 46, after forming magnetic bodies and solder bumps on a wafer (not shown), a die 600 containing contact pads 610, interconnects 630 made of solder bump, and at least one magnetic body 620 is separated from the wafer. Although not shown, the contact pads 610 are connected to wiring metals of a semiconductor device formed on the die 600. After the die 600 is separated, the die 600 is moved close to a substrate 500 so that the interconnects 630 are alined to corresponding contact pads 510 on the substrate 500. Then, the die 600 is attracted to an aligned position by a magnetic force (F) induced by the interaction between magnetic bodies 520 formed on the substrate 500 and the magnetic bodies 620 of the die 600. Hereinafter, the magnetic bodies 520 formed on the substrate 500 are referred to as first magnetic bodies and the magnetic bodies 620 formed on the die 600 are referred to as second magnetic bodies. In case of die-to-wafer stacking the substrate 500 is a wafer, in case of die-to-die stacking the substrate 500 is a corresponding die, and in case of die to chip support stacking the substrate 500 is a chip support. Although not shown, the corresponding contact pads 510 are connected to wiring metals of a semiconductor device (not shown) formed on the substrate 500, or to wiring metals of a chip support.

[87] Referring to FIG. 47, once the interconnects 630 and the corresponding contact pads 510 are aligned by a magnetic force between the first magnetic bodies 520 and the second magnetic bodies 620, the interconnects 630 are positioned just on the corresponding contact pads 510. Next, the interconnects 630 are heated and retlowed, then melted solders wet the corresponding contact pads 510. Here, a balance of force between the magnetic force (F) and the surface tension of the melted solders can maintain a gap between the die 600 and the substrate 500. Therefore, merging of the melted solders can be avoided by preventing the die 600 and the substrate 500 from coming too much close to each other. For this force balance, before a complete melting of the interconnects 630, an external magnetic field opposite to the magnetic field induced between the first magnetic bodies 520 and the second magnetic bodies 620 can be applied to reduce the magnetic force. Another method of reducing the magnetic force is to select a magnetic material whose magnetism becomes substantially weak at the melting temperature of the interconnects 630. Finally, as shown in FIG. 48, temperature is lowered and a semiconductor structure that the die 600 and the substrate 500 are connected through the interconnects 630' is fabricated.

[88] FIG. 49 illustrates a case that interconnects 530 made of solder bump are formed on a substrate 500 having contact pads 512. A die 600 contains corresponding contact pads 612 to be joined to the interconnects 530. When the interconnects 530 are formed on the substrate 500, the mass of the die 600 becomes lighter and therefore the magnetic force (F) can move the die 600 more effectively. In this case also, after aligning the interconnects 530 and the corresponding contact pads 612, a semi- conductor structure that the die 600 and the substrate 500 are connected as in FIG. 48 can be formed through reflowing the interconnects 530.

[89] In the present embodiment, while examples of forming the interconnects 530, 630 made of solder bump directly on the contact pads 512, 610 are described, an UBM (Under Bump Metal) can be formed between the interconnects 530, 630 and the contact pads 512, 610.

[90] According to the present embodiment, as illustrated in FIG. 48, a semiconductor structure is fabricated, which comprises the substrate 500, the die 600 stacked on the substrate 500, the interconnects 630' between the substrate 500 and the die 600, and the first magnetic bodies 520 belonging to the substrate 500 which interact with the second magnetic bodies 620 belonging to the die 600 for aligning the interconnects 630'.

[91] Although only an example that the magnetic bodies 520, 620 are formed on the die 600 and substrate 500 is shown in the present embodiment, magnetic bodies can be formed also in the die 600 or substrate 500, similarly to FIG. 20 or FIG. 23.

[92] FIGS. 50 through 52 illustrate methods to prevent merging of melted solders during the aforementioned process of joining solder bumps.

[93] A substrate 500 and a die 600 in FIGS. 50 and 51 have the same structure shown in FIG. 47 except that barriers 640 against merging are formed between interconnects 630 made of solder. The barriers 640 are made of an insulating material such as silicon oxide, silicon nitride or benzocyclobutene. It is preferred that the barriers 640 are formed before forming the interconnects 630. According to the aforementioned aligning method, the die 600 is moved close to the substrate 500. Then, as shown in FIG. 50, the interconnects 630 are aligned to corresponding contact pads 510 on the substrate 500 by the interaction between first magnetic bodies 520 and second magnetic bodies 620. Thereafter, as shown in FIG. 51, by raising the temperature the interconnects 630 become melted solders 630" which wet the corresponding contact pads 510. At the same time, the die 600 can come closer to the substrate 500 by the magnetic force (F), which might cause merging of the melted solders 630" by pressing the melted solders and deforming them flat. Here, the barriers 640 prevent the melted solders 630" from being merged. Other purpose of the barriers 640 is for a role of spacers between the substrate 500 and the die 600. When the die 600 approaches the substrate 500 by the magnetic force (F), the die 600 stops approaching once the barriers 640 touch the substrate 500. Therefore, the melted solders 630" can be made to wet the contact pads 510 more reliably by the barriers 640 which stop the die 600 at a controlled gap, to which the die 600 and the substrate 500 approach each other by the magnetic force. Once wetting is done, the temperature is lowered and the connection of the die 600 and the substrate 500 is completed. The temperature can be lowered either after weakenine the maenetic force with an external maenetic field to restore a flat shape of the melted solders 630" to a round shape or with applying continuously the magnetic force.

[94] Referring to FIG. 52, first magnetic bodies 522 are formed on a substrate 500 in a way that the first magnetic bodies 522 are made protruded enough so that the first magnetic bodies 522 and second magnetic bodies 620 together can act as spacers when the two magnetic bodies 522, 620 are attached. As shown in the drawing, when the two magnetic bodies 522, 620 touch each other, further pressing of the melted solders 630" is difficult and therefore merging of the melted solders 630" can be avoided. Although only the thickness of the first magnetic bodies 522 is changed in FIG. 52, the thickness of the second magnetic bodies 620 or the thicknesses of the two magnetic bodies 522, 620 can be changed.

[95] FIGS. 53 through 55 illustrate a method of fabricating a semiconductor structure using magnetic bodies according to another embodiment of the present invention. In the present embodiment, stud type bumps made of a material other than solder are used as interconnects.

[96] Referring to FIG. 53, after forming magnetic bodies and stud type bumps made of a material other than solder on a wafer (not shown), a die 600 containing contact pads 614, interconnects 650 of stud type bump, and at least one magnetic body 620 is separated from the wafer. The material other than solder, which constitutes the interconnects 650, can be Cu or Au. Although not shown, the contact pads 614 are connected to wiring metals of a semiconductor device formed on the die 600. After the die 600 is separated, the die 600 is moved close to a substrate 500 so that the interconnects 650 are alined to corresponding contact pads 514 on the substrate 500. Then, the die 600 is attracted to an aligned position by a magnetic force (F) induced by the interaction between first magnetic bodies 520 formed on the substrate and the second magnetic bodies 620 of the die 600. Here, in case of die-to-wafer stacking the substrate 500 is a wafer, in case of die-to-die stacking the substrate 500 is a corresponding die, and in case of die to chip support stacking the substrate 500 is a chip support. Although not shown, the corresponding contact pads 514 are connected to wiring metals of a semiconductor device (not shown) formed on the substrate 500, or to wiring metals of a chip support.

[97] Referring to FIG. 54, the interconnects 650 and the corresponding contact pads 514 are aligned and contacting each other by a magnetic force between the first magnetic bodies 520 and the second magnetic bodies 620. For the reliable joining of the interconnects 650 to the corresponding contact pads 514, a gap between the substrate 500 and the die 600 can be filled with an adhesive material (not shown) such as anisotropic conductive adhesive. Another method of reliable joining is to apply heat and pressure to the die 600 maintaining the alignment, which can result in a metal bonding by diffusion of atoms at the interface between the interconnects 650 and the corresponding contact pads 514. Pressure can be applied by pressing the die 600 mechanically. Another method of applying pressure to the interface is using an external magnetic field which is constructive to the magnetic field induced by the first and second magnetic bodies 520, 620. The constructive external magnetic field results in a larger attractive force between the substrate 500 and the die 600. Consequently higher pressure is applied to the interface between the interconnects 650 and the corresponding contact pads 514. The temperature necessary for the metal bonding is generally 350~400 °C which can be lowered by applying ultrasonic waves.

[98] FIG. 55 illustrates a case that interconnects 550 made of a material other than solder are formed on a substrate 500 having contact pads 516. A die 600 contains corresponding contact pads 616 to be joined to the interconnects 550. When the interconnects 550 are formed on the substrate 500, the mass of the die 600 becomes lighter as in the above case of solder bumps, and the magnetic force (F) can move the die 600 more effectively.

[99] In the present embodiment, while an example of forming the interconnects 650 made of a material other than solder directly on the contact pads 614 are illustrated, an UBM can be formed between the interconnects 650 and the contact pads 614.

[100] According to the present embodiment, as illustrated in FIG. 54, a semiconductor structure is fabricated, which comprises the substrate 500, the die 600 stacked on the substrate 500, the interconnects 650 between the substrate 500 and the die 600, and the first magnetic bodies 520 belonging to the substrate 500 which interact with the second magnetic bodies 620 belonging to the die 600 for aligning the interconnects 650.

[101] Although only an example that the magnetic bodies 520, 620 are formed on the die 600 and substrate 500 is shown in the present embodiment, magnetic bodies can be formed also in the die 600 or substrate 500, similarly to FIG. 20 or FIG. 23.

[102] FIGS. 56 and 57 illustrate a method of fabricating a semiconductor structure using magnetic bodies according to another embodiment of the present invention.

[103] In the present embodiment, a substrate and a die are connected through the joining of bonding pads. While the disposition and material of bonding pads may be same as those of the contact pads described in the aforementioned embodiments, bonding pads in this embodiment are different from the contact pads in that connecting a substrate and a die is achieved by a direct bonding between bonding pads formed on the substrate and the die respectively without the assistance of other medium such as bumps.

[104] Referring to FIG. 56, first bonding pads 5 iS are formed on a substrate 500, made protαided with respect to the upper surface of the substrate 500. Although only the first bonding pads 518 on the substrate 500 are protruded in the drawing, second bonding pads 618 formed on a die 600 can be protruded too. Although not shown, the second bonding pads 618 are connected to wiring metals of a semiconductor device (not shown) formed on the die 600. The first and second bonding pads 518, 6f 8 are made of Cu or Au, or the surfaces thereof are coated with Cu or Au, so that a metal bonding between the first and second bonding pads 518, 618 can be facilitated. As shown in FIG. 56, first magnetic bodies 524 on the substrate 500 and second magnetic bodies 624 on the die 600 are fabricated in a way that the magnetic bodies 524, 624 are less protαided than the first and the second bonding pads 518, 618 lest the magnetic bodies 524, 624 obstruct the joining between the first and the second bonding pads 518, 618. Next, according to the same method as the aforementioned embodiments, the die 600 is moved close to the substrate 500 so that the die 600 is attracted to an aligned position by a magnetic force (F) induced by the interaction between the first magnetic bodies 524 and the second magnetic bodies 624. Here, in case of die-to-wafer stacking the substrate 500 is a wafer, in case of die-to-die stacking the substrate 500 is a corresponding die, and in case of die to chip support stacking the substrate 500 is a chip support. Although not shown, the first bonding pads 518 are connected to wiring metals of a semiconductor device (not shown) formed on the substrate 500, or to wiring metals of a chip support.

[105] Thereafter, as shown in FIG. 57, the second bonding pads 618 formed on the die 600 and the first bonding pads 518 formed on the substrate 500 are aligned and contacting each other. Here, heat and pressure are applied to the die 600, then diffusion of atoms takes place at the interface between the first and the second boding pads 518, 618, which results in a metal bonding between the bonding pads 518, 618. Pressure can be applied by pressing the die 600 mechanically. Another method of applying pressure to the interface is using an external magnetic field which is constαictive to the magnetic field induced by the first and second magnetic bodies 524, 624. The constαictive external magnetic field results in a larger attractive force between the substrate 500 and the die 600. Consequently higher pressure is applied to the interface between the first and second bonding pads 518, 618. The temperature necessary for the metal bonding is generally 350~400 °C , which can be lowered by applying ultrasonic waves.

[106] According to the present embodiment, as illustrated in FIG. 57, a semiconductor stαicture is fabricated, which comprises the substrate 500 having the first bonding pads 518 thereon, the die 600 stacked on the substrate 500 and having the second bonding pads 618 joined to the first bonding pads 518, and the first magnetic bodies 524 belonging to the substrate 500 which interact with the second magnetic bodies 620 belonging to the die 600 for aligning the first bonding pads 518 and the second bonding pads 618. [107] Although only an example that the magnetic bodies 520, 620 are formed on the die 600 and substrate 500 is shown in the present embodiment, magnetic bodies can be formed also in the die 600 or substrate 500, similarly to FIG. 20 or FIG. 23.

[108] FIGS. 58 and 59 illustrate an example of semiconductor structure where the aforementioned embodiments are applied together. Referring to FIG. 58, substrate contact pads 12 fonned on a substrate 10 and first interconnects of stud bump 26 formed on the lower surface of a first die 20 are joined after having been aligned by the interaction between magnetic bodies 14 of the substrate f 0 and magnetic bodies 24 of the first die 20. The magnetic bodies 24 of the first die 20 have been formed during the fabrication process of a semiconductor device (not shown) so that the magnetic bodies 24 extend to the inside of the first die 20, which can induce a magnetic force for aligning not only in the lower direction of the first die 20 but also in the upper direction thereof. After connecting the first die 20 to the substrate 10, second die 30 having second interconnects of solder bump 36 and barriers against melt merging 38 is stacked on the first die 20. Here, the second interconnects 36 and contact pads 22 of the first die 20 are aligned by a magnetic force between the magnetic bodies 24 of the first die 20 and bottom magnetic bodies 34b of the second die 30. Next, third die 40 having third interconnects of solder bump 46 is stacked on the second die 30. Here, the third interconnects 46 and contact pads 32 of the second die 30 are aligned by a magnetic force between upper magnetic bodies 34t of the second die 30 and magnetic bodies 44 of the third die 40. The magnetic bodies 44 of the third die 40 are made protruded to act as spacers. The aligned dies 20, 30, 40 keep attaching to each other by a magnetic force induced by the magnetic bodies 24, 34b, 34t, 44. Next, heat is applied to reflow the second and the third interconnects of solder bump 36, 46, then as shown in FIG. 59, the contact pads 22 of the first die 20 and the contact pads 32 of the second die 30 are wetted with solders 36', 46', and joining the dies 20, 30, 40 is achieved.

[109] As described in the aforementioned embodiments, the present invention reduces the time needed for aligning semiconductor devices in various die stacking processes by achieving the alignment with a magnetic force between magnetic bodies belonging respectively to the two members to be stacked. After aligning is achieved, an aligned state is maintained also by the magnetic force, which enables fabricating various semiconductor stαictures using die stacking.

[i 10] f fOWhile the principles of the present invention have been described with reference to particular embodiments illustrated herein, it will be understood by those skilled in the art that various changes in form and in detail may be made thereto without departing from the spirit and scope of the invention, as covered by the following claims.

Claims

[I] A method of aligning a first semiconductor device on a wafer and a second semiconductor device on a die in die-to-wafer stacking, the method being characterized in that the first semiconductor device on the wafer and the second semiconductor device on the die are aligned by a magnetic force between at least a first magnetic body belonging to the wafer and at least a second magnetic body belonging to the die.

[2] The method of claim 1, wherein the magnetic force between the first magnetic body and the second magnetic body is an attractive force.

[3] The method of claim 2, further comprising attaching the die to the wafer by the attractive force after aligning the first semiconductor device and the second semiconductor device.

[4] The method of claim 1, wherein the first magnetic body is formed on the wafer.

[5] The method of claim 1, wherein the first magnetic body is formed in the wafer.

[6] The method of claim 1, wherein the second magnetic body is formed on the die.

[7] The method of claim 1, wherein the second magnetic body is fonned in the die.

[8] The method of claim 1, wherein the first magnetic body and the second magnetic body are made of an alloy containing at least one of the metal selected from the group of Fe, Co, Ni, Mn, Nd and Sm.

[9] The method of claim 1, wherein at least one of the first magnetic body and the second magnetic body is magnetized.

[10] The method of claim 1, further comprising, prior to aligning the first semiconductor device and the second semiconductor device, making the die and the wafer close to each other by a mechanical transfer within a distance where the magnetic force is effective in aligning the first semiconductor device and the second semiconductor device.

[I I] The method of claim 1, wherein an external magnetic field is applied additionally in the course of aligning the first semiconductor device and the second semiconductor device so as to increase the magnetic force.

[12] A method of aligning a first semiconductor device on a first die and a second semiconductor device on a second die in die-to-die stacking, the method being characterized in that the first semiconductor device on the first die and the second semiconductor device on the second die are aliened by a magnetic force between at least a first magnetic body belonging to the first die and at least a second magnetic body belonging to the second die.

[13] The method of claim 12, wherein the magnetic force between the first magnetic body and the second magnetic body is an attractive force.

[14] The method of claim 13, further comprising attaching the first die to the second die by the attractive force after aligning the first semiconductor device and the second semiconductor device.

[i5] The method of claim 12, wherein the first magnetic body is formed on the first die.

[16] The method of claim 12, wherein the first magnetic body is formed in the first die.

[i7] The method of claim 12, wherein the second magnetic body is fonned on the second die.

[18] The method of claim 12, wherein the second magnetic body is fonned in the second die.

[i9] The method of claim 12, wherein the first magnetic body and the second magnetic body are made of an alloy containing at least one of the metal selected from the group of Fe, Co, Ni, Mn, Nd and Sm.

[20] The method of claim 12, wherein at least one of the first magnetic body and the second magnetic body is magnetized.

[21] The method of claim 12, further comprising, prior to aligning the first semiconductor device and the second semiconductor device, making the first die and the second die close to each other by a mechanical transfer within a distance where the magnetic force is effective in aligning the first semiconductor device and the second semiconductor device.

[22] The method of claim 12, wherein an external magnetic field is applied additionally in the course of aligning the first semiconductor device and the second semiconductor device so as to increase the magnetic force.

[23] A method of aligning a semiconductor device on a die to a chip support in die to chip support stacking, the method being characterized in that the semiconductor device on the die is aligned to the chip support by a magnetic force between at least a first magnetic body belonging to the chip support and at least a second magnetic body belonging to the die.

[24] The method of claim 23, wherein the magnetic force between the first magnetic body and the second magnetic body is an attractive force.

[25] The method of claim 24, further comprising attaching the die to the chip support by the attractive force after aligning the semiconductor device to the chip support.

[26] The method of claim 23, wherein the first magnetic body is formed on the chip support.

[27] The method of claim 23, wherein the first magnetic body is formed in the chip support.

[28] The method of claim 23, wherein the second magnetic body is fonned on the die.

[29] The method of claim 23, wherein the second magnetic body is fonned in the die.

[30] The method of claim 23, wherein the first magnetic body and the second magnetic body are made of an alloy containing at least one of the metal selected from the group of Fe, Co, Ni, Mn, Nd and Sm.

[31 ] The method of claim 23, wherein at least one of the first magnetic body and the second magnetic body is magnetized.

[32] The method of claim 23, further comprising, prior to aligning the semiconductor device to the chip support, making the die and the chip support close to each other by a mechanical transfer within a distance where the magnetic force is effective in aligning the semiconductor device to the chip support.

[33] The method of claim 23, wherein an external magnetic field is applied additionally in the course of aligning the semiconductor device to the chip support so as to increase the magnetic force.

[34] A semiconductor structure, comprising: a substrate; a die stacked on the substrate; a plurality of interconnects between the substrate and the die; and at least a first magnetic body belonging to the substrate which interacts with at least a second magnetic body belonging to the die for aligning the interconnects.

[35] The semiconductor structure of claim 34, wherein the substrate is a wafer where at least a semiconductor device is fonned.

[36] The semiconductor structure of claim 34, wherein the substrate is a die where at least a semiconductor device is fonned.

[37] The semiconductor structure of claim 34, wherein the die contains at least a semiconductor device.

[38] The semiconductor structure of claim 34, wherein the substrate is a chip support.

[39] The semiconductor structure of claim 34, wherein the interconnects comprise solder bumps.

[40] The semiconductor structure of claim 39, wherein the solder is selected from the group consisting of Pb, Sn, Cu, Ni, Ag, Bi, In or alloys thereof. [41] The semiconductor structure of claim 34, wherein the interconnects comprise bumps made of a material other than solder. [42] The semiconductor structure of claim 41, wherein the material other than solder is Cu or Au. [43] The method of claim 34, wherein the first magnetic body is formed on the substrate. [44] The method of claim 34, wherein the first magnetic body is formed in the substrate. [45] The method of claim 34, wherein the second magnetic body is fonned on the die. [46] The method of claim 34, wherein the second magnetic body is fonned in the die. [47] A semiconductor structure, comprising: a substrate having first bonding pads thereon; a die stacked on the substrate and having second bonding pads joined to the first bonding pads; and at least a first magnetic body belonging to the substrate which interacts with at least a second magnetic body belonging to the die for aligning the first bonding pads and the second bonding pads. [48] The semiconductor structure of claim 47, wherein the substrate is a wafer where at least a semiconductor device is fonned. [49] The semiconductor structure of claim 47, wherein the substrate is a die where at least a semiconductor device is fonned. [50] The semiconductor structure of claim 47, wherein the die contains at least a semiconductor device. [51] The semiconductor structure of claim 47, wherein the substrate is a chip support. [52] The semiconductor structure of claim 47, wherein the first bonding pads and the second bonding pads are made of Cu or Au. [53] The method of claim 47, wherein the first magnetic body is formed on the substrate. [54] The method of claim 47, wherein the first magnetic body is formed in the substrate. [55] The method of claim 47, wherein the second magnetic body is fonned on the die. [56] The method of claim 47, wherein the second magnetic body is fonned in the die.