JP2010129684A - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
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Abstract
【解決手段】 電極パッド12に対応した位置で半導体基板11を貫通する貫通孔2を形成する。次に、貫通孔2を含む半導体基板11の裏面上に絶縁膜1を形成する。次に、少なくとも貫通孔開口部の絶縁膜1の表面に金属もしくは無機絶縁膜から密着安定化層3を形成する。
密着安定化層3の上に、ボトムエッチングのマスクとなるレジスト層4を形成する。次に、ボトムエッチングを行い、電極パッド12を露出させる。次に、レジスト層4を剥離して、ボトムエッチング後であっても凹凸のない絶縁膜1を得る。その後、低温プロセスで、バリア層5、シード層6、導電層7を形成して、パターニングを行い、密着安定化層3を有する貫通電極8付半導体装置を作る。
【選択図】 図1
Description
この特許文献1には、図16、図17に示すように、貫通孔開口部にオーバーハング部18が出来るように、補強用絶縁膜16を形成する方法と、図18、図19に示すように、ハードマスク17で庇を作り、貫通孔開口部に庇を作って、これをマスクとしてボトムエッチングを行い、電極パッド12を露出させる方法が開示されている。
半導体基板の表面に形成された電極パッドに対応する位置の、前記半導体基板の表面に対して反対側の裏面に開口部をもつ、前記半導体基板を貫通する貫通孔を形成し、前記電極パッドを前記貫通孔の底部に露出させる工程と、
前記貫通孔の底部及び貫通孔の側壁に絶縁膜を形成する工程と、
少なくとも前記貫通孔の開口部の前記絶縁膜表面に密着安定化層を形成する工程と、
前記密着安定化層の表面にレジスト層を形成する工程と、
前記レジスト層をマスクとして前記貫通孔底部の前記絶縁膜をエッチングし、前記貫通孔底部に前記電極パッドを露出させる工程と、
前記レジスト層を剥離し、前記密着安定化層を露出させる工程と、
前記貫通孔の底部及び貫通孔の側壁に導電層を形成し、前記導電層と電極パッドを接触させる工程とを有することを特徴とする。
よって、半導体装置の歩留り向上及び信頼性向上を実現することができる。
バリア層5は、例えばチタン、クロム、タングステン、チタンタングステン(TiW)、チタンナイトライド(TiN)、もしくはタンタルナイトライド(TaN)層等の金属から成る。
次に、本発明の第2の実施形態をについて説明する。第2の実施形態は、密着安定化層3を無機絶縁膜によって形成するものである。
実施例2は密着安定化層3を無機絶縁物で形成した場合である。
また、無機絶縁物で形成した場合は、必要により、表面にそのまま残すこともできる。
2 貫通孔
3 密着安定化層
4 レジスト層
5 バリア層
6 シード層
7 メッキ層
8 貫通電極
9 レジスト層残渣
10 絶縁膜
11 半導体基板
12 電極パッド
13 層間絶縁膜
14 樹脂層
15 支持体
16 補強用絶縁膜
17 ハードマスク
18 オーバーハング部
111 半導体基板の表面
112 半導体基板の裏面
113 開口部の縁
Claims (4)
- 半導体基板の表面に電極パッド及び半導体素子が形成された半導体装置の製造方法であって、
半導体基板の表面に形成された電極パッドに対応する位置の、前記半導体基板の表面に対して反対側の裏面に開口部をもつ、前記半導体基板を貫通する貫通孔を形成し、前記電極パッドを前記貫通孔の底部に露出させる工程と、
前記貫通孔の底部及び貫通孔の側壁に絶縁膜を形成する工程と、
少なくとも前記貫通孔の開口部の前記絶縁膜表面に密着安定化層を形成する工程と、
前記密着安定化層の表面にレジスト層を形成する工程と、
前記レジスト層をマスクとして前記貫通孔底部の前記絶縁膜をエッチングし、前記貫通孔底部に前記電極パッドを露出させる工程と、
前記レジスト層を剥離し、前記密着安定化層を露出させる工程と、
前記貫通孔の底部及び貫通孔の側壁に導電層を形成し、前記導電層と電極パッドを接触させる工程とを有することを特徴とする半導体装置の製造方法。 - 半導体基板表面に電極パッドが形成され、前記電極パッドに対応する位置の前記半導体基板の裏面に開口部をもち、前記半導体基板を貫通する貫通孔を有する半導体装置において、少なくとも前記貫通孔の側壁に絶縁膜が形成され、前記絶縁膜上であって、少なくとも前記貫通孔側壁の開口部に密着安定化層を有し、前記密着安定化層を含む貫通孔側壁及び貫通孔底部には、導電層を有し、前記電極パッドと前記導電層が接触していることを特徴とする半導体装置。
- 前記密着安定化層は、金属または無機絶縁物よりなることを特徴とする請求項2記載の半導体装置。
- 密着安定化層は、その厚みが0.01μmから0.1μmであることを特徴とする請求項2または3記載の半導体装置。
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JP2008301210A JP5596919B2 (ja) | 2008-11-26 | 2008-11-26 | 半導体装置の製造方法 |
US12/620,660 US8440565B2 (en) | 2008-11-26 | 2009-11-18 | Semiconductor apparatus manufacturing method and semiconductor apparatus |
CN2009102259310A CN101740490B (zh) | 2008-11-26 | 2009-11-23 | 半导体装置制造方法和半导体装置 |
CN201210427775.8A CN102931154B (zh) | 2008-11-26 | 2009-11-23 | 半导体装置 |
US13/861,598 US20130228931A1 (en) | 2008-11-26 | 2013-04-12 | Semiconductor apparatus manufacturing method and semiconductor apparatus |
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JP5424675B2 (ja) * | 2008-03-18 | 2014-02-26 | キヤノン株式会社 | 半導体装置の製造方法及び半導体装置 |
JP5455538B2 (ja) * | 2008-10-21 | 2014-03-26 | キヤノン株式会社 | 半導体装置及びその製造方法 |
TWI546925B (zh) * | 2010-02-09 | 2016-08-21 | 精材科技股份有限公司 | 晶片封裝體及其形成方法 |
JP5352534B2 (ja) * | 2010-05-31 | 2013-11-27 | パナソニック株式会社 | 半導体装置及びその製造方法 |
JP2012216812A (ja) * | 2011-03-31 | 2012-11-08 | Elpida Memory Inc | 半導体装置及びその製造方法 |
US9859761B2 (en) | 2013-02-12 | 2018-01-02 | Asmo Co., Ltd. | Rotor and motor |
US9466554B2 (en) * | 2014-02-13 | 2016-10-11 | Qualcomm Incorporated | Integrated device comprising via with side barrier layer traversing encapsulation layer |
CN106328579B (zh) * | 2015-06-24 | 2019-09-27 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法 |
EP3460835B1 (en) * | 2017-09-20 | 2020-04-01 | ams AG | Method for manufacturing a semiconductor device and semiconductor device |
US20190096866A1 (en) * | 2017-09-26 | 2019-03-28 | Powertech Technology Inc. | Semiconductor package and manufacturing method thereof |
US10741477B2 (en) * | 2018-03-23 | 2020-08-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices and methods of forming the same |
US11289370B2 (en) | 2020-03-02 | 2022-03-29 | Nanya Technology Corporation | Liner for through-silicon via |
KR20220111758A (ko) * | 2021-02-01 | 2022-08-10 | 삼성전자주식회사 | 반도체 장치 및 그의 제조 방법 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6232609A (ja) * | 1985-08-06 | 1987-02-12 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JP2005019522A (ja) * | 2003-06-24 | 2005-01-20 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
JP2006108328A (ja) * | 2004-10-04 | 2006-04-20 | Sharp Corp | 半導体装置およびその製造方法 |
JP2007053149A (ja) * | 2005-08-16 | 2007-03-01 | Renesas Technology Corp | 半導体ウエハ及びその製造方法 |
JP2007305960A (ja) * | 2006-04-14 | 2007-11-22 | Sharp Corp | 半導体装置およびその製造方法 |
JP2008091628A (ja) * | 2006-10-02 | 2008-04-17 | Seiko Epson Corp | 半導体装置、半導体装置の製造方法、回路基板および電子機器 |
JP2008205000A (ja) * | 2007-02-16 | 2008-09-04 | Fujitsu Ltd | 化合物半導体装置の製造方法 |
JP2008545251A (ja) * | 2005-06-28 | 2008-12-11 | インテル・コーポレーション | 応力緩衝カラーを備えるシリコン貫通ビアを形成する方法およびその装置 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2604939C3 (de) * | 1976-02-09 | 1978-07-27 | Ibm Deutschland Gmbh, 7000 Stuttgart | Verfahren zum Herstellen von wenigstens einem Durchgangsloch insbesondere einer Düse für Tintenstrahldrucker |
US5929526A (en) * | 1997-06-05 | 1999-07-27 | Micron Technology, Inc. | Removal of metal cusp for improved contact fill |
US6451705B1 (en) * | 2000-08-31 | 2002-09-17 | Micron Technology, Inc. | Self-aligned PECVD etch mask |
US6624066B2 (en) * | 2001-02-14 | 2003-09-23 | Texas Instruments Incorporated | Reliable interconnects with low via/contact resistance |
JP3967239B2 (ja) * | 2001-09-20 | 2007-08-29 | 株式会社フジクラ | 充填金属部付き部材の製造方法及び充填金属部付き部材 |
JP2003289073A (ja) | 2002-01-22 | 2003-10-10 | Canon Inc | 半導体装置および半導体装置の製造方法 |
US6790775B2 (en) * | 2002-10-31 | 2004-09-14 | Hewlett-Packard Development Company, L.P. | Method of forming a through-substrate interconnect |
JP4343044B2 (ja) * | 2004-06-30 | 2009-10-14 | 新光電気工業株式会社 | インターポーザ及びその製造方法並びに半導体装置 |
JP4376715B2 (ja) * | 2004-07-16 | 2009-12-02 | 三洋電機株式会社 | 半導体装置の製造方法 |
JP4873517B2 (ja) * | 2004-10-28 | 2012-02-08 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置及びその製造方法 |
US7271482B2 (en) * | 2004-12-30 | 2007-09-18 | Micron Technology, Inc. | Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods |
US7892972B2 (en) * | 2006-02-03 | 2011-02-22 | Micron Technology, Inc. | Methods for fabricating and filling conductive vias and conductive vias so formed |
JP2007311771A (ja) * | 2006-04-21 | 2007-11-29 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
US7863189B2 (en) * | 2007-01-05 | 2011-01-04 | International Business Machines Corporation | Methods for fabricating silicon carriers with conductive through-vias with low stress and low defect density |
US8034702B2 (en) * | 2007-08-16 | 2011-10-11 | Micron Technology, Inc. | Methods of forming through substrate interconnects |
JP5656341B2 (ja) * | 2007-10-29 | 2015-01-21 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置およびその製造方法 |
US7691747B2 (en) * | 2007-11-29 | 2010-04-06 | STATS ChipPAC, Ltd | Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures |
US20110042803A1 (en) * | 2009-08-24 | 2011-02-24 | Chen-Fu Chu | Method For Fabricating A Through Interconnect On A Semiconductor Substrate |
-
2008
- 2008-11-26 JP JP2008301210A patent/JP5596919B2/ja not_active Expired - Fee Related
-
2009
- 2009-11-18 US US12/620,660 patent/US8440565B2/en not_active Expired - Fee Related
- 2009-11-23 CN CN2009102259310A patent/CN101740490B/zh not_active Expired - Fee Related
- 2009-11-23 CN CN201210427775.8A patent/CN102931154B/zh not_active Expired - Fee Related
-
2013
- 2013-04-12 US US13/861,598 patent/US20130228931A1/en not_active Abandoned
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6232609A (ja) * | 1985-08-06 | 1987-02-12 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JP2005019522A (ja) * | 2003-06-24 | 2005-01-20 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
JP2006108328A (ja) * | 2004-10-04 | 2006-04-20 | Sharp Corp | 半導体装置およびその製造方法 |
JP2008545251A (ja) * | 2005-06-28 | 2008-12-11 | インテル・コーポレーション | 応力緩衝カラーを備えるシリコン貫通ビアを形成する方法およびその装置 |
JP2007053149A (ja) * | 2005-08-16 | 2007-03-01 | Renesas Technology Corp | 半導体ウエハ及びその製造方法 |
JP2007305960A (ja) * | 2006-04-14 | 2007-11-22 | Sharp Corp | 半導体装置およびその製造方法 |
JP2008091628A (ja) * | 2006-10-02 | 2008-04-17 | Seiko Epson Corp | 半導体装置、半導体装置の製造方法、回路基板および電子機器 |
JP2008205000A (ja) * | 2007-02-16 | 2008-09-04 | Fujitsu Ltd | 化合物半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN102931154A (zh) | 2013-02-13 |
US8440565B2 (en) | 2013-05-14 |
US20100127403A1 (en) | 2010-05-27 |
CN101740490B (zh) | 2013-06-05 |
CN102931154B (zh) | 2015-06-24 |
JP5596919B2 (ja) | 2014-09-24 |
US20130228931A1 (en) | 2013-09-05 |
CN101740490A (zh) | 2010-06-16 |
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