JP2008545251A - 応力緩衝カラーを備えるシリコン貫通ビアを形成する方法およびその装置 - Google Patents
応力緩衝カラーを備えるシリコン貫通ビアを形成する方法およびその装置 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/4763—Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Abstract
Description
Claims (32)
- 第1の材料からなる基板中にビアを形成する段階と、
前記ビア中に緩衝材料層を堆積する段階と、
前記ビア内の前記緩衝層上に第2の材料を堆積する段階と、を含み、
前記緩衝層は、前記第1および第2の材料間における熱拡張の不一致による応力を吸収することができる、
ことを特徴とする方法。 - 前記第1の材料はシリコンを含み、前記第2の材料は銅を含むことを特徴とする請求項1記載の方法。
- 前記緩衝材料の熱膨脹係数(CTE)は、銅のCTEとほぼ等しいことを特徴とする請求項2記載の方法。
- 前記緩衝材料のCTEは、シリコンのCTEと銅のCTEとの平均にほぼ等しいことを特徴とする請求項2記載の方法。
- 前記緩衝材料は、シリコンおよび銅と比較して比較的柔軟性のある材料を含むことを特徴とする請求項2記載の方法。
- 前記緩衝材料は、シリコン、アクリル酸塩、ポリイミド、ベンゾシクロブテン(BCB)、パリレン、フッ化炭化水素、ポリオレフィン、ポリエステル、および、エポキシ樹脂を含むグループから選択された材料を含むことを特徴とする請求項1記載の方法。
- 前記基板は、シリコン・ウエハを含み、前記シリコン・ウエハは、正面側および裏面側に形成された回路類を有し、ここで、ビアを形成する段階は、前記ウエハの裏面からビアを形成する段階を含み、前記ビアは、前記ウエハの正面側に近接する導体へ伸びることを特徴とする請求項1記載の方法。
- 緩衝材料層を堆積する段階は、
前記ビアを充填するために前記緩衝材料層を堆積する段階と、
前記ビアの底部に近接するところまで伸びるホールを前記緩衝材料内に形成する段階と、
を含むことを特徴とする請求項1記載の方法。 - 前記ホールは、レーザ融除、エッチング、リソグラフィ、および、研磨から成るグループから選択されたプロセスを使用して形成されることを特徴とする請求項8記載の方法。
- 前記緩衝材料層は、スピン・コーティング・プロセスを使用して堆積されることを特徴とする請求項8記載の方法。
- 前記緩衝材料層を堆積する段階は、
前記緩衝材料のコンフォーマル層を前記ビア中に堆積する段階と、
前記ビアの底部から前記緩衝層の一部を取り除く段階と、
を含むこと特徴とする請求項1記載の方法。 - 前記緩衝材料層は、化学蒸着法(CVD)のプロセスを使用して堆積されることを特徴とする請求項11記載の方法。
- 前記緩衝層の堆積に先立って、絶縁層およびパッシベーション層の少なくとも1つを前記ビア中に堆積する段階をさらに含むことを特徴とする請求項1記載の方法。
- 前記ビアの底部から前記少なくとも1つの層の一部を取り除く段階をさらに含むことを特徴とする請求項13記載の方法。
- 前記第2の材料の堆積に先立って、シード層および障壁層の少なくとも1つを前記緩衝材料上に堆積する段階さらに含むことを特徴とする請求項1記載の方法。
- 第1の熱膨脹係数(CTE)を有する第1の材料からなる基板中にビアを形成する段階と、
前記ビア中に第2のCTEを有する第2の材料層を堆積する段階と、
前記第2の材料層上に第3の材料を前記ビア内に堆積する段階であって、前記第3の材料は、第3のCTEを有する、段階と、を含み、
前記第2のCTEは、前記第1のCTEと第3のCTEとの間の範囲にある、
ことを特徴とする方法。 - 前記第2のCTEは、前記第3のCTEとほぼ等しいことを特徴とする請求項16記載の方法。
- 前記第2のCTEは、前記第1のCTEと前記第3のCTEとの平均にほぼ等しいことを特徴とする請求項16記載の方法。
- 前記第1の材料はシリコンを含み、前記第3の材料は銅を含むことを特徴とする請求項16記載の方法。
- 前記第2の材料は、シリコン、アクリル酸塩、ポリイミド、ベンゾシクロブテン(BCB)、パリレン、フッ化炭化水素、ポリオレフィン、ポリエステル、および、エポキシ樹脂を含むグループから選択された材料を含むことを特徴とする請求項19記載の方法。
- 前記第2の材料は、第1および第3の材料と比較して、比較的柔軟性のある材料を含むことを特徴とする請求項16記載の方法。
- 第1の材料からなるダイと、
前記ダイへ伸びるビアと、
前記ビア内に配置された緩衝材料層と、
前記ビア内の前記緩衝材料上に配置された第2の材料と、を含み、
前記緩衝層は、前記第1および第2の材料間における熱膨張の不一致による応力を吸収することができる、
ことを特徴とする装置。 - 前記ダイは、正面側および対抗する裏面側を含み、ここで、回路類は、前記ダイの裏面側に形成され、相互接続構造は、前記ダイの正面側に配置されることを特徴とする請求項22記載の装置。
- 前記ビアは、前記ダイの裏面側から前記相互接続構造中の導体へ伸び、前記第2の材料は、導体材料を含むことを特徴とする請求項23記載の装置。
- 前記導体材料は銅を含み、前記ダイはシリコンを含むことを特徴とする請求項24記載の装置。
- 前記ダイは、第2のダイに接合されることを特徴とする請求項24記載の装置。
- 第1の材料からなる基板中にビアを形成する段階と、
前記ビア中に緩衝材料層を堆積する段階と、
前記緩衝層上に第2の材料を前記ビア内に堆積する段階と、を含み、
前記緩衝材料は、前記第1および第2材料と比較して、比較的柔軟性のある材料を含む、
ことを特徴とする方法。 - 前記第1および第2材料の各々は、およそ40GPAより大きい弾性係数を有することを特徴とする請求項27記載の方法。
- 前記緩衝材料は、およそ10GPa未満の弾性係数を有することを特徴とする請求項28記載の方法。
- 前記緩衝材料は、およそ0.001GPaより大きい弾性係数を有することを特徴とする請求項29記載の方法。
- 前記第1の材料はシリコンを含み、前記第2の材料は銅を含み、前記緩衝材料は、およそ0.001と10GPaとの間の範囲に弾性係数を有することを特徴とする請求項27記載の方法。
- 前記緩衝材料は、ほぼ前記第1の材料のCTEと前記第2の材料のCTEとの間の範囲に熱膨脹係数(CTE)を有することを特徴とする請求項27記載の方法。
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US11/169,595 US7402515B2 (en) | 2005-06-28 | 2005-06-28 | Method of forming through-silicon vias with stress buffer collars and resulting devices |
PCT/US2006/025471 WO2007002870A1 (en) | 2005-06-28 | 2006-06-28 | Method of forming through-silicon vias with stress buffer collars and resulting devices |
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US (2) | US7402515B2 (ja) |
JP (1) | JP2008545251A (ja) |
KR (2) | KR20090115819A (ja) |
CN (1) | CN101199049B (ja) |
DE (1) | DE112006001588T5 (ja) |
HK (1) | HK1118956A1 (ja) |
TW (1) | TWI336117B (ja) |
WO (1) | WO2007002870A1 (ja) |
Cited By (5)
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JP2009110983A (ja) * | 2007-10-26 | 2009-05-21 | Shinko Electric Ind Co Ltd | シリコンインターポーザとこれを用いた半導体装置用パッケージおよび半導体装置 |
JP2009246246A (ja) * | 2008-03-31 | 2009-10-22 | National Institute Of Advanced Industrial & Technology | 低容量貫通電極を持つ3次元積層構造体およびコンピュータシステム |
JP2010129684A (ja) * | 2008-11-26 | 2010-06-10 | Canon Inc | 半導体装置の製造方法および半導体装置 |
JP2015524172A (ja) * | 2012-06-07 | 2015-08-20 | レンセレイアー ポリテクニック インスティテュート | 三次元集積におけるシリコン貫通電極(tsv)応力を低減するためのコンフォーマルコーティング弾性クッションの使用 |
US9648741B2 (en) | 2014-12-15 | 2017-05-09 | Fujitsu Limited | Electronic device and method for manufacturing electronic device |
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US20060290002A1 (en) | 2006-12-28 |
CN101199049B (zh) | 2010-11-17 |
DE112006001588T5 (de) | 2008-05-21 |
KR20080014095A (ko) | 2008-02-13 |
TWI336117B (en) | 2011-01-11 |
KR100943306B1 (ko) | 2010-02-23 |
KR20090115819A (ko) | 2009-11-06 |
TW200707645A (en) | 2007-02-16 |
WO2007002870A1 (en) | 2007-01-04 |
HK1118956A1 (en) | 2009-02-20 |
CN101199049A (zh) | 2008-06-11 |
US7402515B2 (en) | 2008-07-22 |
US20080251932A1 (en) | 2008-10-16 |
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