JP2007053149A - 半導体ウエハ及びその製造方法 - Google Patents
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Abstract
複数の半導体チップを積層するときの、コンタクト電極を、半導体基板の裏面から加工するための製造方法を提案する。
【解決手段】
半導体基板の裏面から開口部がすり鉢状の貫通孔を形成した後、絶縁膜を形成し、その後、貫通孔の底面のコンタクト部となる部分の絶縁膜を除去し、シード層をスパッタした後、Auメッキとパッド部のパターンニングによりコンタクト電極を形成することを特徴とする。
【効果】
貫通孔の開口部がすり鉢状であるため、フォトリソグラフィー時、孔にレジストが充填されやすく、露光時に孔の底面まで光がまわりやすいため、孔底面の絶縁膜に開口パターンを形成することができる。これにより、裏面と素子面との電気的な接続が可能となる。さらに、半導体基板の裏面からの加工であるため半導体素子がプラズマによる影響を受けず、素子の欠陥が発生しない。
【選択図】 図1
Description
ドライエッチング装置により開口部の半導体基板をエッチングして孔を形成する工程と、
レジストを除去した後、半導体基板の第2の面に絶縁膜を形成する工程と、
さらに絶縁膜の上にアルミニウム膜を形成する工程と、
フォトリソグラフィ技術により、孔の底面の一部に開口を設けるレジストパターンニング工程の後、エッチングにより孔の底面のアルミニウム膜にパターンニングして開口を設けた後に、レジストを除去する工程と、
エッチングにより、孔底面の絶縁膜と半導体ウエハの第1の面に形成された絶縁膜を除去する工程と、
半導体基板の第2の面に、金属シード層を形成する工程と、
第2の面の金属シード層に、フォトリソグラフィ技術により、孔部を含む部分に開口を有するパターンニング工程と、
メッキにより、孔を含む部分の開口に金属層を堆積させた後、レジストを除去する工程と、
孔を含む部分のパターンに、フォトリソグラフィ技術によりレジストのカバーを設けた後に、金属シード層をエッチングして、パッドと配線を半導体基板の第2の面に形成することを特徴とする半導体ウエハの製造方法を提案するものである。
ドライエッチング装置により開口部の半導体基板をエッチングして孔を形成する工程と、
レジストを除去した後、半導体基板の第2の面に絶縁膜を形成する工程と、さらにフォトリソグラフィ技術により、孔の底面の一部に開口を設けるレジストパターンニング工程と、
エッチングにより、孔底面の絶縁膜と半導体ウエハの第1の面に形成された絶縁膜を除去した後、レジストを除去する工程と
半導体ウエハの第2の面と孔の内面と底面に、金属シード層を形成する工程と、
第2の面の金属シード層に、フォトリソグラフィ技術により、孔部を含む部分に開口を有するパターンニング工程と、
メッキにより、孔を含む部分の開口に金属層を堆積させた後、レジストを除去する工程と、
孔を含む部分のパターンに、フォトリソグラフィ技術によりレジストのカバーを設けた後に、金属シード層をエッチングして、パッドと配線を半導体ウエハの第2の面に形成する工程とを有する半導体ウエハの製造方法を提案するものである。
図1は、裏面加工が完了した半導体ウエハの概略構成を示す模式的断面図、
図2は、図1の半導体ウエハの孔部分を拡大した模式的断面図、
図3は、半導体ウエハの保持と薄型化方法を示す模式的断面図、
図4〜図8は、半導体ウエハの製造において、裏面加工プロセスを説明するための模式的断面図である。
図21は、半導体チップの一部を拡大したパッド、配線を示す模式的平面図である。
Claims (15)
- 第1の面に半導体素子が形成された半導体基板の第2の面に、フォトリソグラフィ技術により、前記半導体基板の第1の面に設けられ、前記半導体素子と電気的に接続した電極の位置と相対する位置に開口を設けるレジストパターンニング工程と、
ドライエッチング装置により前記開口部の前記半導体基板をエッチングして孔を形成する工程と、
前記レジストを除去した後、前記半導体基板の第2の面に絶縁膜を形成する工程と、
前記絶縁膜の上にアルミニウム膜を形成する工程と、
フォトリソグラフィ技術により、前記孔の底面の一部に開口を設けるレジストパターンニング工程の後、エッチングにより前記孔の底面の前記アルミニウム膜にパターンニングして開口を設けた後に、前記レジストを除去する工程と、
エッチングにより、前記孔底面の前記絶縁膜と前記半導体基板の第1の面に形成された絶縁膜を除去する工程と、
前記半導体基板の前記第2の面と前記孔の内面と底面に、金属シード層を形成する工程と、
前記第2の面の前記金属シード層に、フォトリソグラフィ技術により、前記孔部を含む部分に開口を有するパターンニング工程と、
メッキにより、前記孔を含む部分の開口に金属層を堆積させた後、前記レジストを除去する工程と、
前記孔を含む部分のパターンに、フォトリソグラフィ技術によりレジストのカバーを設けた後に、前記金属シード層をエッチングして、パッドと配線を半導体基板の第2の面に形成する工程とを有すること特徴とする半導体ウエハの製造方法。 - 第1の面に半導体素子が形成された半導体基板の第2の面に、フォトリソグラフィ技術により、前記半導体基板の第1の面に設けられ、前記半導体素子と電気的に接続した電極の位置と相対する位置に開口を設けるレジストパターンニング工程と、
ドライエッチング装置により前記開口部の前記半導体基板をエッチングして孔を形成する工程と、
前記レジストを除去した後、前記半導体基板の第2の面に絶縁膜を形成する工程と、
フォトリソグラフィ技術により、前記孔の底面の一部に開口を設けるレジストパターンニング工程と、
エッチングにより、前記孔底面の前記絶縁膜と前記半導体ウエハの第1の面に形成された絶縁膜を除去した後、前記レジストを除去する工程と、
前記半導体ウエハの前記第2の面と前記孔の内面と底面に、金属シード層を形成する工程と、
前記第2の面の前記金属シード層に、フォトリソグラフィ技術により、前記孔部を含む部分に開口を有するパターンニング工程と、
メッキにより、前記孔を含む部分の開口に金属層を堆積させた後、前記レジストを除去する工程と、
前記孔を含む部分のパターンに、フォトリソグラフィ技術によりレジストのカバーを設けた後に、前記金属シード層をエッチングして、パッドと配線を半導体基板の第2の面に形成する工程とを有すること特徴とする半導体ウエハの製造方法。 - 請求項1または請求項2に記載の半導体ウエハの製造方法において、
前記半導体基板に前記孔を形成する前記ドライエッチングは、等方性エッチングの後に異方性エッチングしたことを特徴とする半導体ウエハの製造方法。 - 請求項1または請求項2に記載の半導体ウエハの製造方法において、
前記半導体ウエハに形成した前記孔の開口上部がすり鉢状の形状であることを特徴とする半導体ウエハの製造方法。 - 請求項1または請求項2に記載の半導体ウエハの製造方法において、
前記絶縁膜が二酸化シリコンであることを特徴とする半導体ウエハの製造方法。 - 請求項1または請求項2に記載の半導体ウエハの製造方法において、
前記絶縁膜を除去する工程がドライエッチングであることを特徴とする半導体ウエハの製造方法。 - 請求項1または請求項2に記載の半導体ウエハの製造方法において、
前記絶縁膜を除去する工程がウェットエッチングであることを特徴とする半導体ウエハの製造方法。 - 第1の面に半導体素子が形成された半導体基板の第2の面が、前記半導体素子と電気的に接続した電極と相対する位置に孔を有し、前記第2の面の前記孔を含む位置に電極パッドが形成され、前記孔の壁面に配線が形成され、前記第1の面の前記電極と、前記第2の面の電極パッドが電気的に接続し、前記孔の開口部がすり鉢状であることを特徴とする半導体ウエハ。
- 第1の面に半導体素子が形成された半導体基板の第2の面が、前記半導体素子と電気的に接続した電極と相対する位置に孔を有し、前記第2の面の前記孔を含む位置に電極パッドが形成され、前記孔の壁面に配線が形成され、前記孔の底面の一部に絶縁膜の開口が設けられ、前記第1の面の前記電極と、前記第2の面の電極パッドが電気的に接続し、前記孔の開口部がすり鉢状であることを特徴とする半導体ウエハ。
- 請求項8または請求項9に記載の半導体ウエハにおいて、
前記第1の面に形成された絶縁膜の前記電極部分の厚みが他の部分よりも薄いことを特徴とする半導体ウエハ。 - 請求項8または請求項9に記載の半導体ウエハにおいて、
前記第1の面に形成された絶縁膜の前記電極部分に、前記電極と電気的に接続するコンタクトプラグを有することを特徴とする半導体ウエハ。 - 請求項8乃至請求項11のうちの何れか1項に記載の半導体ウエハにおいて、
前記孔の壁面の前記配線は、メッキにより形成されたことを特徴とする半導体ウエハ。 - 請求項1乃至請求項7のうちの何れか1項に記載の半導体ウエハの製造方法で製造したことを特徴とする半導体ウエハ。
- 請求項1乃至請求項7のうちの何れか1項に記載の半導体ウエハの製造方法で製造した半導体ウエハを分割して半導体チップを形成し、前記半導体チップを複数積層したことを特徴とする半導体装置。
- 請求項8乃至請求項13のうちの何れか1項に記載の半導体ウエハを分割して形成された半導体チップを複数積層したことを特徴とする半導体装置。
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CN104600024B (zh) * | 2013-10-30 | 2019-12-24 | 拉碧斯半导体株式会社 | 半导体装置及其制造方法 |
US10580732B2 (en) | 2013-10-30 | 2020-03-03 | Lapis Semiconductor Co., Ltd. | Semiconductor device |
CN104600024A (zh) * | 2013-10-30 | 2015-05-06 | 拉碧斯半导体株式会社 | 半导体装置及其制造方法 |
JP2015173179A (ja) * | 2014-03-11 | 2015-10-01 | キヤノン株式会社 | 形成方法、および物品の製造方法 |
JP2017041539A (ja) * | 2015-08-20 | 2017-02-23 | 大日本印刷株式会社 | 金属充填構造体及びその製造方法 |
US11482557B2 (en) | 2018-03-09 | 2022-10-25 | Sony Semiconductor Solutions Corporation | Solid-state image-capturing device, semiconductor apparatus, electronic apparatus, and manufacturing method |
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