JP2011100963A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2011100963A JP2011100963A JP2010128045A JP2010128045A JP2011100963A JP 2011100963 A JP2011100963 A JP 2011100963A JP 2010128045 A JP2010128045 A JP 2010128045A JP 2010128045 A JP2010128045 A JP 2010128045A JP 2011100963 A JP2011100963 A JP 2011100963A
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Abstract
【解決手段】半導体装置は、基板80と、基板80に設けられた1又は複数のビアホール91と、1又は複数のビアホール91内にそれぞれ設けられた貫通電極TSVとをそれぞれ有する複数のコアチップと、貫通電極TSVを通じて各コアチップと電気的に接続するインターフェースチップとを備え、ビアホール91は、両端部の径r1,r3に比べて中央部r2の径が大きいボーイング形状部分91aを有する。
【選択図】図7
Description
4〜6 内部回路
10 半導体装置
11a,11b クロック端子
11c クロックイネーブル端子
12a〜12e コマンド端子
13 アドレス端子
14 データ入出力端子
15a,15b データストローブ端子
16 キャリブレーション端子
17a,17b 電源端子
21 クロック発生回路
22 DLL回路
23 入出力バッファ回路
24 キャリブレーション回路
25 データラッチ回路
31 コマンド入力バッファ
32 コマンドデコーダ
33 不良チップ情報保持回路
41 アドレス入力バッファ
42 モードレジスタ
43 パワーオン検出回路
44 層アドレス設定回路
45 層アドレスコントロール回路
46 層アドレス発生回路
47 層アドレス比較回路
50 メモリセルアレイ
51 ロウデコーダ
52 カラムデコーダ
53 センス回路
54 データコントロール回路
55 入出力回路
61 ロウ制御回路
61a アドレスバッファ
61b リフレッシュカウンタ
62 カラム制御回路
62a アドレスバッファ
62b バーストカウンタ
63 コントロールロジック回路
64 モードレジスタ
65 コマンドデコーダ
70 内部電圧発生回路
71 パワーオン検出回路
80 半導体基板
81 層間絶縁膜
82 絶縁リング
83,86 貫通電極TSVの端部
84 裏面バンプ
85 表面バンプ
87 層間絶縁膜
90 半導体基板
91 ビアホール
91a ボーイング形状部分
100 マスクパターン
101 シード層
102 マスクパターン
103 導電物質
104 バンプ
201 電極
202 スルーホール電極
203 再配線層
204 NCF
205 リードフレーム
206 アンダーフィル
207 封止樹脂
500 データ処理システム
510 システムバス
520 データプロセッサ
540 ストレージデバイス
550 I/Oデバイス
CC0〜CC7 コアチップ
IF インターフェースチップ
IP インターポーザ
L0〜L3 配線層
TSV 貫通電極
Claims (11)
- 1又は複数のビアホールと、前記1又は複数のビアホール内にそれぞれ設けられた貫通電極とを有する半導体基板を備え、
前記ビアホールは、両端部の径と中央部の径とが異なる部分を有することを特徴とする半導体装置。 - 前記部分は、両端部の径に比べて中央部の径が大きいボーイング形状部分であることを特徴とする請求項1に記載の半導体装置。
- 前記ビアホールの一方端部の開口径は、該ボーイング形状部分の前記一方端部側端部の径に比べて大きいことを特徴とする請求項2に記載の半導体装置。
- 前記ビアホールの他方端部の開口径は、該ボーイング形状部分の前記他方端部側端部の径に比べて大きいことを特徴とする請求項3に記載の半導体装置。
- それぞれ前記半導体基板を有する複数のコアチップと、
前記貫通電極を通じて前記各コアチップと電気的に接続するインターフェースチップとを備えることを特徴とする請求項1乃至4のいずれか一項に記載の半導体装置。 - 貫通電極を有する半導体基板を用いる半導体装置の製造方法であって、
前記半導体基板の一方表面に、平面視で前記貫通電極を形成すべき位置に開口を有するマスクパターンを形成するマスクパターン形成工程と、
前記マスクパターンの上から前記半導体基板をエッチングすることで、両端部の径に比べて中央部の径が大きいボーイング形状を有する第1のビアホールを形成する第1のビアホール形成工程と、
前記第1のビアホール内が導電物質で埋まるよう導電物質を成膜することにより、貫通電極を形成する貫通電極形成工程とを備えることを特徴とする半導体装置の製造方法。 - 前記半導体基板の他方表面に絶縁膜を形成する工程と、
前記絶縁膜をストッパとして用いて前記第1のビアホール内をエッチングすることで、前記第1のビアホールとの接続端部の径に比べて前記絶縁膜との接続端部の径が大きい第2のビアホールを形成する第2のビアホール形成工程とをさら備えることを特徴とする請求項6に記載の半導体装置の製造方法。 - 前記第2のビアホール形成工程では、前記第1のビアホール形成工程に比べて低いバイアス電力を用いることを特徴とする請求項6又は7に記載の半導体装置の製造方法。
- 前記絶縁膜の表面に配線層を形成する工程と、
前記第2のビアホール底面に露出した前記絶縁膜をエッチングすることで、前記配線層を露出させる配線層露出工程とをさらに備えることを特徴とする請求項6乃至8のいずれか一項に記載の半導体装置の製造方法。 - 前記第1及び第2のビアホール形成工程ではエッチングガスとしてSF6ガスを用い、
前記配線層露出工程ではエッチングガスとしてCF4ガスを用いることを特徴とする請求項9に記載の半導体装置の製造方法。 - 前記第1のビアホール形成工程を行う前に前記マスクパターンの上から前記半導体基板をエッチングすることで、開口端部の径が底面の径に比べて大きい第3のビアホールを形成する第3のビアホール形成工程をさらに備えることを特徴とする請求項6に記載の半導体装置の製造方法。
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US8519514B2 (en) | 2013-08-27 |
US20130328188A1 (en) | 2013-12-12 |
US8779560B2 (en) | 2014-07-15 |
JP5697898B2 (ja) | 2015-04-08 |
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