JP5593053B2 - 半導体装置 - Google Patents
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Description
4〜6 内部回路
10 半導体記憶装置
101〜108,111〜118 ドライバ回路
120,130,140 出力切り替え回路
121a〜128a 制御回路部
121b〜128b スイッチ回路部
121c〜128c 置換制御回路
201〜208,211〜218 レシーバ回路
220,230,240 入力切り替え回路
301〜310 貫通電極
400 救済情報保持回路
CC0〜CC7 コアチップ
IF インターフェースチップ
Claims (14)
- それぞれ1番〜n番(nは自然数)の番号が割り当てられたn個のドライバ回路を有する第1の半導体チップと、
前記1番〜n番のドライバ回路にそれぞれ対応して設けられ、それぞれ1〜n番の番号が割り当てられたn個のレシーバ回路を有する第2の半導体チップと、
前記第1の半導体チップ又は前記第2の半導体チップに設けられ、それぞれ1番〜n+m番(mは自然数)の番号が割り当てられたn+m個の貫通電極と、を備え、
前記第1の半導体チップは、i番(iは1〜nの整数)のドライバ回路の出力端をi番からi+m番の貫通電極のいずれかに接続することによって、前記n個のドライバ回路をそれぞれ異なる貫通電極に接続する出力切り替え回路を有し、
前記第2の半導体チップは、i番(iは1〜nの整数)のレシーバ回路の入力端をi番からi+m番の貫通電極のいずれかに接続することによって、前記n個のレシーバ回路をそれぞれ異なる貫通電極に接続する入力切り替え回路を有し、
前記出力切り替え回路は、1〜n番の第1選択信号をそれぞれ生成するn個の第1制御回路部と、対応する前記第1選択信号に基づいて、i番のドライバ回路の出力端をi番及びi+1番の第1信号パスのいずれかに接続するn個の第1スイッチ回路部とを含み、
j番(jは2〜nの整数)の第1制御回路部は、それぞれ対応する第1救済信号及びj−1番の第1選択信号に基づいて、j番の第1選択信号を生成し、
前記出力切り替え回路は、1〜n+1番の第2選択信号をそれぞれ生成するn+1個の第2制御回路部と、対応する前記第2選択信号に基づいて、k番(kは1〜n+1の整数)の第1信号パスをk番及びk+1番の第2信号パスのいずれかに接続するn+1個の第2スイッチ回路部とを含むことを特徴とする半導体装置。 - 前記出力切り替え回路は、より番号の大きいドライバ回路の出力端をより番号の大きい貫通電極に接続し、
前記入力切り替え回路は、より番号の大きいレシーバ回路の入力端をより番号の大きい貫通電極に接続することを特徴とする請求項1に記載の半導体装置。 - 前記i番からi+m番の貫通電極が隣接配置されていることを特徴とする請求項1又は2に記載の半導体装置。
- 1番の第1制御回路部は、前記第1選択信号にかかわらず、対応する第1救済信号に基づいて1番の第1選択信号を生成することを特徴とする請求項1乃至3のいずれか一項に記載の半導体装置。
- 前記第1信号パスは、それぞれ対応する貫通電極に接続されていることを特徴とする請求項1乃至4のいずれか一項に記載の半導体装置。
- p番(pは2〜n+1の整数)の第2制御回路部は、それぞれ対応する第2救済信号及びp−1番の第2選択信号に基づいて、p番の第2選択信号を生成することを特徴とする請求項1乃至5のいずれか一項に記載の半導体装置。
- 前記複数の貫通電極のうち、前記ドライバ回路及び前記レシーバ回路に接続されない貫通電極は、不良のある貫通電極であることを特徴とする請求項1乃至6のいずれか一項に記載の半導体装置。
- 前記第1の半導体チップと複数の前記第2の半導体チップが積層されており、前記貫通電極が前記複数の第2の半導体チップに設けられていることを特徴とする請求項1乃至7のいずれか一項に記載の半導体装置。
- 複数の前記第1の半導体チップと前記第2の半導体チップが積層されており、前記貫通電極が前記複数の第1の半導体チップに設けられていることを特徴とする請求項1乃至8のいずれか一項に記載の半導体装置。
- 複数の前記第1又は第2の半導体チップに設けられた前記貫通電極のうち、同じ番号が割り当てられた貫通電極は全て短絡されていることを特徴とする請求項8又は9に記載の半導体装置。
- 前記ドライバ回路及び前記レシーバ回路と前記貫通電極との接続関係は、複数の前記第1又は第2の半導体チップにおいて共通であることを特徴とする請求項10に記載の半導体装置。
- 前記第1及び第2の半導体チップの一方がインターフェースチップであり、他方がコアチップであることを特徴とする請求項1乃至6のいずれか一項に記載の半導体装置。
- 前記インターフェースチップは、前記第1救済信号を記憶する救済情報保持回路を有していることを特徴とする請求項12に記載の半導体装置。
- 前記インターフェースチップは、前記救済情報保持回路に記憶された前記第1救済信号を電源投入時に前記コアチップに転送することを特徴とする請求項13に記載の半導体装置。
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JP2009235488A JP5593053B2 (ja) | 2009-10-09 | 2009-10-09 | 半導体装置 |
US12/923,800 US8584061B2 (en) | 2009-10-09 | 2010-10-07 | Semiconductor device |
US13/872,553 US8839161B2 (en) | 2009-10-09 | 2013-04-29 | Semiconductor device |
US14/325,436 US9032350B2 (en) | 2009-10-09 | 2014-07-08 | Semiconductor device |
US14/634,510 US9312209B2 (en) | 2009-10-09 | 2015-02-27 | Semiconductor device |
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JP2009235488A JP5593053B2 (ja) | 2009-10-09 | 2009-10-09 | 半導体装置 |
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JP2012083243A (ja) | 2010-10-13 | 2012-04-26 | Elpida Memory Inc | 半導体装置及びそのテスト方法 |
WO2012086100A1 (ja) * | 2010-12-21 | 2012-06-28 | パナソニック株式会社 | 半導体装置 |
JP5684590B2 (ja) * | 2011-01-28 | 2015-03-11 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置 |
KR20120088450A (ko) * | 2011-01-31 | 2012-08-08 | 에스케이하이닉스 주식회사 | 반도체 장치 및 이의 리페어 방법 |
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KR20120108474A (ko) * | 2011-03-24 | 2012-10-05 | 에스케이하이닉스 주식회사 | 반도체 장치 |
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