JP5564230B2 - 積層型半導体装置 - Google Patents
積層型半導体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 112
- 239000000872 buffer Substances 0.000 claims description 84
- 238000006243 chemical reaction Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 8
- 230000003213 activating effect Effects 0.000 claims 2
- 230000002950 deficient Effects 0.000 description 39
- 239000010410 layer Substances 0.000 description 39
- 238000012360 testing method Methods 0.000 description 33
- 241000724291 Tobacco streak virus Species 0.000 description 32
- 230000006870 function Effects 0.000 description 17
- 230000007547 defect Effects 0.000 description 15
- 238000010586 diagram Methods 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000001514 detection method Methods 0.000 description 6
- 101100033865 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) RFA1 gene Proteins 0.000 description 5
- 101100524516 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) RFA2 gene Proteins 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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Description
4〜6 内部回路
10 半導体記憶装置
100〜108 切替回路
110,120 セレクタ回路群
111〜118,121〜129 セレクタ回路
200,300〜307 切替制御回路
210 切替情報保持回路
220 ラッチ回路
230 オシレータ回路
240,340 カウンタ回路
250,350 デコーダ
260 パラレルシリアル変換回路
360 救済データラッチ回路
401〜408,501〜508 バッファ回路
601〜610 TSV
700〜708,800〜808 切替回路
CC0〜CC7 コアチップ
IF インターフェースチップ
SW 貫通電極切替情報
Claims (18)
- 複数の半導体チップ間でデータ転送を行うための複数の貫通電極を互いに共有した積層型半導体装置であって、
前記複数の半導体チップに含まれる第1の半導体チップは、前記複数の貫通電極のうちデータ転送を行う貫通電極を指定する貫通電極切替情報を保持し、前記複数の半導体チップに含まれる第2の半導体チップに前記貫通電極切替情報を転送することを特徴とする積層型半導体装置。 - 前記第1の半導体チップは、前記貫通電極切替情報に基づいて前記データ転送を行う貫通電極を選択する第1の切替回路を備え、
前記第2の半導体チップは、前記第1の半導体チップから転送された前記貫通電極切替情報に基づいて、前記データ転送を行う貫通電極を選択する第2の切替回路を備えることを特徴とする請求項1に記載の積層型半導体装置。 - 前記第1の切替回路によって選択された貫通電極と前記第2の切替回路によって選択された貫通電極は、同一又は共通接続されていることを特徴とする請求項2に記載の積層型半導体装置。
- 前記第1の切替回路によって選択されない貫通電極は、前記第2の切替回路によっても選択されないことを特徴とする請求項2又は3に記載の積層型半導体装置。
- 前記第1の半導体チップは、前記貫通電極切替情報を保持する切替情報保持回路と、前記切替情報保持回路から読み出されたパラレルな前記貫通電極切替情報をシリアル変換して前記第2の半導体チップに転送するパラレルシリアル変換回路とをさらに備えることを特徴とする請求項2乃至4のいずれか一項に記載の積層型半導体装置。
- 前記第1の半導体チップは、クロック信号に同期してカウント動作を行う第1のカウンタ回路と、前記第1のカウンタ回路のカウント値をデコードする第1のデコーダとをさらに備え、
前記パラレルシリアル変換回路は、前記第1のデコーダの出力に基づいてパラレルシリアル変換を行うことを特徴とする請求項5に記載の積層型半導体装置。 - 前記第2の半導体チップは、シリアルに供給される前記貫通電極切替情報をラッチし、これをパラレル変換して前記第2の切替回路に供給する救済データラッチ回路を備えることを特徴とする請求項6に記載の積層型半導体装置。
- 前記第2の半導体チップは、前記クロック信号に同期してカウント動作を行う第2のカウンタ回路と、前記第2のカウンタ回路のカウント値をデコードする第2のデコーダとをさらに備え、
前記救済データラッチ回路は、前記第2のデコーダの出力に基づいてラッチ動作を行うことを特徴とする請求項7に記載の積層型半導体装置。 - 前記第1の切替回路は、それぞれ1番〜n番(nは自然数)の番号が割り当てられたn個の第1バッファ回路を含み、
前記第2の切替回路は、前記1番〜n番の第1バッファ回路にそれぞれ対応して設けられ、それぞれ1〜n番の番号が割り当てられたn個の第2バッファ回路を含み、
前記複数の貫通電極には、それぞれ1番〜n+m番(mは自然数)の番号が割り当てられており、
前記第1の切替回路は、前記貫通電極切替情報に基づいて、i番(iは1〜nの整数)の第1バッファ回路の入力端又は出力端をi番からi+m番の貫通電極のいずれかに接続することによって、前記n個の第1バッファ回路をそれぞれ異なる貫通電極に接続し、
前記第2の切替回路は、前記貫通電極切替情報に基づいて、i番(iは1〜nの整数)の第2バッファ回路の入力端又は出力端をi番からi+m番の貫通電極のいずれかに接続することによって、前記n個の第1バッファ回路をそれぞれ異なる貫通電極に接続することを特徴とする請求項2乃至8のいずれか一項に記載の積層型半導体装置。 - 前記第1の切替回路は、i番の第1バッファ回路の入力端又は出力端とi番からi+m番の貫通電極との間にそれぞれ設けられた複数の第1トライステートバッファを含み、
前記第2の切替回路は、i番の第2バッファ回路の入力端又は出力端とi番からi+m番の貫通電極との間にそれぞれ設けられた複数の第2トライステートバッファを含み、
前記第1の切替回路は、前記貫通電極切替情報に基づいて、i番の第1バッファ回路の入力端又は出力端と、i番からi+m番の貫通電極のうちいずれかの貫通電極との間に設けられた複数の第1トライステートバッファを活性化させ、
前記第2の切替回路は、前記貫通電極切替情報に基づいて、i番の第2バッファ回路の入力端又は出力端と、i番からi+m番の貫通電極のうちいずれかの貫通電極との間に設けられた複数の第2トライステートバッファを活性化させることを特徴とする請求項9に記載の積層型半導体装置。 - 前記貫通電極切替情報は、並列接続された複数の貫通電極を介して前記第1の半導体チップから前記第2の半導体チップに転送されることを特徴とする請求項1乃至10のいずれか一項に記載の積層型半導体装置。
- n個(nは自然数)の第1バッファ回路を有する第1の半導体チップと、
前記第1の半導体チップに積層され、n個の第2バッファ回路を有する第2の半導体チップと、
前記第1の半導体チップ又は前記第2の半導体チップに設けられたn+m個(mは自然数)の第1貫通電極と、
前記第1の半導体チップ又は前記第2の半導体チップに設けられた少なくとも一つの第2貫通電極と、を備え、
前記第1の半導体チップは、前記n+m個の貫通電極のうちn個の貫通電極を指定する貫通電極切替情報を保持する切替情報保持回路と、前記貫通電極切替情報に基づいて前記n個の貫通電極と前記n個の第1バッファ回路とを接続する第1の切替回路とを含み、
前記第2の半導体チップは、前記第2貫通電極を介して前記切替情報保持回路から転送される前記貫通電極切替情報に基づいて、前記n個の貫通電極と前記n個の第2バッファ回路とを接続する第2の切替回路とを含むことを特徴とする積層型半導体装置。 - 前記第1の半導体チップは、前記切替情報保持回路から読み出されたパラレルな前記貫通電極切替情報をシリアル変換するパラレルシリアル変換回路をさらに含み、シリアル変換された前記貫通電極切替情報が前記第2貫通電極を介して前記第2の半導体チップに転送されることを特徴とする請求項12に記載の積層型半導体装置。
- 前記第2貫通電極を複数備え、
前記第1の半導体チップは、並列接続された前記複数の第2貫通電極を介して前記貫通電極切替情報を前記第2の半導体チップに転送することを特徴とする請求項12又は13に記載の積層型半導体装置。 - 前記n個の第1バッファ回路は、それぞれ1番〜n番の番号が割り当てられ、
前記n個の第2バッファ回路は、前記1番〜n番の第1バッファ回路に対応してそれぞれ1〜n番の番号が割り当てられ、
前記n+m個の貫通電極には、それぞれ1番〜n+m番の番号が割り当てられ、
前記第1の切替回路は、前記貫通電極切替情報に基づいて、i番(iは1〜nの整数)の第1バッファ回路の入力端又は出力端をi番からi+m番の貫通電極のいずれかに接続することによって、前記n個の第1バッファ回路をそれぞれ異なる貫通電極に接続し、
前記第2の切替回路は、前記貫通電極切替情報に基づいて、i番(iは1〜nの整数)の第2バッファ回路の入力端又は出力端をi番からi+m番の貫通電極のいずれかに接続することによって、前記n個の第2バッファ回路をそれぞれ異なる貫通電極に接続することを特徴とする請求項12乃至14のいずれか一項に記載の積層型半導体装置。 - 前記第1の切替回路は、i番の第1バッファ回路の入力端又は出力端とi番からi+m番の貫通電極との間にそれぞれ設けられた複数の第1トライステートバッファを含み、
前記第2の切替回路は、i番の第2バッファ回路の入力端又は出力端とi番からi+m番の貫通電極との間にそれぞれ設けられた複数の第2トライステートバッファを含み、
前記第1の切替回路は、前記貫通電極切替情報に基づいて、i番の第1バッファ回路の入力端又は出力端と、i番からi+m番の貫通電極のうちいずれかの貫通電極との間に設けられた複数の第1トライステートバッファを活性化させ、
前記第2の切替回路は、前記貫通電極切替情報に基づいて、i番の第2バッファ回路の入力端又は出力端と、i番からi+m番の貫通電極のうちいずれかの貫通電極との間に設けられた複数の第2トライステートバッファを活性化させることを特徴とする請求項15に記載の積層型半導体装置。 - 前記第2の半導体チップを複数備え、
前記第1貫通電極及び前記第2貫通電極は、前記複数の第2の半導体チップにそれぞれ設けられており、
前記前記複数の第2の半導体チップに設けられた前記第1貫通電極及び前記第2貫通電極のうち、対応する貫通電極は互いに短絡されていることを特徴とする請求項12乃至16のいずれか一項に記載の積層型半導体装置。 - 前記第1の半導体チップは、外部とのインターフェースを行うフロントエンド部が集積されたインターフェースチップであり、
前記第2の半導体チップは、メモリコアを含むバックエンド部が集積されたコアチップであることを特徴とする請求項12乃至17のいずれか一項に記載の積層型半導体装置。
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