WO2007032184A1 - 半導体装置、半導体チップ、チップ間配線のテスト方法、および、チップ間配線切り替え方法 - Google Patents
半導体装置、半導体チップ、チップ間配線のテスト方法、および、チップ間配線切り替え方法 Download PDFInfo
- Publication number
- WO2007032184A1 WO2007032184A1 PCT/JP2006/316410 JP2006316410W WO2007032184A1 WO 2007032184 A1 WO2007032184 A1 WO 2007032184A1 JP 2006316410 W JP2006316410 W JP 2006316410W WO 2007032184 A1 WO2007032184 A1 WO 2007032184A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- chip
- wiring
- inter
- circuit
- control signal
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
- G01R31/2812—Checking for open circuits or shorts, e.g. solder bridges; Testing conductivity, resistivity or impedance
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31717—Interconnect testing
Definitions
- the present invention relates to a semiconductor chip, a semiconductor device having a plurality of semiconductor chips, an interchip wiring test method, and an interchip wiring switching method.
- Patent Document 1 Means for realizing a large-scale integrated circuit by stacking semiconductor chips without changing the chip area is described in Japanese Patent Laid-Open No. 4-196263 (hereinafter referred to as Patent Document 1).
- the memory circuit is stacked on another chip stacked on the integrated circuit body.
- Patent Document 2 Japanese Patent Application Laid-Open No. 2002-26283
- wiring between chips is required in addition to the wiring in the chip surface so far.
- wiring between the chips there is a through wiring that penetrates the back surface from the front surface of the semiconductor substrate of the chip in order to increase the wiring density.
- Chip As a method for redundant repair of inter-wiring, as a test process in the device manufacturing process, a disconnection or short circuit and / or defective inter-chip wiring is identified by a continuity test of inter-chip wiring. Based on the test results, the address of the defective part is programmed using a fuse mounted on the chip for each stacked semiconductor device. When the device is used, the defective interchip wiring path is switched to a spare interchip wiring path based on the programmed address.
- this method requires a test process and a fuse program process for each stacked semiconductor device, and is expensive.
- test signal data is transferred to the sending side of all interchip wiring. After passing these test signal data through each inter-chip wiring, all the data on the sending side and the receiving side are chipped in order to compare the test signal data on the receiving side with the original test signal data. It is transferred to the coincidence judgment circuit provided at a specific location. For these data transfers, flip-flops are connected to scan the data.
- test day Data storage elements, test result storage elements, connection rearrange circuits, etc. are required at both ends of all interchip wiring.
- Patent Document 3 requires a clock cycle time corresponding to the number of inter-chip wirings for scanning test data, and includes a test signal and a coincidence determination circuit for each inter-chip wiring. Even if the test data is received, the test data on the receiving side is restored, the test is performed on each of the low and high levels to test the low and high signal transmission, and the test results are It takes time to tally and switch the wiring, and it is difficult to do it during device operation.
- the number of inter-chip wiring is as high as several hundreds, and the distance between inter-chip wiring is as small as several tens / zm. Considering this, in order to provide a test and relief circuit for each inter-chip wiring, it is necessary to reduce the size of each circuit.
- the present invention has been made to solve the problems of the conventional techniques as described above, and detects a defect in inter-chip wiring, and switches to normal inter-chip wiring in accordance with the result.
- An object of the present invention is to provide a semiconductor chip, a semiconductor device, an inter-chip wiring test method, and an inter-chip wiring switching method.
- a semiconductor device of the present invention includes a first inter-chip interconnect for electrically connecting a first semiconductor chip and a second semiconductor chip, and a first inter-chip interconnect.
- a test signal generation circuit that transmits a test signal to the second semiconductor chip via the first inter-chip wiring, and a test signal that is provided on the second semiconductor chip and receives the test signal via the first inter-chip wiring
- the determination circuit that outputs the second control signal that is an inverted signal of the first control signal and the second semiconductor chip are provided.
- the first inter-chip wiring is set as a path for electrically connecting the first semiconductor chip and the second semiconductor chip, and the second control signal is set.
- a switching circuit that sets a second inter-chip wiring as a path when a signal is input.
- the test signal from the test signal generation circuit reaches the second semiconductor chip from the first semiconductor chip via the first inter-chip wiring, the path between the chips is obtained.
- the first interchip wiring is selected.
- the test signal does not reach the second semiconductor chip, it is determined that the first inter-chip wiring is defective, and the second inter-chip wiring of the spare wiring is selected as a route.
- FIG. 1 is a schematic diagram showing a configuration example of a stacked semiconductor device according to this embodiment.
- FIG. 2 is a diagram showing an example of wiring connecting circuit 100A and circuit 100B shown in FIG.
- FIG. 3 is a flowchart showing a procedure of an interchip wiring switching method.
- FIG. 4 is a diagram illustrating a configuration example of a test determination circuit.
- FIG. 5 is a diagram showing another configuration example of the test determination circuit.
- FIG. 6 is a diagram showing signal waveforms when normal inter-chip wiring is normal and defective.
- FIG. 7 is a schematic diagram showing a configuration example in which a plurality of regular inter-chip wirings are provided on chip A. It is.
- FIG. 8 is a diagram showing an example of a circuit configuration in the case where the chip A also selects which of the regular and spare inter-chip wiring is selected.
- FIG. 9 is a schematic diagram of the stacked semiconductor device of Example 1.
- FIG. 10 is a diagram showing a configuration example of redundant relief circuits for chip A and chip B.
- FIG. 11 is a diagram showing signal waveforms resulting from the operation of the configuration shown in FIG.
- FIG. 12A is a schematic view showing a configuration of the stacked semiconductor device of Example 2.
- FIG. 12A is a schematic view showing a configuration of the stacked semiconductor device of Example 2.
- FIG. 12B is an enlarged view of a redundant switching portion of the stacked semiconductor device shown in FIG. 12A.
- FIG. 13 is a diagram showing an example of a redundant relief circuit configuration of chip C and chip D shown in FIG. 12A.
- a semiconductor device includes a circuit for sending a test signal to the inter-chip wiring, a circuit for determining whether the inter-chip wiring is good or not based on whether or not the test signal is received, and a defective inter-chip wiring. And a circuit for switching to spare interchip wiring.
- the semiconductor device of this embodiment will be described.
- a case of a stacked semiconductor device having a configuration in which a plurality of semiconductor chips are stacked will be described.
- FIG. 1 is a schematic diagram showing a configuration example of a stacked semiconductor device.
- the stacked semiconductor device has a configuration in which a chip A is stacked on a chip B.
- Chip A is provided with circuit 100A
- chip B is provided with circuit 100B.
- an interchip wiring for transmitting signals between the chips is provided.
- the inter-chip wiring includes a spare inter-chip wiring 120 that is a substitute for the regular inter-chip wiring 110 when the regular inter-chip wiring 110 is defective due to disconnection or short circuit.
- Regular chip wiring 110 and spare chip wiring Line 120 is a through wire and is shown schematically in FIG.
- FIG. 2 is a diagram showing an example of wiring connecting circuit 100A and circuit 100B shown in FIG.
- the tristate buffer 1 is connected in series between the wiring connecting the circuit 100 A and the regular inter-chip wiring 110. Further, a relay point between the circuit 100A and the tristate buffer 1 and the spare interchip wiring 120 are connected by wiring, and the tristate buffer 2 is connected in series in the middle of the wiring. Further, a test signal generating circuit 4 is connected to a relay point between the tristate buffer 1 and the regular interchip wiring 110. A tristate buffer 3 is connected in series between the relay point and the test signal generation circuit 4.
- the tristate buffer 5 is connected in series between the wiring connecting the circuit 100 B and the regular inter-chip wiring 110. Further, the relay point between the circuit 100B and the tristate buffer 5 and the spare interchip wiring 120 are connected by wiring, and the tristate buffer 6 is connected in series in the middle of the wiring. Further, a test judgment circuit 8 is connected to a relay point between the tristate buffer 5 and the regular interchip wiring 110. A tristate buffer 7 is connected in series between the relay point and the test judgment circuit 8. Then, a wiring is connected to the test determination circuit 8 and the tristate buffer 5, and a signal output from the test determination circuit 8 is input to the tristate buffer 5 as a control signal.
- the tri-state buffer shown in Fig. 2 is enabled depending on the level of the input control signal, and connects the internal (IN side) and external (OUT side), or vice versa. It becomes. High impedance results in the same state as when the inside is disconnected from the outside.
- the tristate buffers 1, 2, and 5 whose control signal input terminals are circled are enabled when the voltage is a low level control signal.
- the tristate buffer 6 whose control signal input terminal is not circled is enabled when the voltage is a high level control signal.
- Chip A if the tristate buffers 1 and 2 are enabled, the signal from the circuit 100 A is sent to both the regular interchip wiring 110 and the spare interchip wiring 120.
- Chip B has a tri-state buffer 5 connected to the output of the regular inter-chip wiring 110 and a spare chip. One of the tristate buffers 6 connected to the output of the inter-wire 120 is enabled. If there is no problem such as a defect in the regular interchip wiring 110, the tristate buffer 5 on the regular interchip wiring 110 side is enabled by the control signal from the test decision circuit 8, and the signal path to the circuit 100B is Wiring 110 is selected.
- the spare chip-to-chip wiring 6 on the 120 side is enabled by the control signal from the test judgment circuit 8, and the spare chip-to-chip wiring is used as a signal path to the circuit 100B. 120 is selected.
- Tristate buffers 5 and 6 serve as switching circuits for selecting the chip-to-chip wiring.
- FIG. 3 is a flowchart showing the procedure of the inter-chip wiring switching method.
- Information “1” corresponds to a high signal level, and information “0” corresponds to a low signal level.
- the output from the test determination circuit 8 of the chip B to the tristate buffers 5 and 6 is set to the initial value ".
- a signal is transmitted to the circuit 100B in the initial state.
- the spare inter-chip wiring 120 is selected.
- the tristate buffers 1 and 2 on the path of the interchip wiring from the circuit 100A of the chip A are also made to have a high impedance and the test signal generating circuit 4 Enable tri-state buffer 3 on the path leading to regular interchip interconnect 110.
- a test signal is sent to the chip B via the regular interchip wiring 110 (step 101).
- the test determination circuit 8 determines whether or not a test signal is received from the chip A (step 102).
- the test signal is transmitted to the chip B and sent to the test determination circuit 8.
- the test determination circuit 8 receives this test signal as a control signal, the output is changed from the initial value “1” to “0” (step 103). The value is held in the test decision circuit 8 as the decision result.
- the tri-state buffer 5 receives information “0” from the test determination circuit 8 as a control signal, the tri-state buffer 5 is enabled. Conversely, tristate noffer 6 is no longer enabled. As a result, the regular interchip wiring 110 is selected as a route (step 104).
- step 102 if the normal interchip wiring 110 is defective, the test signal generation circuit The test signal output from 4 is not sent to the test decision circuit 8. In this case, the value held in the test determination circuit 8 as the determination result remains the initial value “1” (step 105). As a result, the inter-chip wiring that transmits a signal to the circuit 100B becomes the preliminary inter-chip wiring 120 selected in the initial state (step 106).
- the processing of steps 101 to 103 and 105 corresponds to the procedure of the test method for checking whether or not the normal interchip wiring 110 is normal.
- the test method and the wiring switching method shown in FIG. 3 are performed at a predetermined timing between two chips, and the number of executions is not limited to one and may be plural.
- the determination result of the test determination circuit 8 of the chip B is “0”. This determination result is input to the tristate buffers 5 and 6 in the output part of the interchip wiring of chip B as a switching control signal. Then, the tristate buffer 6 on the spare interchip wiring 120 side becomes high impedance, the tristate buffer 5 on the normal interchip wiring 110 side is enabled, and the path is switched to the normal interchip wiring 110. On the other hand, if the regular inter-chip wiring 110 is defective, the determination result of the test determination circuit 8 remains “1”, so that the spare inter-chip wiring 120 is selected.
- test determination circuit 8 will be described.
- FIG. 4 is a diagram illustrating a configuration example of the test determination circuit.
- the test determination circuit 8 has a configuration including a flip-flop circuit 30 and performs test determination at a frequency level of data exchanged between the chips.
- the test signal is a toggle waveform equivalent to repeated low and high data at the operating frequency.
- the output timing of the data input value differs depending on the type of the flip-flop circuit 30 as follows.
- the flip-flop circuit 30 When the flip-flop circuit 30 is of the rising edge detection type of the clock input waveform, the flip-flop circuit 30 outputs the data input value when the input test signal transitions from low to noise. Further, when the flip-flop circuit 30 is a falling edge detection type of the clock input waveform, the flip-flop circuit 30 is input. When the test signal K changes from low to low, the data input value is output. Therefore, in either case, if the data output of the flip-flop circuit 30 is first set to "1" and the data input is set to "0", only when the toggle signal is input to the clock terminal, The output changes to "0".
- FIG. 5 is a diagram illustrating another configuration example of the test determination circuit.
- the test determination circuit 8 has a configuration having a shift register in which two flip-flop circuits 34 and 35 are connected in series. In this case, since the output changes to “0” only when the toggle waveform to the clock pin repeats the transition of the low force to the high level twice or more, a more reliable determination is possible.
- FIG. 6 is a diagram showing signal waveforms when the regular inter-chip wiring is normal and defective.
- the test determination circuit 8 has a configuration having one rising edge detection type flip-flop circuit.
- Chip A test signal generation circuit 4 sends a toggle waveform of test signal TSG to regular interchip interconnect 110.
- the test signal TSG is input to the clock input terminal of the flip-flop circuit 30 of the test determination circuit 8 of the chip B shown in FIG.
- the flip-flop circuit 30 outputs the data input value “0” to the output terminal when the input test signal TSG transitions from low to high.
- the output value SWB is at the low level indicated by the solid line.
- the clock input terminal of the flip-flop circuit 30 is short-circuited to a high impedance state or to a fixed potential such as a ground potential and a power supply potential. In this case, it remains at that potential. For this reason, the flip-flop circuit 30 does not output the data input value “0” to the output terminal, but maintains the state of outputting the initial value “. As shown in FIG. To maintain.
- transmission of a high level signal and transmission of a low level signal This can be determined by detecting only one transition from low to high. In other words, it is not necessary to compare the high-level signal on the sending side and the high-level signal on the receiving side, and the low-level signal on the sending side and low-level signal on the receiving side.
- test and wiring switching operation are inserted not only at the time of starting the device but also during operation. It becomes possible to do. This is effective against defects that occur in the chip-to-chip wiring due to chip temperature rise during operation.
- the minimum circuit configuration necessary for the above-described test and wiring switching control is the chip B on the receiving side, as shown in FIG. Two tristate buffers, one spare interchip interconnect, and one tristate buffer.
- the tip A on the sending side requires a test signal generation circuit as shown in Fig.2.
- the test signal is a toggle signal that repeats a low level voltage and a high level voltage.
- a new circuit such as a test signal generation circuit which may use a clock signal used for synchronization of the circuit 100A or a divided clock signal. Therefore, even if the number of wirings between chips is several hundreds, the circuit scale for testing and switching can be kept small.
- the signal from the circuit 100A flows through both the regular and spare inter-chip wirings. Considering the power consumption of the wiring charge / discharge, it is more advantageous to select one of the paths on the input side of the interchip wiring.
- FIG. 7 is a schematic diagram showing a configuration example in which a plurality of regular interchip wirings are provided on chip A.
- the circuit 100A, the circuit 100A, and the circuit 100A are provided on the chip A. It is The circuit 100A is connected to the regular interchip wiring 111A via the tristate buffer 9, and is connected to the spare interchip wiring 121 via the tristate buffer 10. The circuit 100A is connected to the normal interchip wiring 111A "via the tristate buffer 11, and is connected to the spare interchip wiring 121 via the tristate buffer 12. The circuit 100A" includes the tristate buffer 13 Is connected to the regular interchip wiring 111A '"via the tristate buffer 14, and is connected to the spare interchip wiring 121 via the tristate buffer 14.
- FIG. 8 is a diagram illustrating a circuit configuration example of the chip A and the chip B when the chip A determines which of the regular and spare inter-chip wirings to select.
- the circuit 100 A of the chip A is connected to the regular interchip wiring 110 via the tristate buffer 15 and is connected to the spare interchip wiring 120 via the tristate buffer 16. Yes.
- a test signal generating circuit 19 is connected via a tristate buffer 17 to a relay point of the wiring connecting the circuit 100A and the regular interchip wiring 110.
- a test determination circuit 20 is connected to the same relay point via a tristate buffer 18. Tristate buffers 15 and 18 are enabled when the control signal is at low level, and tristate buffers 16 and 17 are enabled when the control signal is at high level.
- circuit B is connected to regular inter-chip wiring 110 via tristate buffer 21 and is connected to spare interchip wiring 120 via tristate buffer 22.
- a test signal generation circuit 25 is connected via a tri-state buffer 23 to a relay point of the wiring connecting the circuit 100B and the regular inter-chip wiring 110. Also that same relay A test determination circuit 26 is connected to the point via a tristate buffer 24. Tristate buffers 21 and 23 are enabled when the control signal is low, and tristate buffers 22 and 24 are enabled when the control signal is high.
- the outputs of the test judgment circuits 20 and 26 in the chip A and the chip B are both set to the initial value “1”.
- the tristate buffers 15 and 21 before and after the regular chip-to-chip wiring 110 become high impedance.
- the tristate buffers 16 and 22 before and after the spare interchip wiring 120 are enabled. For this reason, the circuit 100A and the circuit 100B are in a state where signals are exchanged by the preliminary interchip wiring 120, not by the regular interchip wiring 110.
- the test signal generation circuit 19 of the chip A outputs a test signal and sends it to the regular interchip wiring 110.
- the test signal is transmitted to the chip B and input to the test determination circuit 26.
- the test judgment circuit 26 sets the judgment result power “1” in the initial state to “0” and holds the value, and the output of the test judgment circuit 26 is set to “0”.
- the tristate buffer 21 is enabled, the tristate buffer 22 becomes high impedance, and the path to the circuit B in the chip B is normally routed from the spare interchip wiring 120. Switch to wiring 110.
- the test signal transmitted from the chip A is not transmitted to the test determination circuit 26 of the chip B.
- the value held as the determination result in the test determination circuit 26 remains the initial value “1”. Therefore, the spare interchip wiring 120 is maintained as a path to the circuit B in the chip B.
- test signal generation circuit 25 of the chip B outputs a test signal and sends it to the regular interchip wiring 110.
- the test judgment circuit 20 of chip A makes the following judgment.
- the test determination circuit 20 receives the test signal and outputs “0” if the normal inter-chip wiring 110 is normal. On the contrary, if the regular inter-chip wiring 110 is defective, the test signal is not received and the initial value “1” is output as it is.
- the tri-state buffer 15 is enabled. As a result, the tristate buffer 16 becomes high impedance, and the path to the circuit A in the chip A is switched from the spare interchip wiring 120 to the regular interchip wiring 110. If the normal inter-chip wiring 110 is defective, the spare inter-chip wiring 120 is maintained in the chip A as a path to the circuit 100A.
- the two-way up / down test and the automatic path switching can be simultaneously performed on each inter-chip wiring.
- the inter-chip wiring test and the redundancy relief can be performed in a short time during the start-up or operation of the stacked semiconductor device.
- the transmission timing and the transmission cycle of the test signal are made to correspond to the input / output cycle of data exchanged between chip A and chip B. If the process from the test to the wiring switching is completed in one cycle of data input / output, it is possible to insert the test and the wiring switching operation as needed not only at the time of starting the apparatus but also during the operation.
- the inter-chip wiring for electrically connecting a plurality of semiconductor chips a determination is made as to whether or not the inter-chip wiring is normal, and a normal chip corresponding to the result is determined. Switching to the intermediate wiring is performed. If the determination power wiring is switched in several cycles of the operating frequency, even if the chip-to-chip wiring becomes defective during the operation of the semiconductor device, it is possible to set the spare inter-chip wiring again. In addition, compared to conventional wafer test and fuse repair methods, the fuse is not necessary because the cost of the test process during manufacturing is reduced.
- FIG. 9 is a schematic diagram of the stacked semiconductor device of this example.
- the chip A is stacked on the chip B. It is a layered configuration.
- Chip A is provided with a circuit 100A and a circuit 100A ′.
- Chip B is provided with a circuit 100B and a circuit 100B ′.
- the chips are connected by a regular interchip wiring 111A, a regular interchip wiring 111A ', and a spare interchip wiring 121.
- chip A and chip B are stacked, and in order to transmit signals from chip A to chip B, two regular inter-chip wirings are provided, and one spare one is provided. It is provided. If there is an electrical failure such as disconnection or short circuit in one of the two regular interchip interconnects, redundant relief is performed by switching the defective interchip interconnect to a spare interchip interconnect transmission path.
- FIG. 10 is a diagram showing a configuration example of redundant relief circuits for chip A and chip B.
- the tristate buffer 36 for selecting the path from the circuit 100A to the regular interchip wiring 111A and the circuit 100A force also selects the path to the spare interchip wiring 121
- a tristate buffer 37 is provided for each path.
- a tristate buffer 38 for selecting a path from the circuit 100A 'to the regular interchip wiring 111A' and a tristate buffer 39 for selecting a path from the circuit 100A 'to the spare interchip wiring 121 are provided. It is provided for each route.
- the chip A is provided with a test signal generating circuit 44 for sending a test signal to the chip B, and flip-flop circuits 45 and 46 for determining a test signal that also receives the chip B force.
- the test signal generation circuit 44 of the chip A is connected to the path to the regular interchip wiring 111A via the tristate buffer 40. Further, it is connected to the path to the regular interchip wiring 111A ′ via the tristate buffer 42.
- the flip-flop circuit 45 is connected to the path from the regular interchip interconnect 111A via the tri-state buffer 41.
- the flip-flop circuit 46 is connected to the path from the regular interchip wiring 111 A ′ via the tristate buffer 43.
- the control signal input to the tristate buffers 40 and 41 selects whether the test signal from the test signal generation circuit 44 is sent to the chip B and whether the test signal that also receives the chip B force is input to the flip-flop circuit 45.
- the Try The state buffers 42 and 43 function in the same manner as the tristate buffers 40 and 41, respectively.
- chip B has a tristate buffer 47 for selecting a path from the regular interchip wiring 111A to the circuit 100B and a path from the spare interchip wiring 121 to the circuit 1 OOB.
- a tri-state buffer 48 for selection is provided for each path.
- a tristate buffer 49 for selecting the path from the regular interchip interconnect 111B 'to the circuit 100B' and a tristate buffer 50 for selecting the path from the spare interchip interconnect 121 to the circuit 100B ' are provided. It is provided in the route.
- the chip B is provided with a test signal generation circuit 55 for sending a test signal to the chip A, and flip-flop circuits 56 and 57 for determining a test signal that also receives the chip A power.
- the test signal generation circuit 55 of the chip B is connected to the path to the regular interchip wiring 111A via the tristate buffer 51. Further, it is connected to the path to the regular interchip wiring 111A ′ via the tristate buffer 53.
- the flip-flop circuit 56 is connected to the path from the regular interchip interconnect 111A via the tri-state buffer 52.
- the flip-flop circuit 57 is connected to the path from the regular interchip interconnect 111 A ′ via the tristate buffer 54.
- the control signal input to the tristate buffers 51 and 52 selects whether the test signal from the test signal generation circuit 55 is sent to the chip A and the test signal that also receives the chip A power is input to the flip-flop circuit 56.
- the tri-state buffers 53 and 54 function in the same manner as the tri-state buffers 51 and 52, respectively.
- test signal generating circuits 44 and 55 divide the frequency when receiving the clock signal at the operating frequency. Output.
- the circuit configuration example shown in FIG. 10 and the operation of the configuration shown in FIG. This will be described with reference to FIG. 11 showing signal waveforms.
- the regular interchip wiring 111A is electrically defective and the regular interchip wiring 111A ′ is normal.
- the output is set to the initial value “1” for the flip-flop circuits 45, 46, 56, 57 of the test decision circuit having four power points.
- the path of the spare interchip wiring 121 is selected instead of the regular interchip wiring 111A, 111A ′.
- the high-level control signal TEN is input to the tristate buffer 40 and the tristate buffer 42 to enable them (see Fig. 11). Dashed line Tl).
- the test signal generation circuit 44 of the chip IV generates a low and a noise toggle signal TSG, and sends the toggle signal to the tristate buffers 40 and 42 as a test signal. Since the regular interchip wiring 111A is electrically defective, the toggle signal transmitted from the tristate buffer 40 is not transmitted to the chip B. Since the normal interchip wiring 111 A ′ is normal, the toggle signal transmitted from the tristate buffer 42 is transmitted to the chip B.
- the control signal is input so that the signals from the regular interchip interconnects 111A and 111A are input to the clock input terminals of the flip-flop circuits 56 and 57, which are test determination circuits. To enable tristate buffers 52 and 54. Since the normal interchip wiring 111A is electrically defective, the toggle signal is not input to the clock input terminal of the flip-flop circuit 56 for judging this, and the output SWB of the flip-flop circuit 56 is the initial value “1”. Remains.
- test signal generation circuit 55 of the chip B sends a test signal to the chip A, and selects a path in the chip A as follows.
- chip B low level control signal
- the toggle signal output from test signal generator 55 is sent as test signal to regular interchip interconnect 111A and regular interchip interconnect 111A '.
- the path to the circuit 100A remains the path using the spare interchip wiring 121, but the path to the circuit 100A ′ is switched to the path using the regular interchip wiring 111A ′. In this way, the path in chip A is selected. The selected state of this path is maintained until the flip-flop circuit 46 is set to the initial value again or the power of the stacked semiconductor device is turned off.
- test determination and path switching are performed by the test signal transmission from chip A to chip B and the test signal transmission from chip B to chip A.
- a wiring route is determined.
- the test process is completed in two cycles of the operating frequency.
- the test signal judgment period is limited by the time of the control signal TEN. For this reason, for example, even for a defect in which the wiring between chips is conductive but the resistance is very high, the waveform of the test signal is greatly dulled before passing through the wiring between chips. The transition of the test signal input to the network is not completed, and it can be judged as defective.
- the inter-chip wiring test and the path switching are performed in a circuit built in the stacked semiconductor device, the test is started at the time of starting the device or during operation, and a test pattern is input to the inter-chip wiring. It is possible to automate all procedures up to the redundant relief.
- the normal interchip wiring 111A is defective and the normal interchip wiring 111A 'is normal has been described.
- the normal interchip wiring 111A is normal and the normal interchip wiring 111A is normal.
- the regular interchip wiring 111A is selected for transmission between the circuit 100A and the circuit 100B, and the transmission between the circuit ⁇ ' and the circuit 100B 'is preliminarily selected.
- the interchip wiring 121 is selected. Further, when both the regular interchip wiring 111A and the regular interchip wiring 111A ′ are normal, these are selected, and the spare interchip wiring 121 is not selected as a route.
- the force required to have two regular inter-chip wirings may be increased even if the determination circuit is arranged for each inter-chip wiring.
- a spare inter-chip wiring may be increased, but in that case, a function for selecting which spare inter-chip wiring is used at the time of switching the redundant relief is added.
- the force between the chip and the wiring that penetrates the chip is connected to the wiring between the chips.
- the wiring may be flip chip bonded with the I / O signal pads facing each other.
- a configuration in which a plurality of chips are stacked one above the other is used.
- a configuration in which the chips are arranged horizontally may be used.
- the stacked semiconductor device of this example has five stacked chips.
- FIG. 12A is a schematic diagram showing the configuration of the stacked semiconductor device of this example.
- FIG. 12B is an enlarged view of the redundant switching portion indicated by a broken line in FIG. 12A.
- the stacked semiconductor device has a configuration in which chip E, chip D, chip C, chip B, and chip A are stacked in the order of lower force. Between each chip, there is one spare interchip interconnect for every four regular interchip interconnects. In FIG. 12A, only between chip A and chip B, the symbols of the regular interchip wiring 112 and the spare interchip wiring 122 are displayed.
- FIG. 12B shows a redundant switching portion between chip C and chip D.
- the regular interchip interconnect 112 between chip C and chip D is connected to the tristate bus in chip C. It is connected to the regular interchip wiring 113 between chip B and chip C through the buffers 60 and 58. Further, it is connected to the regular interchip wiring 114 between the chip D and the chip E via the tristate buffers 62 and 64 in the chip D.
- the spare inter-chip wiring 122 between the chip C and the chip D is connected to the spare inter-chip wiring 123 between the chip B and the chip C via the tristate notches 61 and 59 in the chip C. Further, it is connected to spare interchip wiring 124 between chip D and chip E via tristate buffers 63 and 65 in chip D.
- Chip C is provided with chip C internal wiring 131 that connects the middle point of tristate buffers 60 and 58 and the relay point of tristate buffers 61 and 59.
- chip D a chip D internal wiring 132 for connecting the relay point of the tristate buffers 62 and 64 and the relay point of the tristate buffers 63 and 65 is provided.
- the tri-state buffers 58, 60, 62, and 64 are enabled when the control signal is at a low level.
- Tri-state buffers 59, 61, 63, 65 are enabled when the control signal is high.
- the control signal input to the tristate buffers 58 and 59 is SW1
- the control signal input to the tristate buffers 60 and 61 is SW2.
- the control signal input to the tristate buffer 62, 63 is SW3, and the control signal input to the tristate buffer 64, 65 is SW4.
- the regular interchip interconnect 112 is selected as the path between the chip C and the chip D.
- the spare interchip wiring 122 is selected as a path between the chip C and the chip D. In this way, it is possible to select regular interchip wiring and spare interchip wiring for each chip. If normal interchip wiring between chip C and chip ⁇ and normal interchip wiring between chip D and chip ⁇ are normal, SW1 and SW4 are at low level.
- one of the regular interchip interconnects between chip C and chip D is defective. Exemplify the case of switching.
- FIG. 13 is a diagram showing an example of the redundant relief circuit configuration of chip C and chip D shown in FIG. 12A.
- the regular interchip wiring 112 between the chip C and the chip D is connected to the regular interchip wiring between the chip B and the chip C via the tristate buffers 68 and 66 in the chip C. It is connected to the. Further, it is connected to the regular interchip wiring 114 between the chip D and the chip E through the tristate buffers 70 and 72 in the chip D.
- the spare interchip wiring 122 between the chip C and the chip D is connected to the spare interchip wiring 123 between the chip B and the chip C via the tristate notches 69 and 67 in the chip C. Further, it is connected to the regular interchip wiring 124 between the chip D and the chip E via tristate buffers 73 and 71 in the chip D.
- chip C internal wiring 131 is provided to connect the middle point of tristate buffers 68 and 66 and the relay point of tristate buffers 69 and 67. Chip C internal wiring 131 is connected to circuit C.
- chip C has a flip-flop circuit 79 for determining a test signal of chip D and a test signal generation circuit (not shown) in order to select a route with chip D.
- a tri-state notch 75 for making it possible to select whether or not to send the test signal to the chip D, and a logic gate NOR circuit 83 for preventing the test signal from flowing into other circuits.
- the output terminal of the tristate buffer 75 and the clock input terminal of the flip-flop circuit 79 are connected to the relay point between the regular interchip wiring 112 and the tristate buffer 68.
- the output terminal of the flip-flop circuit 79 is connected to the control signal input terminal of the tristate buffer 69 and the first input terminal of the NOR circuit 83.
- a control signal TE0 different from the control signal TE1 of the tristate buffer 75 is input to the second input terminal of the NOR circuit 83.
- the output terminal of the NOR circuit 83 is connected to the control signal input terminal of the tristate buffer 68.
- the chip C has a free path for route selection with the chip B.
- a flop circuit 78, a tristate buffer 74, and a NOR circuit 82 are provided.
- Chip D has flip-flop circuits 80 and 81, tristate buffers 76 and 77, and NOR circuits 84 and 85 for path selection with chip C and chip E, respectively.
- the tri-state buffers 66 to 77 are enabled when a high-level control signal is input.
- the control signal TE0 is input to the tristate buffers 74 and 76, and the control signal TE1 is input to the tristate buffers 75 and 77.
- a control signal TE1 is input to the NOR circuits 82 and 84, and a control signal TE0 is input to the NOR circuits 83 and 85.
- the output is set to the initial value “1” for the flip-flop circuits 79 and 80 of the test determination circuit for selecting a path between the chip C and the chip D.
- the route of the spare interchip wiring 122 which is not the regular interchip wiring 112 is selected.
- the tristate buffer 75 is enabled by setting the control signal TE0 to low level and the control signal TE1 to noise level.
- the test signal for chip C force is also sent to the regular interchip interconnect 112 via the tri-state buffer 75. If the regular interchip interconnect 112 is normal, the test signal that has passed through the regular interchip interconnect 112 is input to the clock input terminal of the flip-flop circuit 80 in the chip D. In the initial state, the output of the flip-flop circuit 80 is set to “1”, but when the toggle waveform as the test signal is input, the output transitions to the input value “0”. As a result, the tri-state buffer 71 is not enabled, and the connection between the circuit D and the spare interchip wiring 122 is disconnected.
- the toggle waveform is not input to the flip-flop circuit 80, and the flip-flop circuit 80 maintains the output "1".
- the connection state between the circuit D and the spare interchip wiring 122 is maintained while the tristate buffer 71 remains in the enabled state.
- the tri-state buffer 76 is enabled by setting the control signal TE0 to the noise level and the control signal TE1 to the low level.
- Chip D force test signal is tri-stay
- the data is sent to the normal interchip wiring 112 via the data buffer 76.
- the flip-flop circuit 79 of the determination circuit of chip C determines whether or not the test signal is transmitted. If the normal interchip wiring 112 is normal, a toggle waveform as a test signal is input to the clock input terminal of the flip-flop circuit 79. When the toggle waveform as the test signal is input, the flip-flop circuit 79 transitions the output from the initial state “1” to the input value “0”. As a result, the tristate buffer 69 is not enabled, and the connection between the circuit C and the spare interchip wiring 122 is disconnected.
- the toggle waveform is not input to the flip-flop circuit 79, and the output of the flip-flop circuit 79 remains "1".
- the tristate buffer 69 maintains the enabled state, and the connection state between the circuit C and the spare interchip wiring 122 is maintained.
- the path is selected so that the regular interchip wiring 112 between the chip C and the chip D is not used and the preliminary interchip wiring 122 is used.
- defect determination and redundancy switching are performed independently between chips, so that the time required for redundancy relief is not increased even if the number of stacked chips increases! Is possible.
- the test start time is intentionally set on a chip-by-chip basis or on a chip basis in order to reduce the current that flows simultaneously. It may be shifted for each intermediate wiring.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2006800310923A CN101248363B (zh) | 2005-08-23 | 2006-08-22 | 半导体器件、半导体芯片、芯片间互连测试方法以及芯片间互连切换方法 |
JP2007535408A JP5098644B2 (ja) | 2005-08-23 | 2006-08-22 | 半導体装置、および半導体チップ |
US12/064,639 US20090102503A1 (en) | 2005-08-23 | 2006-08-22 | Semiconductor device, semiconductor chip, interchip interconnect test method, and interchip interconnect switching method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005-241039 | 2005-08-23 | ||
JP2005241039 | 2005-08-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2007032184A1 true WO2007032184A1 (ja) | 2007-03-22 |
Family
ID=37864782
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2006/316410 WO2007032184A1 (ja) | 2005-08-23 | 2006-08-22 | 半導体装置、半導体チップ、チップ間配線のテスト方法、および、チップ間配線切り替え方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20090102503A1 (ja) |
JP (1) | JP5098644B2 (ja) |
CN (1) | CN101248363B (ja) |
WO (1) | WO2007032184A1 (ja) |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2010097947A1 (ja) * | 2009-02-27 | 2010-09-02 | 株式会社日立製作所 | 半導体装置 |
JP2011081882A (ja) * | 2009-10-09 | 2011-04-21 | Elpida Memory Inc | 積層型半導体装置 |
JP2011253607A (ja) * | 2010-06-01 | 2011-12-15 | Samsung Electronics Co Ltd | 積層半導体メモリ装置、これを含むメモリシステム及び貫通電極の欠陥リペア方法 |
JP2012160246A (ja) * | 2011-01-31 | 2012-08-23 | Sk Hynix Inc | 半導体メモリ装置及びそのリペア方法 |
JP2012174309A (ja) * | 2011-02-22 | 2012-09-10 | Elpida Memory Inc | 半導体装置及びその試験方法 |
JP2012527130A (ja) * | 2009-05-20 | 2012-11-01 | クアルコム,インコーポレイテッド | シリコン貫通ビア(tsv)冗長性を設けるための方法および装置 |
WO2012169168A1 (ja) * | 2011-06-09 | 2012-12-13 | パナソニック株式会社 | 三次元集積回路、及びそのテスト方法 |
EP2546873A2 (en) | 2011-06-14 | 2013-01-16 | Elpida Memory, Inc. | Semiconductor device |
JP2013088426A (ja) * | 2011-10-18 | 2013-05-13 | Sk Hynix Inc | 半導体装置 |
JP2013531891A (ja) * | 2010-06-17 | 2013-08-08 | モサイド・テクノロジーズ・インコーポレーテッド | シリコン貫通孔を有する半導体デバイス |
JP2013205251A (ja) * | 2012-03-28 | 2013-10-07 | Nec Corp | 接続テスト回路および接続テスト方法 |
JP2014142991A (ja) * | 2014-02-26 | 2014-08-07 | Ps4 Luxco S A R L | 半導体装置 |
JP2015507812A (ja) * | 2011-12-23 | 2015-03-12 | インテル・コーポレーション | 積層メモリアーキテクチャのための自己修復論理 |
JP2015514226A (ja) * | 2012-04-09 | 2015-05-18 | トランスラリティー インコーポレイテッド | テスト用マイクロエレクトロニクス基板の両面に結合可能なトランスレータ、ならびに関連するシステムおよび方法 |
WO2015141153A1 (ja) * | 2014-03-17 | 2015-09-24 | 日本電気株式会社 | プログラマブル論理集積回路 |
EP3029720A1 (en) | 2014-12-02 | 2016-06-08 | Fujitsu Limited | Semiconductor device and method of testing semiconductor device |
JP2016109452A (ja) * | 2014-12-02 | 2016-06-20 | 富士通株式会社 | 試験回路および試験回路の制御方法 |
JP2016122735A (ja) * | 2014-12-25 | 2016-07-07 | 東芝情報システム株式会社 | 半導体装置 |
JP2016125850A (ja) * | 2014-12-26 | 2016-07-11 | 富士通株式会社 | 試験回路および試験回路の制御方法 |
JP2017050040A (ja) * | 2016-09-27 | 2017-03-09 | インテル・コーポレーション | 装置、システム、方法、プログラム、およびコンピュータ可読記憶媒体 |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101384914A (zh) * | 2006-02-23 | 2009-03-11 | 松下电器产业株式会社 | 半导体集成电路及其检查方法 |
US8026726B2 (en) * | 2009-01-23 | 2011-09-27 | Silicon Image, Inc. | Fault testing for interconnections |
US8471582B2 (en) * | 2009-01-27 | 2013-06-25 | Qualcomm Incorporated | Circuit for detecting tier-to-tier couplings in stacked integrated circuit devices |
US8533543B2 (en) * | 2009-03-30 | 2013-09-10 | Infineon Technologies Ag | System for testing connections between chips |
US9304166B2 (en) * | 2010-07-16 | 2016-04-05 | Infineon Technologies Ag | Method and system for wafer level testing of semiconductor chips |
JP5589658B2 (ja) * | 2010-08-12 | 2014-09-17 | 富士通株式会社 | クロック供給装置およびクロック供給方法 |
CN103576072A (zh) * | 2012-07-25 | 2014-02-12 | 联咏科技股份有限公司 | 集成电路及其测试系统 |
KR102058101B1 (ko) * | 2012-12-20 | 2019-12-20 | 에스케이하이닉스 주식회사 | 반도체 집적회로 |
KR20150027894A (ko) * | 2013-08-30 | 2015-03-13 | 에스케이하이닉스 주식회사 | 반도체 장치 |
DE102014014309B4 (de) * | 2014-10-01 | 2018-08-16 | Tdk-Micronas Gmbh | Verfahren zum Testen eines Signalpfades |
KR20170060205A (ko) * | 2015-11-23 | 2017-06-01 | 에스케이하이닉스 주식회사 | 적층형 메모리 장치 및 이를 포함하는 반도체 메모리 시스템 |
KR102637795B1 (ko) * | 2017-02-10 | 2024-02-19 | 에스케이하이닉스 주식회사 | 반도체 장치 |
CN108732489B (zh) * | 2018-08-31 | 2023-09-05 | 长鑫存储技术有限公司 | 测试方法、测试设备、测试载板及测试系统 |
WO2020042906A1 (en) | 2018-08-31 | 2020-03-05 | Changxin Memory Technologies, Inc. | Test methods, tester, load board and test system |
CN116613139B (zh) * | 2023-07-17 | 2023-11-21 | 长鑫存储技术有限公司 | 芯片及芯片堆叠结构 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05157816A (ja) * | 1991-12-04 | 1993-06-25 | Fujitsu Ltd | 実装回路の不良検出回路及び集積回路 |
JPH06249919A (ja) * | 1993-03-01 | 1994-09-09 | Fujitsu Ltd | 半導体集積回路装置の端子間接続試験方法 |
JPH09230002A (ja) * | 1996-02-27 | 1997-09-05 | Fujitsu Ltd | デバイス間接触不良結線検出方法 |
JP2001296330A (ja) * | 2000-04-11 | 2001-10-26 | Fujitsu Ltd | 断線位置検出機能を備えた電子機器及び断線位置検出方法 |
JP2003309183A (ja) * | 2002-04-17 | 2003-10-31 | Toshiba Corp | 半導体システム、半導体システムの接続テスト方法及び半導体システムの製造方法 |
JP2004028885A (ja) * | 2002-06-27 | 2004-01-29 | Fujitsu Ltd | 半導体装置、半導体パッケージ及び半導体装置の試験方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03157956A (ja) * | 1989-11-16 | 1991-07-05 | Fujitsu Ltd | ウエハスケール半導体集積回路装置 |
JPH04253365A (ja) * | 1991-01-29 | 1992-09-09 | Fujitsu Ltd | ウェーハ集積回路 |
US5563507A (en) * | 1994-11-15 | 1996-10-08 | Hughes Aircraft Company | Method of testing the interconnection between logic devices |
US6259309B1 (en) * | 1999-05-05 | 2001-07-10 | International Business Machines Corporation | Method and apparatus for the replacement of non-operational metal lines in DRAMS |
JP4662740B2 (ja) * | 2004-06-28 | 2011-03-30 | 日本電気株式会社 | 積層型半導体メモリ装置 |
JP4534132B2 (ja) * | 2004-06-29 | 2010-09-01 | エルピーダメモリ株式会社 | 積層型半導体メモリ装置 |
JP4063796B2 (ja) * | 2004-06-30 | 2008-03-19 | 日本電気株式会社 | 積層型半導体装置 |
JP4187022B2 (ja) * | 2006-08-23 | 2008-11-26 | ソニー株式会社 | 半導体装置、半導体集積回路およびバンプ抵抗測定方法 |
JP2008249388A (ja) * | 2007-03-29 | 2008-10-16 | Fujitsu Microelectronics Ltd | 半導体装置および半導体装置モジュール |
JP2009134573A (ja) * | 2007-11-30 | 2009-06-18 | Nec Corp | マルチチップ半導体装置およびデータ転送方法 |
-
2006
- 2006-08-22 CN CN2006800310923A patent/CN101248363B/zh not_active Expired - Fee Related
- 2006-08-22 JP JP2007535408A patent/JP5098644B2/ja not_active Expired - Fee Related
- 2006-08-22 US US12/064,639 patent/US20090102503A1/en not_active Abandoned
- 2006-08-22 WO PCT/JP2006/316410 patent/WO2007032184A1/ja active Application Filing
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05157816A (ja) * | 1991-12-04 | 1993-06-25 | Fujitsu Ltd | 実装回路の不良検出回路及び集積回路 |
JPH06249919A (ja) * | 1993-03-01 | 1994-09-09 | Fujitsu Ltd | 半導体集積回路装置の端子間接続試験方法 |
JPH09230002A (ja) * | 1996-02-27 | 1997-09-05 | Fujitsu Ltd | デバイス間接触不良結線検出方法 |
JP2001296330A (ja) * | 2000-04-11 | 2001-10-26 | Fujitsu Ltd | 断線位置検出機能を備えた電子機器及び断線位置検出方法 |
JP2003309183A (ja) * | 2002-04-17 | 2003-10-31 | Toshiba Corp | 半導体システム、半導体システムの接続テスト方法及び半導体システムの製造方法 |
JP2004028885A (ja) * | 2002-06-27 | 2004-01-29 | Fujitsu Ltd | 半導体装置、半導体パッケージ及び半導体装置の試験方法 |
Cited By (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8242589B2 (en) | 2009-02-27 | 2012-08-14 | Hitachi, Ltd. | Semiconductor device |
JP5416200B2 (ja) * | 2009-02-27 | 2014-02-12 | 株式会社日立製作所 | 半導体装置 |
WO2010097947A1 (ja) * | 2009-02-27 | 2010-09-02 | 株式会社日立製作所 | 半導体装置 |
JP2012527130A (ja) * | 2009-05-20 | 2012-11-01 | クアルコム,インコーポレイテッド | シリコン貫通ビア(tsv)冗長性を設けるための方法および装置 |
US8988130B2 (en) | 2009-05-20 | 2015-03-24 | Qualcomm Incorporated | Method and apparatus for providing through silicon via (TSV) redundancy |
JP2011081882A (ja) * | 2009-10-09 | 2011-04-21 | Elpida Memory Inc | 積層型半導体装置 |
JP2011253607A (ja) * | 2010-06-01 | 2011-12-15 | Samsung Electronics Co Ltd | 積層半導体メモリ装置、これを含むメモリシステム及び貫通電極の欠陥リペア方法 |
JP2013531891A (ja) * | 2010-06-17 | 2013-08-08 | モサイド・テクノロジーズ・インコーポレーテッド | シリコン貫通孔を有する半導体デバイス |
US9030024B2 (en) | 2010-06-17 | 2015-05-12 | Conversant Intellectual Property Management Inc. | Semiconductor device with through-silicon vias |
JP2012160246A (ja) * | 2011-01-31 | 2012-08-23 | Sk Hynix Inc | 半導体メモリ装置及びそのリペア方法 |
JP2012174309A (ja) * | 2011-02-22 | 2012-09-10 | Elpida Memory Inc | 半導体装置及びその試験方法 |
WO2012169168A1 (ja) * | 2011-06-09 | 2012-12-13 | パナソニック株式会社 | 三次元集積回路、及びそのテスト方法 |
US9267986B2 (en) | 2011-06-09 | 2016-02-23 | Panasonic Intellectual Property Management Co., Ltd. | Three-dimensional integrated circuit and testing method for the same |
US9121894B2 (en) | 2011-06-09 | 2015-09-01 | Panasonic Intellectual Property Management Co., Ltd. | Three-dimensional integrated circuit and testing method for the same |
EP2546873A2 (en) | 2011-06-14 | 2013-01-16 | Elpida Memory, Inc. | Semiconductor device |
US9035444B2 (en) | 2011-06-14 | 2015-05-19 | Ps4 Luxco S.A.R.L. | Semiconductor device having penetration electrodes penetrating through semiconductor chip |
JP2013088426A (ja) * | 2011-10-18 | 2013-05-13 | Sk Hynix Inc | 半導体装置 |
US10224115B2 (en) | 2011-12-23 | 2019-03-05 | Intel Corporation | Self-repair logic for stacked memory architecture |
JP2015507812A (ja) * | 2011-12-23 | 2015-03-12 | インテル・コーポレーション | 積層メモリアーキテクチャのための自己修復論理 |
US9646720B2 (en) | 2011-12-23 | 2017-05-09 | Intel Corporation | Self-repair logic for stacked memory architecture |
JP2013205251A (ja) * | 2012-03-28 | 2013-10-07 | Nec Corp | 接続テスト回路および接続テスト方法 |
JP2015514226A (ja) * | 2012-04-09 | 2015-05-18 | トランスラリティー インコーポレイテッド | テスト用マイクロエレクトロニクス基板の両面に結合可能なトランスレータ、ならびに関連するシステムおよび方法 |
JP2014142991A (ja) * | 2014-02-26 | 2014-08-07 | Ps4 Luxco S A R L | 半導体装置 |
JPWO2015141153A1 (ja) * | 2014-03-17 | 2017-04-06 | 日本電気株式会社 | プログラマブル論理集積回路 |
WO2015141153A1 (ja) * | 2014-03-17 | 2015-09-24 | 日本電気株式会社 | プログラマブル論理集積回路 |
US9692422B2 (en) | 2014-03-17 | 2017-06-27 | Nec Corporation | Programmable logic integrated circuit |
JP2016109439A (ja) * | 2014-12-02 | 2016-06-20 | 富士通株式会社 | 半導体装置および半導体装置の試験方法 |
JP2016109452A (ja) * | 2014-12-02 | 2016-06-20 | 富士通株式会社 | 試験回路および試験回路の制御方法 |
US9746878B2 (en) | 2014-12-02 | 2017-08-29 | Fujitsu Limited | Semiconductor device and method of testing semiconductor device |
EP3029720A1 (en) | 2014-12-02 | 2016-06-08 | Fujitsu Limited | Semiconductor device and method of testing semiconductor device |
JP2016122735A (ja) * | 2014-12-25 | 2016-07-07 | 東芝情報システム株式会社 | 半導体装置 |
JP2016125850A (ja) * | 2014-12-26 | 2016-07-11 | 富士通株式会社 | 試験回路および試験回路の制御方法 |
JP2017050040A (ja) * | 2016-09-27 | 2017-03-09 | インテル・コーポレーション | 装置、システム、方法、プログラム、およびコンピュータ可読記憶媒体 |
Also Published As
Publication number | Publication date |
---|---|
JP5098644B2 (ja) | 2012-12-12 |
CN101248363B (zh) | 2012-01-18 |
JPWO2007032184A1 (ja) | 2009-03-19 |
US20090102503A1 (en) | 2009-04-23 |
CN101248363A (zh) | 2008-08-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5098644B2 (ja) | 半導体装置、および半導体チップ | |
US9222977B2 (en) | Semiconductor test system and method | |
US8242589B2 (en) | Semiconductor device | |
US7725781B2 (en) | Repair techniques for memory with multiple redundancy | |
JPH01501033A (ja) | 素早い注文設計及び独特な試験能力の為の集積回路パッケージ形式 | |
JP2003309183A (ja) | 半導体システム、半導体システムの接続テスト方法及び半導体システムの製造方法 | |
TW201025543A (en) | Systems and methods utilizing redundancy in semiconductor chip interconnects | |
US20080048706A1 (en) | Semiconductor device, semiconductor integrated circuit and bump resistance measurement method | |
JP3617831B2 (ja) | 積層配線構造をもつ半導体集積回路の製造方法 | |
Huang et al. | Built-in self-test/repair scheme for TSV-based three-dimensional integrated circuits | |
JP2004264057A (ja) | バウンダリスキャンコントローラ、半導体装置、半導体装置の半導体回路チップ識別方法、半導体装置の半導体回路チップ制御方法 | |
JP2002064142A (ja) | 半導体集積回路 | |
US20030229831A1 (en) | Pad connection structure of embedded memory devices and related memory testing method | |
JPH08101255A (ja) | マルチチップモジュール | |
Maity et al. | Built-in self-repair for manufacturing and runtime TSV defects in 3D ICs | |
KR100746228B1 (ko) | 반도체 메모리 모듈 및 반도체 메모리 장치 | |
Yang et al. | A TSV repair scheme using enhanced test access architecture for 3-D ICs | |
US20230307420A1 (en) | Stack type semiconductor device and method of testing the stack type semiconductor device | |
US12009043B2 (en) | Integrated circuit chip and die test without cell array | |
US20070300107A1 (en) | Device test apparatus | |
Huang et al. | On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs | |
CN115241664A (zh) | 电连接结构的修复电路及其控制方法 | |
JPH0888280A (ja) | ウェハスケール集積装置とその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200680031092.3 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
ENP | Entry into the national phase |
Ref document number: 2007535408 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 12064639 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 06796624 Country of ref document: EP Kind code of ref document: A1 |