JP2013030534A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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Abstract
【解決手段】基板1の第1の主面に、俯瞰形状が環状となる第1の溝部2Tを形成し、第1の主面全面に第1の絶縁膜2aを形成し、第1の絶縁膜2aの表面から前記第1の溝部の内部まで達する深さの空孔を残しつつ、前記第1の絶縁膜を第1の溝部に埋め込み、空孔内を埋め込むように第1の絶縁膜上に第2の絶縁膜を形成し、第1の溝部内に第1の絶縁膜および第2の絶縁膜を残しつつ、基板表面高さまで化学機械研磨法により平坦化する。
【選択図】図1−2
Description
基板の第1の主面に、俯瞰形状が環状となる第1の溝部を形成する工程と、
前記第1の主面全面に第1の絶縁膜を形成し、前記第1の絶縁膜の表面から前記第1の溝部の内部まで達する深さの空孔を残しつつ、前記第1の絶縁膜を前記第1の溝部に埋め込む工程と、
前記空孔内を埋め込むように前記第1の絶縁膜上に第2の絶縁膜を形成する工程と、
前記第1の溝部内に前記第1の絶縁膜および前記第2の絶縁膜を残しつつ、前記基板表面高さまで化学機械研磨法により平坦化する工程と、
を有することを特徴とする半導体装置の製造方法、が提供される。
半導体基板の第1の主面に形成された素子形成領域と、
前記半導体基板の第1の主面から対向する第2の主面に貫通し、俯瞰形状が環状である絶縁分離部と、
前記環状の絶縁分離部に囲まれた前記半導体基板の第1の主面から対向する第2の主面に貫通し、前記第1の主面及び第2の主面の外部に露出する端子を有する貫通電極と、
を備えた半導体装置であって、
前記環状の絶縁分離部は、前記第1の主面から第2の主面にかけて埋め込まれた第1の絶縁膜と、前記第1の絶縁膜の前記第1の主面側から所定の深さに形成された環状の空孔内に埋設された第2の絶縁膜と、
を有する半導体装置、が提供される。
図1は、本発明が適用されるTSV構造を備えた半導体装置(半導体チップ50)の一例を示すもので、(a)はTSV構造部分を示す概略断面図、(b)、(c)は半導体チップ50の第1の主面側と第2の主面側の概略平面図をそれぞれ示す。図1(a)は(b)、(c)のA1−A1での断面図に相当する。図1(d)は図1(a)のP1部分の拡大図、図1(e)、(f)はそれぞれ、図1(a)のZ1−Z1、Z2−Z2での水平断面図に相当する。
また、第1の実施形態例では、絶縁リング2として1重のリング構造の場合について説明しているが、これに限定されず、多重リング構造としても良い。例えば、図15(図15−1及び図15−2)は、2重のリング構造とした半導体チップ60の概略断面図(a)とP2部分の部分拡大図(b)、Z1−Z1での横断面図(c)を示している。絶縁リングは、内側の絶縁リング2Aと外側の絶縁リング2Bとからなり、それぞれの第1の主面では第2の絶縁膜2bが絶縁リングの幅の中央部の溝状のスリット(空孔)内に形成される。
以上の実施形態例では、絶縁リング用の溝の形状として、垂直形状の溝(TSVトレンチ)2Tを形成しているが、近年の半導体装置の微細化に伴い、TSVトレンチの開口サイズが縮小され、開口のアスペクト比がさらに増加する傾向にある。このため、垂直形状のTSVトレンチに第1の絶縁膜2aをCVD法等で充填する際、開口の上部で堆積した第1の絶縁膜2a同士が接触し、その下方に空洞(ボイド)が残存する現象が起きやすい。このようなボイドが発生すると、シーム2Sでの接合力が低下し、絶縁リングで囲まれた領域が孤立し易くなり、後の製造工程において、層間絶縁膜6等にクラック等が発生する原因となり易くなる。そこで、TSVトレンチの開口上端部をテーパー形状に加工することが有効である。
上記実施形態例1では、半導体基板1の第1の主面に第2の絶縁膜2bとしてBPSG膜などの不純物を含有する絶縁膜が露出している。このように不純物を含む絶縁膜が第1の主面に露出していると、その後の素子形成工程において、ボロン(B)やリン(P)等の不純物が外方拡散し、製膜装置内汚染や、ゲート酸化膜への拡散が生じ、電気特性変動や信頼性に影響を及ぼす場合がある。そこで、本実施形態例2ではこのような不純物の外方拡散を防止する手法について説明する。
この半導体チップ80の製造工程について、図19〜22を参照して説明する。
2 絶縁リング
2a 第1の絶縁膜(TEOS−NSG膜)
2b 第2の絶縁膜(BPSG膜)
2S シーム
2ST スリット
3 ハードマスク層
4 保護膜
5 半導体素子
6 層間絶縁膜
7 配線構造
8 表面保護膜
8a 窒化シリコン膜
8b パッシベーション膜(ポリイミド膜)
9 金属シード層
10 レジストパターン
11 Cu膜
12 Ni/Au膜
13 バンプ電極
14 接着剤層
15 光熱変換層
16 基板サポートシステム
17 裏面保護膜
18 金属シード層
19 フォトレジスト膜
20 Cuプラグ
21 半田膜
22 TSV
23 貫通電極
24 アンダーフィル樹脂
25 モールド樹脂
26 パッケージ基板
27 BGA
30 STI
31 第3の絶縁膜(窒化シリコン膜)
32 第4の絶縁膜(酸化シリコン膜)
33 拡散層
34 コンタクトプラグ
50,60,70,80 半導体チップ
100 半導体モジュール
Claims (20)
- 基板の第1の主面に、俯瞰形状が環状となる第1の溝部を形成する工程と、
前記第1の主面全面に第1の絶縁膜を形成し、前記第1の絶縁膜の表面から前記第1の溝部の内部まで達する深さの空孔を残しつつ、前記第1の絶縁膜を前記第1の溝部に埋め込む工程と、
前記空孔内を埋め込むように前記第1の絶縁膜上に第2の絶縁膜を形成する工程と、
前記第1の溝部内に前記第1の絶縁膜および前記第2の絶縁膜を残しつつ、前記基板表面高さまで化学機械研磨法により平坦化する工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記第2の絶縁膜を形成する工程では、
化学気相成長法により前記第2の絶縁膜としてホウ素、リン、または、それら両方を含む酸化シリコン膜を堆積した後、該堆積した第2の絶縁膜をリフローすることで、前記空孔上部の前記第2の絶縁膜の表面位置を前記空孔周辺上の前記第2の絶縁膜の表面位置に近づけることを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記第1の絶縁膜を形成する工程では、
化学気相成長法により、不純物を含有しない酸化シリコン膜を前記第1の溝部内に前記第1の絶縁膜として堆積した後、熱処理を施すことで、前記第1の絶縁膜から脱ガスする工程を有することを特徴とする請求項1または2に記載の半導体装置の製造方法。 - 前記第2の絶縁膜を形成する前に、前記第1の絶縁膜上に、前記空孔を覆うように保護膜を形成する工程と、
前記保護膜をマスクとしてウェットエッチングを施すことで、前記保護膜に覆われていない部分の前記第1の絶縁膜を除去する工程と
を有する請求項1〜3のいずれか1項に記載の半導体装置の製造方法。 - 前記化学機械研磨法により平坦化する工程の後、
前記空孔内の前記第2の絶縁膜を一部除去することで、底部に前記第2の絶縁膜が露出したリセス部を形成する工程と、
前記リセス部の底部に露出した前記第2の絶縁膜を覆うように、窒化シリコンを主体とする第3の絶縁膜を形成する工程と、
を更に有することを特徴とする請求項1〜4のいずれか1項に記載の半導体装置の製造方法。 - 前記リセス部を形成する工程の後、前記第3の絶縁膜を形成する工程の前に、
前記基板の第1の主面に素子分離用の溝部を形成する工程を更に有し、
前記第3の絶縁膜を形成する工程では、前記リセス部内に加えて前記素子分離用の溝部内にも前記第3の絶縁膜を形成することを特徴とする請求項5に記載の半導体装置の製造方法。 - 前記第3の絶縁膜を形成する工程の後、
前記リセス部の前記第3の絶縁膜上と、前記素子分離用の溝部の前記第3の絶縁膜上とに、酸化シリコンを主体とする第4の絶縁膜を形成する工程を更に有することを特徴とする請求項6に記載の半導体装置の製造方法。 - 前記化学機械研磨法により平坦化する工程の後、
前記基板の第1の主面に半導体素子を形成する工程と、
前記基板を、前記基板の第1の主面と厚さ方向に対向する第2の主面側から、前記第2の主面に前記第1の絶縁膜が露出するまで研削して薄板化する工程と、
環状の前記第1の溝部の内側に位置する前記基板を厚さ方向に貫通するように、前記第2の主面側から貫通電極を形成する工程と、
を更に有することを特徴とする請求項1〜7に記載のいずれか1項に記載の半導体装置の製造方法。 - 前記第1の溝部を形成する工程は、基板の前記主面からその厚み方向の内側に向かって1以上のテーパーとなる第2の溝部を形成する工程と、
前記第2の溝の底部から所定の深さまで垂直形状の溝部を形成する工程とを含む請求項1〜8のいずれか1項に記載の半導体装置の製造方法。 - 半導体基板の第1の主面に形成された素子形成領域と、
前記半導体基板の第1の主面から対向する第2の主面に貫通し、俯瞰形状が環状である絶縁分離部と、
前記環状の絶縁分離部に囲まれた前記半導体基板の第1の主面から対向する第2の主面に貫通し、前記第1の主面及び第2の主面の外部に露出する端子を有する貫通電極と、
を備えた半導体装置であって、
前記環状の絶縁分離部は、前記第1の主面から第2の主面にかけて埋め込まれた第1の絶縁膜と、前記第1の絶縁膜の前記第1の主面側から所定の深さに形成された環状の空孔内に埋設された第2の絶縁膜と、
を有することを特徴とする半導体装置。 - 前記第2の絶縁膜は、ホウ素、リン、または、それら両方を含む酸化シリコンを主体とする絶縁膜であることを特徴とする請求項10に記載の半導体装置。
- 前記第2の絶縁膜は前記第1の主面がなす平面から後退して埋設されており、前記第1の主面が成す平面から前記第2の絶縁膜を離間するように配置された、窒化シリコンを主体とする第3の絶縁膜を更に有することを特徴とする請求項10または11に記載の半導体装置。
- 前記基板の第1の主面に形成され、前記基板上に前記素子形成領域を規定する素子分離部を更に有し、
前記素子分離部は、前記第3の絶縁膜と同じ組成の絶縁膜を含んでいることを特徴とする請求項12に記載の半導体装置。 - 前記環状の絶縁分離部は、前記第1の主面が成す平面と前記第3の絶縁膜との間に配置された、酸化シリコンを主体とする第4の絶縁膜を更に有し、
前記素子分離部は、前記第4の絶縁膜と同じ組成の絶縁膜を更に含んでいることを特徴とする請求項13に記載の半導体装置。 - 前記環状の絶縁分離部は、少なくとも前記貫通電極の周囲に配置された第1の絶縁分離部と、該第1の絶縁分離部の周囲に配置された第2の絶縁分離部とを有する請求項10〜14のいずれか1項に記載の半導体装置。
- 前記環状の絶縁分離部は、前記第1の主面近傍において第1の主面での幅が第1の主面から所定の深さでの幅よりも広いテーパー形状を有する請求項10〜15のいずれか1項に記載の半導体装置。
- 前記貫通電極は、前記半導体基板を前記第2の主面から第1の主面に貫通する銅を主体とするプラグを有する請求項10〜16のいずれか1項に記載の半導体装置。
- 前記貫通電極の前記第1の主面及び第2の主面のいずれか一方の外部に露出する端子は表面に導電性の保護膜を有し、他方に露出する端子は表面に半田膜を有する請求項17に記載の半導体装置。
- 前記貫通電極は、前記第2の主面の外部に露出する端子が前記銅を主体とするプラグと一体に形成されており、前記第1の主面側において、外部に露出する銅を主体とするバンプ構造の端子と前記プラグとが前記第1の主面上に形成された層間絶縁膜中の配線構造により電気的に接続されていることを特徴とする請求項17又は18に記載の半導体装置。
- 請求項10〜19のいずれか1項に記載の半導体装置の複数を積層し、前記貫通電極により相互に接続した半導体装置。
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