JP6509635B2 - 半導体装置、及び、半導体装置の製造方法 - Google Patents

半導体装置、及び、半導体装置の製造方法 Download PDF

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JP6509635B2
JP6509635B2 JP2015110745A JP2015110745A JP6509635B2 JP 6509635 B2 JP6509635 B2 JP 6509635B2 JP 2015110745 A JP2015110745 A JP 2015110745A JP 2015110745 A JP2015110745 A JP 2015110745A JP 6509635 B2 JP6509635 B2 JP 6509635B2
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semiconductor device
metal
layer
hole
electrode
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JP2016225472A (ja
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達夫 右田
達夫 右田
浩二 小木曽
浩二 小木曽
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Kioxia Corp
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Toshiba Memory Corp
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Priority to JP2015110745A priority Critical patent/JP6509635B2/ja
Priority to TW104138097A priority patent/TWI611487B/zh
Priority to CN201510848901.0A priority patent/CN106206501B/zh
Priority to US15/061,993 priority patent/US10312143B2/en
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Description

本発明の実施形態は、半導体装置、及び、半導体装置の製造方法に関する。
基板に形成された貫通孔に設けられた貫通電極として機能する金属部材を備えた半導体装置が知られている。更に、金属部材に空洞が形成された半導体装置が開示されている。
特開２０１２−１４２４１４号公報
しかしながら、空洞が形成されることによって、金属部材に形成された亀裂が広がりやすいといった課題がある。
本発明の実施形態は、上記に鑑みてなされたものであって、空洞が形成された金属部材の亀裂が広がることを低減できる半導体装置及び半導体装置の製造方法を提供することを目的とする。
上述した課題を解決し、目的を達成するために、実施形態によれば、半導体装置は、半導体基板と、金属部材と、金属酸化膜とを備える。半導体基板は、一方の面から対向する他方の面に貫通した貫通孔が形成されている。金属部材は、貫通孔の内側に設けられ、内部に空洞が形成されている。金属酸化膜は、金属部材と空洞との間に形成されている。金属部材は、ニッケルを主成分とする。金属酸化膜は、金属部材に含まれる金属材料の酸化物を含む。
図１は、実施形態の半導体装置の縦断面図である。 図２は、半導体装置の製造方法を説明する工程図である。 図３は、半導体装置の製造方法を説明する工程図である。 図４は、半導体装置の製造方法を説明する工程図である。 図５は、半導体装置の製造方法を説明する工程図である。 図６は、半導体装置の製造方法を説明する工程図である。 図７は、半導体装置の製造方法を説明する工程図である。 図８は、半導体装置の製造方法を説明する工程図である。 図９は、半導体装置の製造方法を説明する工程図である。 図１０は、半導体装置の製造方法を説明する工程図である。 図１１は、半導体装置の製造方法を説明する工程図である。
以下の例示的な実施形態や変形例には、同様の構成要素が含まれている。よって、以下では、同様の構成要素には共通の符号が付されるとともに、重複する説明が部分的に省略される。実施形態や変形例に含まれる部分は、他の実施形態や変形例の対応する部分と置き換えて構成されることができる。また、実施形態や変形例に含まれる部分の構成や位置等は、特に言及しない限りは、他の実施形態や変形例と同様である。
＜実施形態＞
図１は、実施形態の半導体装置１０の縦断面図である。半導体装置１０は、ＴＳＶ（Through-Silicon Via）を有する。
図１に示すように、半導体装置１０は、基板１２と、デバイス部１４と、配線層１６と、層間絶縁層１８と、第１パッシベーション層２０と、第２パッシベーション層２２と、電極パッド２４と、第１絶縁層２６と、第２絶縁層２８と、第３絶縁層３０と、貫通電極３２とを備える。
基板１２は、半導体を主成分とする。例えば、基板１２は、シリコンを主成分とする。基板１２の厚みの一例は、２５μｍ〜３５μｍである。基板１２には、貫通孔４０が形成されている。貫通孔４０は、基板１２の一方の面４２から対向する他方の面４４にわたって形成されている。即ち、貫通孔４０は、基板１２を貫通する。貫通孔４０は、平面視において、例えば、円形状である。従って、貫通孔４０は、円柱形状である。平面視における貫通孔４０の直径の一例は、１０μｍである。
デバイス部１４は、トランジスタ等の半導体素子を有する。デバイス部１４は、基板１２の他方の面に設けられている。デバイス部１４には、図示しないゲート電極層を有している。
配線層１６は、基板１２と反対側のデバイス部１４の部分に設けられている。配線層１６は、デバイス部１４の半導体素子と電気的に接続されている。配線層１６は、導電性の材料を含む。例えば、配線層１６は、タングステン、ニッケルシリサイド、コバルトシリサイド、銅、アルミニウム、ボロンがドープされたポリシリコン等を主成分とする。なお、図１では、配線層１６を１層のみを図示しているが、複数の配線層を有する多層配線構造を有していてもよい。
層間絶縁層１８は、基板１２の他方の面４４、デバイス部１４及び配線層１６の少なくとも一部を被覆して、デバイス部１４及び配線層１６が電気的に接続された領域等を除き絶縁する。層間絶縁層１８は、絶縁性の材料を主成分とする。例えば、層間絶縁層１８は、シリコン酸化膜を用いて形成される。
第１パッシベーション層２０は、層間絶縁層１８の少なくとも一部を被覆する。第１パッシベーション層２０は、第２パッシベーション層２２を透過する外気に含まれる水分等から配線層１６を保護する。第１パッシベーション層２０は、シリコン窒化膜を用いて形成される。
第２パッシベーション層２２は、第１パッシベーション層２０の少なくとも一部を被覆する。第２パッシベーション層２２は、デバイス部１４等を保護する。第２パッシベーション層２２は、絶縁性の樹脂等によって形成される。例えば、第２パッシベーション層２２は、ポリイミド樹脂を主成分とする。
電極パッド２４は、配線層１６と電気的に接続されている。電極パッド２４の一部は、第２パッシベーション層２２から露出している。電極パッド２４は、他の半導体装置１０の貫通電極３２等と電気的に接続される。電極パッド２４は、バリアメタル層５０と、シード層５２と、電極本体５４と、電極接続部５６とを有する。
バリアメタル層５０は、配線層１６の一部を被覆する。バリアメタル層５０は、配線層１６と電気的に接続されている。バリアメタル層５０は、電極本体５４を構成する金属材料が層間絶縁層１８等に拡散することを抑制する。バリアメタル層５０は、チタン（Ｔｉ）等の金属材料を主成分とする。
シード層５２は、バリアメタル層５０の内周面を被覆する。シード層５２は、電極本体５４を構成する金属材料がメッキされる際にシードとなる材料を主成分とする。シード層５２は、例えば、銅（Ｃｕ）を主成分とする。
電極本体５４は、シード層５２の内側を埋めるように形成されている。電極本体５４は、導電性の材料を主成分とする。電極本体５４は、例えば、ニッケル（Ｎｉ）を主成分とする。尚、電極本体５４は、銅（Ｃｕ）、金（Ａｕ）、銀（Ａｇ）、コバルト（Ｃｏ）、パラジウム（Ｐｄ）、タングステン（Ｗ）、タンタル（Ｔａ）、Ｐｔ（白金）、Ｒｈ（ロジウム）、Ｉｒ（イリジウム）、Ｒｕ（ルテニウム）、Ｏｓ（オスミウム）、Ｒｅ（レニウム）、Ｍｏ（モリブデン）、Ｎｂ（ニオブ）、Ｂ（ホウ素）、Ｈｆ（ハフニウム）のうち、少なくとも１種類の金属を含む材料によって形成してもよい。
電極接続部５６は、バリアメタル層５０を覆う面とは反対側の電極本体５４の面を覆う。電極接続部５６は、導電性の材料を主成分とする。電極接続部５６は、例えば、金（Ａｕ）を主成分とする。
第１絶縁層２６は、基板１２の一方の面４２の少なくとも一部を被覆する。第１絶縁層２６は、絶縁性の材料を主成分とする。例えば、第１絶縁層２６は、シリコン酸化膜を主成分とする。第１絶縁層２６は、基板１２の一方の面を電気的に絶縁する。
第２絶縁層２８は、基板１２と接する面とは反対側の第１絶縁層２６の面の少なくとも一部を被覆する。第２絶縁層２８は、絶縁性の材料を主成分とする。例えば、第２絶縁層２８は、シリコン窒化膜によって形成される。
第３絶縁層３０は、第１絶縁層２６と接する面とは反対側の第２絶縁層２８の面、及び、基板１２の貫通孔４０の側面を被覆する。第３絶縁層３０は、絶縁性の材料を主成分とする。例えば、第３絶縁層３０は、シリコン酸化膜によって形成される。
貫通電極３２は、金属層の一例であるバリアメタル層６０と、金属層の一例であるシード層６２と、金属部材の一例であるビア電極６４と、金属酸化膜６６と、電極接続部６８を有する。
バリアメタル層６０は、一方の面４２に形成された貫通孔４０の開口の周りに形成された第３絶縁層３０、貫通孔４０の内部に形成された第３絶縁層３０の内面を被覆する。また、バリアメタル層６０は、他方の面４４の貫通孔４０の開口を塞ぐように形成されている。バリアメタル層６０は、デバイス部１４に含まれるゲート電極層と電気的に接続されている。バリアメタル層６０は、シード層６２を構成する金属材料が第３絶縁層３０等に拡散することを抑制する。バリアメタル層６０は、チタン（Ｔｉ）等の金属材料を主成分とする。
シード層６２は、バリアメタル層６０の内周面を被覆する。換言すれば、シード層６２は、一方の面４２に形成された貫通孔４０の開口の周りと、貫通孔４０の内面に形成されている。シード層６２は、ビア電極６４を構成する金属材料がメッキされる際にシードとなる材料を主成分とする。シード層６２は、例えば、銅（Ｃｕ）を主成分とする。
ビア電極６４は、シード層６２上に形成されている。ビア電極６４は、貫通孔４０の内側に設けられている。即ち、ビア電極６４は、貫通孔４０を埋めるように形成されている。ビア電極６４の一部は、一方の面４２に形成された貫通孔４０の開口から突出している。ビア電極６４は、導電性の材料を主成分とする。ビア電極６４は、例えば、ニッケル（Ｎｉ）を主成分とする。ビア電極６４は、銅（Ｃｕ）、銀（Ａｇ）、コバルト（Ｃｏ）、タングステン（Ｗ）、タンタル（Ｔａ）、Ｒｈ（ロジウム）、Ｉｒ（イリジウム）、Ｒｕ（ルテニウム）、Ｏｓ（オスミウム）、Ｒｅ（レニウム）、Ｍｏ（モリブデン）、Ｎｂ（ニオブ）、Ｂ（ホウ素）、Ｈｆ（ハフニウム）のうち、少なくとも１種類の金属を含む材料によって形成してもよい。ビア電極６４の内側には、空洞６７が形成されている。空洞６７は、ビア電極６４内に発生する応力を緩和する。
金属酸化膜６６は、ビア電極６４と空洞６７との間に形成されている。換言すれば、金属酸化膜６６は、ビア電極６４が空洞６７と接する面の少なくとも一部を被覆する。金属酸化膜６６は、ビア電極６４を構成する金属材料を含む金属酸化物を主成分とする。例えば、金属酸化膜６６は、ビア電極６４を構成するニッケルを含むニッケル酸化物を主成分とする。
電極接続部６８は、一方の面４２に形成された貫通孔４０の開口から突出したビア電極６４の部分に形成されている。電極接続部６８は、導電性の材料を主成分とする。電極接続部６８は、電極パッド２４の電極接続部５６と容易に接続できる導電性の材料で構成することが好ましい。例えば、電極接続部６８は、スズ（Ｓｎ）または銅（Ｃｕ）を主成分とする。
図２から図１１は、半導体装置１０の製造方法を説明する工程図である。図２から図１１を参照して、半導体装置１０の製造方法について説明する。本実施形態の製造方法は、貫通電極３２をデバイス部１４よりも後に作成するビアラスト方式である。
図２に示すように、半導体装置１０の製造方法では、基板１２の他方の面４４にデバイス部１４と、配線層１６と、層間絶縁層１８と、第１パッシベーション層２０と、第２パッシベーション層２２と、電極パッド２４とを形成する。次に、基板１２の一方の面４２を機械的研磨法等によって研磨して、基板１２を例えば３０μｍ程度の厚みにする。研磨をした後、基板１２の一方の面４２にシリコン酸化膜を用いた第１絶縁層２６をＣＶＤ（Chemical Vapor Deposition）法によって形成する。次に、第１絶縁層２６上にシリコン窒化膜を用いた第２絶縁層２８をＣＶＤ法によって形成する。
図３に示すように、第１絶縁層２６、第２絶縁層２８、及び、基板１２を、マスクを使用したＲＩＥ（Reactive Ion Etching）法によってエッチングする。これにより、基板１２の一方の面４２から他方の面４４まで貫通した貫通孔４０を基板１２に形成する。
図４に示すように、第２絶縁層２８、貫通孔４０の側面、及び、貫通孔４０の他方の面側の開口から露出したデバイス部１４の領域に、ＣＶＤ法によってシリコン酸化膜を用いた第３絶縁層３０を形成する。
図５に示すように、デバイス部１４に形成された第３絶縁層３０をドライエッチング等のエッチングによって除去する。これにより、デバイス部１４が貫通孔４０に露出する。
図６に示すように、第３絶縁層３０、及び、貫通孔４０の他方の面側の開口から露出したデバイス部１４の領域に、チタンを用いたバリアメタル層６０を真空蒸着法またはスパッタ法によって形成する。次に、バリアメタル層６０上に銅を用いたシード層６２を真空蒸着法またはスパッタ法によって形成する。
図７に示すように、貫通孔４０の内側以外の領域、及び、貫通孔４０の一方の面４２側の開口の周囲以外の領域のシード層６２上にレジスト膜７０をフォトリソグラフィーによって形成する。
図８に示すように、レジスト膜７０から露出しているシード層６２にコンフォーマルめっきによってニッケルを用いたビア電極６４を形成する。ビア電極６４は形成されるにつれて、貫通孔４０の内側におけるビア電極６４が形成されていない領域の他方の面４４側の幅が、一方の面４２側の幅に比べて小さくなる。換言すれば、貫通孔４０の内側に形成されるビア電極６４の一方の面４２側の開口が、他方の面４４側のビア電極６４の形成されていない領域の幅よりも速く小さくなる。
図９に示すように、コンフォーマルめっきを継続することによって、ビア電極６４の内側に空洞６７が形成された状態で、ビア電極６４の一方の面４２側の開口が塞がれる。これにより、内部に空洞６７が形成されたビア電極６４が貫通孔４０の内側に形成される。尚、ビア電極６４の形成は、コンフォーマルめっきに限定されないが、処理時間の短縮及び選択可能なめっき種の多さからコンフォーマルめっきが好ましい。
図１０に示すように、少なくともビア電極６４を加熱することによって、ビア電極６４と空洞６７との間にニッケル酸化物を含む金属酸化膜６６を形成する。例えば、２００°から２５０°の温度で、数分から数時間程度加熱する。これにより、ビア電極６４を構成するニッケル等の金属が、空洞６７内に閉じ込められためっき液中の水分等によって酸化される。これにより、金属酸化膜６６がビア電極６４と空洞６７との間に形成される。
図１１に示すように、レジスト膜７０から露出しているビア電極６４にスズを用いた電極接続部６８を形成する。この後、レジスト膜７０を除去するとともに、表面張力を利用して電極接続部６８を曲面状に変形させる。
上述したように、半導体装置１０では、ビア電極６４とビア電極６４の内部に形成された空洞６７との間に金属酸化膜６６が形成されている。これにより、金属酸化膜６６がビア電極６４を補強しているので、ビア電極６４に熱や機械的なストレスが長期間に渡って加わった場合にビア電極６４に亀裂が発生しても、半導体装置１０はビア電極６４の亀裂が広がることを抑制できる。
半導体装置１０では、ビア電極６４を構成する金属を含む金属酸化物によって金属酸化膜６６を構成しているので、ビア電極６４を加熱することによって金属酸化膜６６を容易に形成することができる。
上述した実施形態は適宜変更してよい。
例えば、上述の実施形態では、半導体装置１０の製造方法として、ビアラスト方式を適用したが、ビアファスト方式等の他の製造方法によって半導体装置を製造してもよい。
本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。
１０…半導体装置、１２…基板、１４…デバイス部、１６…配線層、１８…層間絶縁層、２０…第１パッシベーション層、２２…第２パッシベーション層、２４…電極パッド、２６…第１絶縁層、２８…第２絶縁層、３０…第３絶縁層、３２…貫通電極、４０…貫通孔、６０…バリアメタル層（金属層）、６２…シード層（金属層）、６４…ビア電極（金属部材）、６６…金属酸化膜、６７…空洞、６８…電極接続部

Claims (4)

  1. 一方の面から対向する他方の面に貫通した貫通孔を有する半導体基板と、
    前記貫通孔の内側に設けられ、内部に空洞を有する金属部材と、
    前記金属部材と前記空洞との間に設けられた金属酸化膜と、
    を備え、
    前記金属部材は、ニッケルを主成分とし、
    前記金属酸化膜は、前記金属部材に含まれる金属材料の酸化物を含む、
    半導体装置。
  2. 前記基板の前記一方の面に形成された前記貫通孔の開口の周りに設けられた金属層を更に備え、
    前記金属部材は、前記金属層上に設けられ、前記貫通孔の前記開口から突出している
    請求項１に記載の半導体装置。
  3. 前記貫通孔の前記開口から突出した前記金属部材の部分にはスズまたは銅を含む接続部が形成されている
    請求項２に記載の半導体装置。
  4. 半導体基板の一方の面から対向する他方の面に貫通した貫通孔を前記半導体基板に形成する工程と、
    内部に空洞が形成された金属部材を前記貫通孔の内側に形成する工程と、
    前記金属部材と前記空洞との間に金属酸化膜を形成する工程と、
    を備え、
    前記金属部材は、ニッケルを主成分とし、
    前記金属酸化膜は、前記金属部材に含まれる金属材料の酸化物を含む、
    半導体装置の製造方法。
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6450296B2 (ja) * 2015-10-05 2019-01-09 浜松ホトニクス株式会社 配線構造体、及び配線構造体の製造方法
JP6817895B2 (ja) * 2017-05-24 2021-01-20 株式会社東芝 半導体装置
JP2019054199A (ja) * 2017-09-19 2019-04-04 東芝メモリ株式会社 半導体装置
JP2019160893A (ja) * 2018-03-09 2019-09-19 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子、半導体装置、電子機器、および製造方法
WO2020261356A1 (ja) * 2019-06-25 2020-12-30 日本碍子株式会社 半導体膜
US10896848B1 (en) * 2019-10-15 2021-01-19 Nanya Technology Corporation Method of manufacturing a semiconductor device
KR20210115349A (ko) * 2020-03-12 2021-09-27 에스케이하이닉스 주식회사 적층형 반도체 장치 및 그 제조방법
CN113539944B (zh) * 2020-04-16 2023-09-12 长鑫存储技术有限公司 半导体结构及其形成方法和半导体器件

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6599778B2 (en) * 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
US7276787B2 (en) 2003-12-05 2007-10-02 International Business Machines Corporation Silicon chip carrier with conductive through-vias and method for fabricating same
TWI441955B (zh) * 2007-05-21 2014-06-21 Uyemura C & Co Ltd Electroplating copper bath
CN101330042B (zh) * 2007-06-18 2010-11-10 中芯国际集成电路制造(上海)有限公司 导电插塞及其制作方法
US8673769B2 (en) * 2007-06-20 2014-03-18 Lam Research Corporation Methods and apparatuses for three dimensional integrated circuits
US8039314B2 (en) * 2008-08-04 2011-10-18 International Business Machines Corporation Metal adhesion by induced surface roughness
US8101517B2 (en) * 2009-09-29 2012-01-24 Infineon Technologies Ag Semiconductor device and method for making same
KR20110050957A (ko) * 2009-11-09 2011-05-17 삼성전자주식회사 반도체 소자의 관통 비아 콘택 및 그 형성 방법
JP2012142414A (ja) * 2010-12-28 2012-07-26 Panasonic Corp 半導体装置及びその製造方法並びにそれを用いた積層型半導体装置
FR2970119B1 (fr) * 2010-12-30 2013-12-13 St Microelectronics Crolles 2 Sas Puce de circuits integres et procede de fabrication.
US8901701B2 (en) * 2011-02-10 2014-12-02 Chia-Sheng Lin Chip package and fabrication method thereof
JP2012231096A (ja) * 2011-04-27 2012-11-22 Elpida Memory Inc 半導体装置及びその製造方法
JP5972537B2 (ja) 2011-07-27 2016-08-17 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置及びその製造方法
KR101959284B1 (ko) * 2011-11-18 2019-03-19 삼성전자주식회사 반도체 장치 및 그 형성방법
EP2854167B1 (en) * 2011-11-23 2016-01-20 ams AG Semiconductor device with through-substrate via covered by a solder ball and related method of production
US20130249047A1 (en) * 2012-03-26 2013-09-26 Nanya Technology Corporation Through silicon via structure and method for fabricating the same
KR102117124B1 (ko) * 2012-04-30 2020-05-29 엔테그리스, 아이엔씨. 유전체 물질로 중심-충전된 상 변화 합금을 포함하는 상 변화 메모리 구조체
DE102012210033B4 (de) * 2012-06-14 2023-02-02 Robert Bosch Gmbh Bauelement mit Durchkontaktierung und Verfahren zur Herstellung
JP2014011309A (ja) * 2012-06-29 2014-01-20 Ps4 Luxco S A R L 半導体装置およびその製造方法
JP6176253B2 (ja) * 2012-09-07 2017-08-09 旭硝子株式会社 インターポーザ用の中間品を製造する方法およびインターポーザ用の中間品
US8940635B1 (en) * 2013-08-30 2015-01-27 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for forming interconnect structure
CN203650291U (zh) 2013-09-29 2014-06-18 国家电网公司 光纤活动连接器防尘帽专用钳
US9293388B2 (en) * 2013-10-22 2016-03-22 Globalfoundries Singapore Pte. Ltd. Reliable passivation layers for semiconductor devices
TWI550800B (zh) * 2013-11-11 2016-09-21 力成科技股份有限公司 具強固型晶背凸塊之矽穿孔結構
US10083893B2 (en) 2014-01-30 2018-09-25 Toshiba Memory Corporation Semiconductor device and semiconductor device manufacturing method
JP6113679B2 (ja) * 2014-03-14 2017-04-12 株式会社東芝 半導体装置
CN203850291U (zh) * 2014-05-07 2014-09-24 中芯国际集成电路制造(北京)有限公司 一种tsv孔结构
JP2016032087A (ja) * 2014-07-30 2016-03-07 マイクロン テクノロジー， インク． 半導体装置及びその製造方法
US9666507B2 (en) * 2014-11-30 2017-05-30 United Microelectronics Corp. Through-substrate structure and method for fabricating the same
JP2017050497A (ja) * 2015-09-04 2017-03-09 株式会社東芝 半導体装置およびその製造方法
US9929107B1 (en) * 2016-12-06 2018-03-27 Infineon Technologies Ag Method for manufacturing a semiconductor device

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