JP2017050497A - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
JP2017050497A
JP2017050497A JP2015174753A JP2015174753A JP2017050497A JP 2017050497 A JP2017050497 A JP 2017050497A JP 2015174753 A JP2015174753 A JP 2015174753A JP 2015174753 A JP2015174753 A JP 2015174753A JP 2017050497 A JP2017050497 A JP 2017050497A
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Prior art keywords
electrode
substrate
resist layer
chip
layer
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JP2015174753A
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Inventor
渡辺　慎也
Shinya Watanabe
慎也 渡辺
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Toshiba Corp
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Toshiba Corp
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Priority to JP2015174753A priority Critical patent/JP2017050497A/ja
Priority to TW105103350A priority patent/TWI587418B/zh
Priority to US15/056,189 priority patent/US9922957B2/en
Priority to CN201610121748.6A priority patent/CN106505060A/zh
Publication of JP2017050497A publication Critical patent/JP2017050497A/ja
Pending legal-status Critical Current

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Abstract

【課題】半導体チップ同士を積層する場合における半導体チップ間の距離を短縮することが可能な半導体装置およびその製造方法を提供する。
【解決手段】一の実施形態によれば、半導体装置は、基板と、前記基板の上面側に設けられた第１電極と、前記基板の下面側に設けられ、前記第１電極と電気的に接続された第２電極とを備える。さらに、前記装置は、前記基板の前記上面側に前記第１電極を包囲するように設けられ、前記第１電極と離隔された第１レジスト層と、前記基板の前記下面側に設けられた第２レジスト層とを備える。
【選択図】図１

Description

本発明の実施形態は、半導体装置およびその製造方法に関する。
半導体チップは、ＴＳＶ（Through Silicon Via）電極と呼ばれる貫通電極を備える場合がある。ＴＳＶ電極は、基板の表面側に形成された表面電極と、基板の裏面側に形成された裏面電極とを含んでいる。基板の表面側には、トランジスタや多層配線が形成されている。表面電極は、基板の表面側に多層配線を介して形成され、裏面電極は、基板の裏面側と基板内とに多層配線に達するように形成される。
ＴＳＶ電極を備える半導体チップ同士を電気的に接続する場合、一方のチップが他方のチップ上に積層され、一方のチップの裏面電極が他方のチップの表面電極と接合される。しかしながら、この場合には、これらのチップ間の距離を十分に短くすることが難しいという問題がある。
特開２０１１−２２８４１９号公報 特開２００３−２３４４３２号公報 特開２００３−７８１０８号公報
半導体チップ同士を積層する場合における半導体チップ間の距離を短縮することが可能な半導体装置およびその製造方法を提供する。
一の実施形態によれば、半導体装置は、基板と、前記基板の上面側に設けられた第１電極と、前記基板の下面側に設けられ、前記第１電極と電気的に接続された第２電極とを備える。さらに、前記装置は、前記基板の前記上面側に前記第１電極を包囲するように設けられ、前記第１電極と離隔された第１レジスト層と、前記基板の前記下面側に設けられた第２レジスト層とを備える。
第１実施形態の半導体装置の構造を示す断面図である。 第１実施形態の半導体チップの接続方法を示す断面図(1/2)である。 第１実施形態の半導体チップの接続方法を示す断面図(2/2)である。 第１実施形態の半導体装置の裏面側の構造を示す平面図である。 第１実施形態の半導体装置の裏面側の構造を示す平面図である。 第１実施形態の半導体装置の表面側の構造を示す平面図である。 第１実施形態の比較例の半導体装置の構造を示す断面図である。 第１実施形態の比較例の半導体チップの接続方法を示す断面図(1/2)である。 第１実施形態の比較例の半導体チップの接続方法を示す断面図(2/2)である。 第１実施形態の半導体装置の製造方法を示す断面図(1/5)である。 第１実施形態の半導体装置の製造方法を示す断面図(2/5)である。 第１実施形態の半導体装置の製造方法を示す断面図(3/5)である。 第１実施形態の半導体装置の製造方法を示す断面図(4/5)である。 第１実施形態の半導体装置の製造方法を示す断面図(5/5)である。
以下、本発明の実施形態を、図面を参照して説明する。
（第１実施形態）
図１は、第１実施形態の半導体装置の構造を示す断面図である。図１は、１個の半導体チップの断面を示している。
図１の半導体装置は、基板１と、第１絶縁膜２と、層間絶縁膜３と、配線部４と、表面電極（表面バンプ）５と、第２絶縁膜６と、裏面電極（裏面バンプ）７と、表面レジスト層８と、裏面レジスト層９とを備えている。表面電極５と裏面電極７は、第１および第２電極の例である。表面レジスト層８と裏面レジスト層９は、第１および第２レジスト層の例である。
基板１の例は、シリコン基板などの半導体基板である。符号Ｓ１は、基板１の表面（上面）を示す。符号Ｓ２は、基板１の裏面（下面）を示す。符号Ｓ３は、基板１の表面Ｓ１と裏面Ｓ２との間に設けられた貫通孔Ｈの側面を示す。図１は、基板１の表面Ｓ１や裏面Ｓ２に平行で互いに垂直なＸ方向およびＹ方向と、基板１の表面Ｓ１と裏面Ｓ２に垂直なＺ方向とを示している。本明細書では、＋Ｚ方向を上方向として取り扱い、−Ｚ方向を下方向として取り扱う。本実施形態の−Ｚ方向は、重力方向と一致していてもよいし、重力方向と一致していなくてもよい。基板１の厚さは、例えば３３μｍである。
第１絶縁膜２は、基板１の表面Ｓ１に形成されている。第１絶縁膜２は、貫通孔Ｈを包囲するように形成されている。第１絶縁膜２の例は、シリコン酸化膜やシリコン窒化膜である。
層間絶縁膜３は、基板１の表面Ｓ１に第１絶縁膜２を介して形成されている。層間絶縁膜３の例は、シリコン酸化膜やシリコン窒化膜である。
配線部４は、多層配線や、これらの配線同士を接続するプラグを含んでいる。配線部４は、基板１の表面Ｓ１に第１絶縁膜２を介して形成されており、層間絶縁膜３により覆われている。配線部４の例は、種々の金属層である。
表面電極５は、基板１の表面Ｓ１側に形成されている。表面電極５は、層間絶縁膜３を介して配線部４上に形成されており、配線部４に電気的に接続されている。符号Ｆ３は、表面電極５の上面を示す。表面電極５の上面Ｆ３は、表面電極５を形成する際に形成された窪みＢを有している。符号Ｔ３は、層間絶縁膜３の上面上における表面電極５の厚さを示す。厚さＴ３は、例えば３μｍである。符号αは、表面電極５の外周を示す。
表面電極５は、第１電極層５ａと、第２電極層５ｂと、第３電極層５ｃと、第４電極層５ｄとを順に含んでいる。第１電極層５ａの例は、チタン（Ｔｉ）層である。第２電極層５ｂの例は、銅（Ｃｕ）層である。第３電極層５ｃの例は、ニッケル（Ｎｉ）層である。第４電極層５ｄの例は、金（Ａｕ）層である。本実施形態の第１および第２電極層５ａ、５ｂは、バリアメタル層として機能する。
第２絶縁膜６は、基板１の裏面Ｓ２と基板１の貫通孔Ｈの側面Ｓ３とに形成されている。第２絶縁膜６の例は、シリコン酸化膜やシリコン窒化膜である。
裏面電極７は、基板１の裏面Ｓ２側に形成されている。裏面電極７は、第２絶縁膜６を介して基板１の裏面Ｓ２側と基板１の貫通孔Ｈ内とに形成されており、配線部４に電気的に接続されている。その結果、表面電極５と裏面電極７は、電気的に接続されており、ＴＳＶ電極（貫通電極）を形成している。符号Ｖは、裏面電極７を形成する際に形成されたボイドを示している。
裏面電極７は、第１電極層７ａと、第２電極層７ｂと、第３電極層７ｃと、第４電極層７ｄとを順に含んでいる。第１電極層７ａの例は、チタン（Ｔｉ）層である。第２電極層７ｂの例は、銅（Ｃｕ）層である。第３電極層７ｃの例は、ニッケル（Ｎｉ）層である。第４電極層７ｄの例は、Ｓｎ−Ｃｕ（スズ−銅）合金層である。本実施形態の第１および第２電極層７ａ、７ｂは、バリアメタル層として機能する。本実施形態の第４電極層７ｄは、表面電極５と裏面電極７とを接合するための半田層（メッキ層）である。
表面レジスト層８は、基板１の表面Ｓ１側に表面電極５を包囲するように形成されており、表面電極５と離隔されている。表面レジスト層８は、表面電極５の内周αを包囲する外周βを有している。表面レジスト層８の例は、半導体チップの積層ダメージを抑制するためのフェノール系樹脂である。表面レジスト層８は、表面電極５と同様に、層間絶縁膜３を介して基板１の表面Ｓ１側に形成されている。符号Ｆ１は、表面レジスト層８の上面を示す。符号Ｔ１は、表面レジスト層８の厚さを示す。厚さＴ１は、例えば５μｍである。
本実施形態では、表面電極５の厚さＴ３が、表面レジスト層８の厚さＴ１よりも薄く設定されている。よって、表面電極５の上面Ｆ３の高さが、表面レジスト層８の上面Ｆ１の高さよりも低くなっている。
裏面レジスト層９は、基板１の裏面Ｓ２側に形成されており、裏面電極７と離隔されている。裏面レジスト層９の例は、接着機能と感光性とを有するノボラック系樹脂である。裏面レジスト層９は、裏面電極７と同様に、第２絶縁膜６を介して基板１の裏面Ｓ２側に形成されている。符号Ｆ２は、裏面レジスト層９の下面を示す。符号Ｔ２は、裏面レジスト層９の厚さを示す。
本実施形態では、表面レジスト層８が表面電極５付近から除去されており、表面レジスト層８が表面電極５と離隔されている。符号Ｋは、表面レジスト層８が除去された領域を示している。よって、本実施形態では、表面電極５の上面Ｆ３の高さを表面レジスト層８の上面Ｆ１の高さよりも低くすることができる。これにより、裏面レジスト層９の厚さＴ２を薄くすることも可能となる。よって、本実施形態によれば、図１の構造を有する半導体チップ同士を積層する際に、表面レジスト層８により半導体チップの積層ダメージを抑制しつつ、半導体チップ間の距離を短縮することが可能となる。
図２と図３は、第１実施形態の半導体チップの接続方法を示す断面図である。
図２と図３は、図１の構造を有する半導体チップＣ１〜Ｃ３を示している。ただし、図２は、接続前の半導体チップＣ１〜Ｃ３を示し、図３は、接続後の半導体チップＣ１〜Ｃ３を示している。
半導体チップＣ１、Ｃ２を電気的に接続するときには、半導体チップＣ２が半導体チップＣ１上に積層される（図３）。この際、半導体チップＣ２の裏面電極７が半導体チップＣ１の表面電極５に接し、半導体チップＣ２の裏面レジスト層９が半導体チップＣ１の表面レジスト層８に接するように、半導体チップＣ２が半導体チップＣ１上に積層される。
そして、半導体チップＣ２の裏面電極７が、第４電極層７ｄ（半田層）により半導体チップＣ１の表面電極５と接合される。また、半導体チップＣ２の裏面レジスト層９が、裏面レジスト層９の接着機能により半導体チップＣ１の表面レジスト層８と接着される。こうして、半導体チップＣ１、Ｃ２が電気的に接続される。この場合、半導体チップＣ１は第１チップの例であり、半導体チップＣ２は第２チップの例である。
同様に、半導体チップＣ２、Ｃ３を電気的に接続するときには、半導体チップＣ３が半導体チップＣ２上に積層される（図３）。この場合、半導体チップＣ２は第１チップの例であり、半導体チップＣ３は第２チップの例である。
隣接する半導体チップ間の距離は、各チップの表面レジスト層８と裏面レジスト層９の合計厚さＴ１＋Ｔ２に依存する。この合計厚さＴ１＋Ｔ２は、各チップの表面電極５の厚さＴ３が厚くなると、それに伴い厚くする必要がある。しかしながら、本実施形態によれば、各チップの表面電極５の厚さＴ３を薄くすることができるため、この合計厚さＴ１＋Ｔ２を薄くすることができる。これにより、隣接する半導体チップ間の距離を短縮することが可能となる。
本実施形態では、半導体チップＣ１、Ｃ２を電気的に接続し、半導体チップＣ２、Ｃ３を電気的に接続することにより、半導体チップＣ１〜Ｃ３を備える半導体装置（半導体モジュール）を作製することができる。なお、半導体モジュールを形成する半導体チップの個数は、３個以外でもよい。本実施形態によれば、隣接する半導体チップ間の距離を短縮することにより、半導体モジュールのパッケージの厚さを薄くすることや、半導体モジュールを形成する半導体チップの個数を増やすことが可能となる。
なお、各チップの表面電極５は、窪みＢが小さくかつ浅くなるように形成することが望ましい。理由は、窪みＢが大きくかつ深いと、接合後の表面電極５と裏面電極７との間に隙間が形成される可能性が高くなるからである。
図４と図５は、第１実施形態の半導体装置の裏面Ｓ２側の構造を示す平面図である。
図４(ａ)は、図１の半導体チップの基板１の裏面Ｓ２を示している。符号Ｌ１は、半導体チップのＸ方向の長さを示す。長さＬ１は、例えば１２ｍｍである。符号Ｌ２は、半導体チップのＹ方向の長さを示す。長さＬ２は、例えば１５ｍｍである。
図４(ｂ)は、図４(ａ)の領域Ｒ１の拡大図である。図４(ｂ)は、基板１の裏面Ｓ２側に形成された複数の裏面電極７と複数の裏面レジスト層９とを示している。
図５(ａ)と図５(ｂ)は、図４(ｂ)の領域Ｒ２、Ｒ３の拡大図である。図５(ａ)と図５(ｂ)に示すように、本実施形態の各裏面電極７と各裏面レジスト層９は、円形の平面形状を有している。各裏面電極７の直径は、例えば２０μｍである。各裏面レジスト層９の直径は、例えば４０〜１６０μｍである。
図６は、第１実施形態の半導体装置の表面Ｓ１側の構造を示す平面図である。
図６(ａ)は、図１の半導体チップの表面Ｓ１側の構造の一例を示している。図６(ａ)は、基板１の表面Ｓ１側に形成された複数の表面電極５と、これらの表面電極５を包囲する表面レジスト層８とを示している。これらの表面電極５の外周αと、表面レジスト層８の内周βは、円形の平面形状を有している。
符号Ｄ１は、各表面電極５の外周αの直径を示す。符号Ｄ２は、表面レジスト層８の各内周βの直径を示す。本実施形態では、直径Ｄ２が直径Ｄ１よりも大きく設定されており、その結果、各表面電極５が表面レジスト層８と離隔されている。直径Ｄ１は、例えば２０μｍである。直径Ｄ２は、例えば２５μｍである。直径Ｄ１は第１直径の例であり、直径Ｄ２は第２直径の例である。
図６(ｂ)は、図１の半導体チップの表面Ｓ１側の構造の別の例を示している。図６(ｂ)に示すように、表面レジスト層８の各内周βの平面形状は、円形以外でもよい。
図６(ｃ)は、図１の半導体チップの表面Ｓ１側の構造の別の例を示している。図６(ａ)と図６(ｂ)では、表面レジスト層８の１つの内周βが、１つの表面電極５のみを包囲している。一方、図６(ｃ)では、表面レジスト層８の１つの内周βが、複数の表面電極５を包囲している。このように、１つの内周β内の表面電極５の個数は、何個でもよい。
［第１実施形態の比較例の半導体装置］
図７は、第１実施形態の比較例の半導体装置の構造を示す断面図である。
本比較例の表面電極５は、表面レジスト層８を介して配線部４上に形成されている。そのため、表面電極５の厚さＴ３が、表面レジスト層８の厚さＴ１よりも厚くなっており、表面電極５の上面Ｆ３の高さが、表面レジスト層８の上面Ｆ１の高さよりも高くなっている。よって、本比較例では、裏面レジスト層９の厚さＴ２も厚くする必要がある。
図８と図９は、第１実施形態の比較例の半導体チップの接続方法を示す断面図である。
図８と図９は、図７の構造を有する半導体チップＣ１〜Ｃ３を示している。ただし、図８は、接続前の半導体チップＣ１〜Ｃ３を示し、図９は、接続後の半導体チップＣ１〜Ｃ３を示している。
半導体チップＣ１、Ｃ２を電気的に接続するときには、半導体チップＣ２が半導体チップＣ１上に積層される（図９）。また、半導体チップＣ２、Ｃ３を電気的に接続するときには、半導体チップＣ３が半導体チップＣ２上に積層される（図９）。
隣接する半導体チップ間の距離は、各チップの表面レジスト層８と裏面レジスト層９の合計厚さＴ１＋Ｔ２に依存する。この合計厚さＴ１＋Ｔ２は、各チップの表面電極５の厚さＴ３が厚くなると、それに伴い厚くする必要がある。上述のように、本比較例では各チップの表面電極５の厚さＴ３が厚いため、この合計厚さＴ１＋Ｔ２を薄くすることは難しい。よって、隣接する半導体チップ間の距離が長くなってしまう。
一方、本実施形態によれば、各チップの表面電極５の厚さＴ３を薄くすることができるため、合計厚さＴ１＋Ｔ２を薄くすることができる。これにより、隣接する半導体チップ間の距離を短縮することが可能となる。
［第１実施形態の半導体装置の製造方法］
図１０〜図１４は、第１実施形態の半導体装置の製造方法を示す断面図である。
まず、基板１の表面Ｓ１に、第１絶縁膜２、層間絶縁膜３、および配線部４を形成した後、配線部４の上面に達する開口部Ｅを層間絶縁膜３に形成する（図１０(ａ)）。
次に、配線部４上に表面電極５を形成する（図１０(ｂ)）。表面電極５は例えば、層間絶縁膜３および配線部４上に第１〜第４電極層５ａ〜５ｄを順に形成し、第１〜第４電極層５ａ〜５ｄをエッチングにより加工することで形成される。このとき、表面電極５の上面Ｆ３に窪みＢが形成されることがある。
次に、層間絶縁膜３および表面電極５上に表面レジスト層８を形成する（図１１(ａ)）。表面レジスト層８は、表面電極５の上面Ｆ３を覆うように形成される。その結果、表面電極５の上面Ｆ３の高さは、表面レジスト層８の上面Ｆ１の高さよりも低くなる。
次に、フォトリソグラフィおよびエッチングにより、表面電極５付近の表面レジスト層８を除去する（図１１(ｂ)）。その結果、表面レジスト層８は、表面電極５を包囲し、表面電極５と離隔された形状に加工される。表面電極５の外周αや表面レジスト層８の内周βの平面形状は、例えば円形である。
次に、基板１の裏面Ｓ２を削り、基板１を薄膜化する（図１２(ａ)）。
次に、フォトリソグラフィおよびエッチングにより、基板１の裏面Ｓ２に貫通孔Ｈを形成する（図１２(ｂ)）。基板１の裏面Ｓ２における貫通孔Ｈの直径は、例えば１０μｍである。基板１の表面Ｓ１における貫通孔Ｈの直径は、例えば８μｍである。
次に、基板１の裏面Ｓ２、貫通孔Ｈの側面Ｓ３、および貫通孔Ｈの底面に第２絶縁膜６を形成する（図１３(ａ)）。さらに、貫通孔Ｈの底面から第２絶縁膜６をエッチングにより除去する（図１３(ａ)）。さらに、基板１の裏面Ｓ２、貫通孔Ｈの側面Ｓ３、および貫通孔Ｈの底面に、第２絶縁膜６を介して第１および第２電極層７ａ、７ｂを順に形成する（図１３(ａ)）。
次に、フォトリソグラフィおよびエッチングにより、基板１の裏面Ｓ２側にフォトレジスト層１０を形成する（図１３(ｂ)）。
次に、フォトレジスト層１０をマスクとして使用して、基板１の裏面Ｓ２および基板１の貫通孔Ｈ内に第３電極層７ｃを形成する（図１４(ａ)）。このとき、第３電極層７ｃ内にボイドＶが形成されることがある。さらに、フォトレジスト層１０を除去した後、第３電極層７ｃをマスクとして使用して、第１および第２電極層７ａ、７ｂをエッチングにより加工する（図１４(ａ)）。
次に、フォトリソグラフィおよびエッチングにより、基板１の裏面Ｓ２側に裏面レジスト層９を形成する（図１４(ｂ)）。さらに、第３電極層７ｃの下面に第４電極層７ｄを形成する（図１４(ｂ)）。その結果、基板１の裏面Ｓ２側および基板１の貫通孔Ｈ内に裏面電極７が形成される。裏面電極７は、配線部４に電気的に接続されるように形成される。これにより、裏面電極７は、配線部４を介して表面電極５に電気的に接続され、表面電極５と裏面電極７とを含むＴＳＶ電極が形成される。
このようにして、図１の半導体チップが製造される。その後、図１の構造を有する複数の半導体チップを用いて図３の半導体モジュールが製造される。
以上のように、本実施形態の表面レジスト層８は、基板１の表面Ｓ１側に、表面電極５を包囲し表面電極５と離隔されるように形成される。よって、本実施形態によれば、図１の構造を有する半導体チップ同士を積層する場合において、半導体チップ間の距離を短縮することが可能となる。
以上、いくつかの実施形態を説明したが、これらの実施形態は、例としてのみ提示したものであり、発明の範囲を限定することを意図したものではない。本明細書で説明した新規な装置および方法は、その他の様々な形態で実施することができる。また、本明細書で説明した装置および方法の形態に対し、発明の要旨を逸脱しない範囲内で、種々の省略、置換、変更を行うことができる。添付の特許請求の範囲およびこれに均等な範囲は、発明の範囲や要旨に含まれるこのような形態や変形例を含むように意図されている。
１：基板、２：第１絶縁膜、３：層間絶縁膜、４：配線部、５：表面電極、
５ａ：第１電極層、５ｂ：第２電極層、５ｃ：第３電極層、５ｄ：第４電極層、
６：第２絶縁膜、７：裏面電極、
７ａ：第１電極層、７ｂ：第２電極層、７ｃ：第３電極層、７ｄ：第４電極層、
８：表面レジスト層、９：裏面レジスト層、１０：フォトレジスト層

Claims (8)

  1. 基板と、
    前記基板の上面側に設けられた第１電極と、
    前記基板の下面側に設けられ、前記第１電極と電気的に接続された第２電極と、
    前記基板の前記上面側に前記第１電極を包囲するように設けられ、前記第１電極と離隔された第１レジスト層と、
    前記基板の前記下面側に設けられた第２レジスト層と、
    を備える半導体装置。
  2. 前記第１電極の上面の高さは、前記第１レジスト層の上面の高さよりも低い、請求項１に記載の半導体装置。
  3. 前記第１レジスト層は、前記第１電極の外周を包囲する内周を有し、
    前記第１電極の前記外周は、第１直径を有し、
    前記第１レジスト層の前記内周は、前記第１直径よりも大きい第２直径を有する、
    請求項１または２に記載の半導体装置。
  4. 前記第２電極は、前記基板の前記下面側および前記基板内に設けられている、請求項１から３のいずれか１項に記載の半導体装置。
  5. 第１チップと、
    前記第１チップ上に設けられた第２チップとを備え、
    前記第１および第２チップの各々は、
    基板と、
    前記基板の上面側に設けられた第１電極と、
    前記基板の下面側に設けられ、前記第１電極と電気的に接続された第２電極と、
    前記基板の前記上面側に前記第１電極を包囲するように設けられ、前記第１電極と離隔された第１レジスト層と、
    前記基板の前記下面側に設けられた第２レジスト層とを備え、
    前記第２チップは、前記第２チップの前記第２電極が前記第１チップの前記第１電極に接するように、前記第１チップ上に設けられている、半導体装置。
  6. 前記第２チップは、前記第２チップの前記第２レジスト層が前記第１チップの前記第１レジスト層に接するように、前記第１チップ上に設けられている、請求項５に記載の半導体装置。
  7. 基板の上面側に第１電極を形成し、
    前記基板の前記上面側に、前記第１電極を包囲し、前記第１電極と離隔された第１レジスト層を形成し、
    前記基板の下面側に、前記第１電極と電気的に接続された第２電極を形成し、
    前記基板の前記下面側に第２レジスト層を形成する、
    ことを含む半導体装置の製造方法。
  8. さらに、前記基板の前記下面に孔を形成することを含み、
    前記第２電極は、前記基板の前記下面側および前記基板の前記孔内に形成される、請求項７に記載の半導体装置の製造方法。
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