JPH07505982A - 深い導電性フィードスルーの形成方法,および該方法に従って形成されたフィードスルーを含む配線層 - Google Patents
深い導電性フィードスルーの形成方法,および該方法に従って形成されたフィードスルーを含む配線層Info
- Publication number
- JPH07505982A JPH07505982A JP6517073A JP51707394A JPH07505982A JP H07505982 A JPH07505982 A JP H07505982A JP 6517073 A JP6517073 A JP 6517073A JP 51707394 A JP51707394 A JP 51707394A JP H07505982 A JPH07505982 A JP H07505982A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- silicon
- opening
- dielectric
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/135—Removal of substrate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/164—Three dimensional processing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/928—Front and rear surface processing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/973—Substrate orientation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (9)
- 1.半導体層内に導電性フィードスルーを形成する方法であって、 基板と、該基板の表面を覆う第一表面およびこの第一表面とは反対側の第二表面 を有する誘電体層と、該誘電体層の前記第二表面を覆う第一表面および該第一表 面とは反対側の第二表面を有する半導体層とを含む多層構造体を製造する工程と 、 前記半導体層を貫通する少なくとも一つの開口部(その側壁は、該開口部の径が 半導体層の第一表面側よりも第二表面側の方で大きくなるように傾斜している) を形成して、前記誘電体層の第二表面の一部を露出させ、更に前記開口部の側壁 を誘電材料で被覆する工程と、 前記傾斜した側壁および前記誘電体層の露出した第二表面部分に、導電性材料を 蒸着する工程と、前記基板を除去して、前記誘電体層の第一表面を露出させる工 程と、 前記半導体層を貫通する開口部に一致させて、前記誘電体層を貫通する開口部を 形成し、前記誘電体層の第二表面部分に蒸着された前記導電性材料の一部を露出 させる工程と、前記誘電体層を貫通して形成された前記開口部内に導電性材料を 蒸着し、この誘電体層を貫通する開口部内の導電性材料を、前記半導体層を貫通 する開口部内に蒸着された前記導電性材料に電気的に結合させる工程とを具備し た方法。
- 2.請求の範囲第1項に記載の方法であって、前記半導体層が<100>シリコ ンであり、前記半導体層を貫通する少なくとも一つの開口部を形成する工程が前 記<100>シリコンをKOHでエッチングする工程を含む方法。
- 3.請求の範囲第1項に記載の方法であって、前記半導体層を貫通する少なくと も一つの開口部を形成する工程には、その初期工程として、 前記半導体層の前記第二表面上に誘電体層を形成する工程と、 該誘電体層を貫通する孔(その面積は、前記半導体層の厚さの関数である)を開 孔する工程とが含まれる方法。
- 4.請求の範囲第1項に記載の方法であって、前記半導体層が略10μm〜50 μmの厚さを有する<100>シリコンからなり、また前記半導体層を貫通する 少なくとも一つの開口部を形成する工程が、 前記<100>シリコン層の前記第二表面上に酸化物層を形成する工程と、 該酸化物層を貫通する孔(その径は、前記<100>シリコン層の厚さの少なく とも略2倍である)を開孔する工程と、該孔を介して、前記<100>シリコン をKOHでエッチングする工程とが含まれる方法。
- 5.請求の範囲第2項に記載の方法であって、前記傾斜が54.7度に略等しい 方法。
- 6.二つの活性回路層の間に配置するための配線層であって、 第一表面および該第一表面とは反対側の第二表面を有するシリコン層と、 前記第一表面上に形成された第一誘電体層と、前記第二表面上に形成された第二 誘電体層と、前記シリコン層を貫通する開孔部内に形成された少なくとも一つの 導電性フィードスルーとを具備し、前記開孔部は誘電体材料でコーティングされ た側壁を有し、また該誘電体コーティングの上には導電性材料が形成されており 、更に、前記側壁は、前記開孔部の面積が前記シリコン層の第二表面でよりも前 記シリコン層の第一表面でより大きくなるような傾斜を有している配線層。
- 7.請求の範囲第6項に記載の配線層であって、前記シリコン層は略10μm〜 略50μmの厚さを有する<100>シリコンからなり、また前記開孔部は前記 <100>シリコン層をKOHでエッチングして形成されており、更に前記傾斜 は54.7度に略等しい配線層。
- 8.請求の範囲第7項に記載の配線層であって、前記導電性材料がアルミニウム /シリコン/銅からなる配線層。
- 9.請求の範囲第7項に記載の配線層であって、前記第一誘電体層、第二誘電体 層および前記誘電体コーティング材料が全て二酸化シリコンからなる配線層。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/006,215 US5322816A (en) | 1993-01-19 | 1993-01-19 | Method for forming deep conductive feedthroughs |
US6,215 | 1993-01-19 | ||
US006,215 | 1993-01-19 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH07505982A true JPH07505982A (ja) | 1995-06-29 |
JP2564474B2 JP2564474B2 (ja) | 1996-12-18 |
Family
ID=21719828
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6517073A Expired - Lifetime JP2564474B2 (ja) | 1993-01-19 | 1994-01-10 | 深い導電性フィードスルーの形成方法,および該方法に従って形成されたフィードスルーを含む配線層 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5322816A (ja) |
JP (1) | JP2564474B2 (ja) |
DE (2) | DE4490400C2 (ja) |
GB (1) | GB2280783B (ja) |
WO (1) | WO1994017548A1 (ja) |
Cited By (6)
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JP2011527512A (ja) * | 2008-07-16 | 2011-10-27 | オーストリアマイクロシステムズ アクチエンゲゼルシャフト | 半導体素子の製造方法および半導体素子 |
JP2013544444A (ja) * | 2010-12-02 | 2013-12-12 | テッセラ,インコーポレイテッド | チップ上方のキャリアと段状に形成されたシリコン貫通電極とを有する積層超小型電子アセンブリ |
US9099296B2 (en) | 2010-12-02 | 2015-08-04 | Tessera, Inc. | Stacked microelectronic assembly with TSVS formed in stages with plural active chips |
US9548254B2 (en) | 2006-11-22 | 2017-01-17 | Tessera, Inc. | Packaged semiconductor chips with array |
US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
US10354942B2 (en) | 2010-09-17 | 2019-07-16 | Tessera, Inc. | Staged via formation from both sides of chip |
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US5646067A (en) * | 1995-06-05 | 1997-07-08 | Harris Corporation | Method of bonding wafers having vias including conductive material |
US5618752A (en) * | 1995-06-05 | 1997-04-08 | Harris Corporation | Method of fabrication of surface mountable integrated circuits |
KR100377033B1 (ko) * | 1996-10-29 | 2003-03-26 | 트러시 테크날러지스 엘엘시 | Ic 및 그 제조방법 |
US6882030B2 (en) | 1996-10-29 | 2005-04-19 | Tru-Si Technologies, Inc. | Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate |
US6448153B2 (en) | 1996-10-29 | 2002-09-10 | Tru-Si Technologies, Inc. | Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners |
SE9604678L (sv) * | 1996-12-19 | 1998-06-20 | Ericsson Telefon Ab L M | Bulor i spår för elastisk lokalisering |
SE511425C2 (sv) * | 1996-12-19 | 1999-09-27 | Ericsson Telefon Ab L M | Packningsanordning för integrerade kretsar |
SE511377C2 (sv) * | 1996-12-19 | 1999-09-20 | Ericsson Telefon Ab L M | Viaanordning |
DE69737262T2 (de) * | 1997-11-26 | 2007-11-08 | Stmicroelectronics S.R.L., Agrate Brianza | Herstellungsverfahren für einen Vorder-Hinterseiten-Durchkontakt in mikro-integrierten Schaltungen |
US6297531B2 (en) | 1998-01-05 | 2001-10-02 | International Business Machines Corporation | High performance, low power vertical integrated CMOS devices |
US6137129A (en) | 1998-01-05 | 2000-10-24 | International Business Machines Corporation | High performance direct coupled FET memory cell |
US6222276B1 (en) | 1998-04-07 | 2001-04-24 | International Business Machines Corporation | Through-chip conductors for low inductance chip-to-chip integration and off-chip connections |
US6322903B1 (en) | 1999-12-06 | 2001-11-27 | Tru-Si Technologies, Inc. | Package of integrated circuits and vertical integration |
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US6908845B2 (en) * | 2002-03-28 | 2005-06-21 | Intel Corporation | Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme |
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NO321381B1 (no) * | 2004-07-22 | 2006-05-02 | Thin Film Electronics Asa | Elektrisk viaforbindelse og tilknyttet kontaktanordning samt fremgangsmate til deres fremstilling |
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US7759166B2 (en) * | 2006-10-17 | 2010-07-20 | Tessera, Inc. | Microelectronic packages fabricated at the wafer level and methods therefor |
US7791199B2 (en) * | 2006-11-22 | 2010-09-07 | Tessera, Inc. | Packaged semiconductor chips |
US7952195B2 (en) * | 2006-12-28 | 2011-05-31 | Tessera, Inc. | Stacked packages with bridging traces |
EP2575166A3 (en) * | 2007-03-05 | 2014-04-09 | Invensas Corporation | Chips having rear contacts connected by through vias to front contacts |
WO2009017758A2 (en) * | 2007-07-27 | 2009-02-05 | Tessera, Inc. | Reconstituted wafer stack packaging with after-applied pad extensions |
KR101588723B1 (ko) | 2007-07-31 | 2016-01-26 | 인벤사스 코포레이션 | 실리콘 쓰루 비아를 사용하는 반도체 패키지 공정 |
WO2009020572A2 (en) | 2007-08-03 | 2009-02-12 | Tessera Technologies Hungary Kft. | Stack packages using reconstituted wafers |
US8043895B2 (en) | 2007-08-09 | 2011-10-25 | Tessera, Inc. | Method of fabricating stacked assembly including plurality of stacked microelectronic elements |
CN102067310B (zh) * | 2008-06-16 | 2013-08-21 | 泰塞拉公司 | 带有边缘触头的晶片级芯片规模封装的堆叠及其制造方法 |
TWI468093B (zh) | 2008-10-31 | 2015-01-01 | Princo Corp | 多層基板之導孔結構及其製造方法 |
CN101728355A (zh) * | 2008-11-03 | 2010-06-09 | 巨擘科技股份有限公司 | 多层基板的导孔结构及其制造方法 |
EP2406821A2 (en) * | 2009-03-13 | 2012-01-18 | Tessera, Inc. | Stacked microelectronic assemblies having vias extending through bond pads |
US20110139484A1 (en) * | 2009-12-15 | 2011-06-16 | Advanced Bionics, Llc | Hermetic Electrical Feedthrough |
FR2957749A1 (fr) * | 2010-03-22 | 2011-09-23 | Sorin Crm Sas | Procede de realisation d'une traversee electrique dans la paroi metallique d'un boitier, notamment de dispositif medical actif, et dispositif pourvu d'une telle traversee |
US8598695B2 (en) | 2010-07-23 | 2013-12-03 | Tessera, Inc. | Active chip on carrier or laminated chip having microelectronic element embedded therein |
US8791575B2 (en) | 2010-07-23 | 2014-07-29 | Tessera, Inc. | Microelectronic elements having metallic pads overlying vias |
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US8637968B2 (en) | 2010-12-02 | 2014-01-28 | Tessera, Inc. | Stacked microelectronic assembly having interposer connecting active chips |
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1993
- 1993-01-19 US US08/006,215 patent/US5322816A/en not_active Expired - Lifetime
-
1994
- 1994-01-10 DE DE4490400A patent/DE4490400C2/de not_active Expired - Lifetime
- 1994-01-10 JP JP6517073A patent/JP2564474B2/ja not_active Expired - Lifetime
- 1994-01-10 WO PCT/US1994/000371 patent/WO1994017548A1/en active Application Filing
- 1994-01-10 DE DE4490400T patent/DE4490400T1/de active Pending
- 1994-01-10 GB GB9418860A patent/GB2280783B/en not_active Expired - Lifetime
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Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9548254B2 (en) | 2006-11-22 | 2017-01-17 | Tessera, Inc. | Packaged semiconductor chips with array |
JP2011527512A (ja) * | 2008-07-16 | 2011-10-27 | オーストリアマイクロシステムズ アクチエンゲゼルシャフト | 半導体素子の製造方法および半導体素子 |
US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
US10354942B2 (en) | 2010-09-17 | 2019-07-16 | Tessera, Inc. | Staged via formation from both sides of chip |
JP2013544444A (ja) * | 2010-12-02 | 2013-12-12 | テッセラ,インコーポレイテッド | チップ上方のキャリアと段状に形成されたシリコン貫通電極とを有する積層超小型電子アセンブリ |
US9099296B2 (en) | 2010-12-02 | 2015-08-04 | Tessera, Inc. | Stacked microelectronic assembly with TSVS formed in stages with plural active chips |
US9269692B2 (en) | 2010-12-02 | 2016-02-23 | Tessera, Inc. | Stacked microelectronic assembly with TSVS formed in stages and carrier above chip |
US9368476B2 (en) | 2010-12-02 | 2016-06-14 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
US9620437B2 (en) | 2010-12-02 | 2017-04-11 | Tessera, Inc. | Stacked microelectronic assembly with TSVS formed in stages and carrier above chip |
Also Published As
Publication number | Publication date |
---|---|
US5322816A (en) | 1994-06-21 |
WO1994017548A1 (en) | 1994-08-04 |
DE4490400T1 (de) | 1995-04-27 |
JP2564474B2 (ja) | 1996-12-18 |
GB2280783A (en) | 1995-02-08 |
GB2280783B (en) | 1996-11-13 |
DE4490400C2 (de) | 2001-05-17 |
GB9418860D0 (en) | 1994-11-09 |
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