CN101719488B - 具有锥形轮廓的再分布线的焊垫连接 - Google Patents

具有锥形轮廓的再分布线的焊垫连接 Download PDF

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CN101719488B
CN101719488B CN2009101469881A CN200910146988A CN101719488B CN 101719488 B CN101719488 B CN 101719488B CN 2009101469881 A CN2009101469881 A CN 2009101469881A CN 200910146988 A CN200910146988 A CN 200910146988A CN 101719488 B CN101719488 B CN 101719488B
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redistribution lines
semiconductor substrate
layer
silicon
integrated circuit
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CN101719488A (zh
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许国经
陈承先
黃宏麟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种具有锥形轮廓的再分布线的焊垫连接。具有所述锥形轮廓的再分布线的焊垫连接的集成电路结构包括具有前面和背面的半导体衬底。穿透硅通孔(TSV)穿过所述半导体衬底，其中所述TSV具有延伸到所述半导体衬底背面的后端。再分布线(RDL)形成在所述半导体衬底背面上方，并连接到所述穿透硅通孔的后端。钝化层位于所述再分布线上方并具有在所述钝化层中的开口，其中所述再分布线的一部分顶面和所述再分布线的侧壁通过所述开口暴露出。金属整精层形成在所述开口中，并与所述再分布线的所述部分顶面和侧壁接触。

Description

具有锥形轮廓的再分布线的焊垫连接
技术领域
本发明通常涉及集成电路结构，尤其涉及穿透硅通孔，并且更进一步涉及一种连接到穿透硅通孔的焊垫形成。
背景技术
自从集成电路发明以来，由于各种电子部件(例如晶体管、二极管、电阻器、电容器等)集成密度的持续改善，半导体工业已经经历了连续快速的发展。在极大程度上，这种集成密度的改善来自于最小特征尺寸的反复减少，以允许更多的部件被集成到给定的芯片区域内。
本质上这些集成改善基本上是二维(2D)的，因为由集成部件占据的体积基本位于半导体晶片的表面上。虽然平版印刷术的巨大改善已引起很大程度的二维集成电路形成的改善，但是仍存在对二维集成电路中能够获得密度的物理限制。其中一种限制是制造这些部件所需的最小尺寸。并且，当更多器件被放入到一个芯片中时，则需要更复杂的设计。
另外的限制是来自于随着器件数量的显著增加引起的器件之间互连数量和长度的增加。当互连数量和长度增加时，电路阻容(RC)延迟和功率消耗均增加。
在解决上述限制的尝试中，通常使用三维集成电路(3DIC)和堆叠管芯。穿透硅通孔(TSV)因此使用于三维集成电路和堆叠管芯中，用来连接管芯。这种情况下，TSV通常用于将管芯上的集成电路连接到管芯的背面。此外，TSV也用来提供穿过管芯背面将集成电路接地的短接地路径，其上可以涂有接地金属膜。
图1显示了传统形成在芯片104中的TSV 102，TSV 102位于硅衬底106中。穿过金属化层中的互连线路(金属线和通孔，图中未显示)，TSV 102电连接到焊垫108上，其中焊垫108位于芯片104的前表面上。TSV 102以铜柱的形式穿过衬底106的后表面暴露出来。当芯片104键合到其它芯片上时，TSV 102键合到其他芯片的焊垫上，它们之间具有或者没有焊料。这种方案存在缺陷。由于TSV键合需要TSV之间具有相对较大的间距，因此限制了TSV的位置，并且TSV之间的距离需要足够大以允许容纳例如焊球。因此，需要新的背面结构。
发明内容
根据本发明的一个方面，一种集成电路结构包括具有前面和背面的半导体衬底。穿透硅通孔穿过所述半导体衬底，并包括延伸到所述半导体衬底背面的后端。再分布线形成在所述半导体衬底背面上方，并连接到所述穿透硅通孔后端。钝化层位于所述再分布线上方并具有开口，其中所述再分布线的一部分顶面和所述再分布线的侧壁通过所述开口暴露。金属整精层形成在开口中，并与所述再分布线的所述部分顶面和侧壁接触。
根据本发明的另一方面，一种集成电路结构包括具有前面和背面的半导体衬底。穿透硅通孔穿过所述半导体衬底，并包括超出所述半导体衬底背面延伸的后端。再分布线位于所述半导体衬底背面上方，并连接到所述穿透硅通孔后端。所述再分布线包括：与所述穿透硅通孔接触的再分布线带；和宽度大于所述再分布线带宽度的再分布线垫。所述集成电路结构还包括位于所述再分布线上方的钝化层；位于所述钝化层中的开口，其中所述再分布线垫的基本所有侧壁通过所述开口暴露；以及位于所述开口中并与所述再分布线垫侧壁接触的金属整精层。所述金属整精层与所述再分布线垫的基本所有侧壁接触，并且所述金属整精层的顶面高于所述钝化层的顶面。
根据本发明的又一方面，一种集成电路结构包括具有前面和背面的半导体衬底；以及穿过所述半导体衬底的穿透硅通孔。所述穿透硅通孔包括超出所述半导体衬底背面延伸的后端。再分布线位于所述半导体衬底背面上方，并连接到所述穿透硅通孔后端。所述再分布线具有顶部窄于对应底部的锥形轮廓。所述集成电路结构还包括位于所述再分布线上方的钝化层；以及位于所述钝化层中的开口。部分的所述再分布线垫通过所述开口暴露。金属整精层形成在所述开口中，并与所述部分的再分布线接触。金属整精层可以包括镍层、钯层及/或金层。
本发明的优点包括改善金属整精层与再分布线之间的粘结力。此外，本发明更容易清除残留物，从而产生更可靠的焊接结构。
附图说明
为了更全面地理解本发明及其优点，现在将结合附图给出下面的详细说明，其中：
图1显示了一种包括穿透硅通孔(TSV)的传统集成电路结构，其中TSV穿过衬底背面突出并以铜柱的形式键合到另一个芯片的焊垫上；
图2至图8为根据本发明实施例的制造中间阶段的顶视图和横截面图。
具体实施方式
下面，将对本发明的优选实施例的实现及使用做出讨论。但是，应当了解本发明提供许多可应用的发明概念，这些发明概念可以体现在各种特定环境下。文中讨论的特定实施例仅阐述了本发明的实现及使用的特定方式，并不用来限制本发明的保护范围。
本发明实施例提供了一种连接到穿透硅通孔(TSV)的新式背面连接结构及其形成方法。附图显示了本发明优选实施例的制造中间阶段，并对优选实施例的变化进行描述。在贯穿本发明的不同附图和图示实施例中，相似的参考数字用来指示类似的元件。
现在参考图2，提供了一个包括衬底10和位于衬底10内部的集成电路(图中未显示)的芯片2。衬底10优选为半导体衬底，例如体硅衬底，但是它也可以包括其他半导体材料，例如III族、IV族以及/或者V族元素。半导体器件，例如晶体管(图中未显示)可以形成在衬底10的前表面(图2中朝下的表面)上。包括形成在其中的金属线和通孔(图中未显示)的互连结构12形成在衬底10的下方，并连接到半导体器件上。这些金属线和通孔可以由铜或者铜合金形成，并且可以利用公知的镶嵌工艺形成。互连结构12可以包括公知的层间电介质(ILD)和金属间电介质(IMD)。焊垫14形成在芯片2前表面的前面(图2中朝下的侧)，并突出于前表面。
TSV 20形成在衬底10中，并从后表面(图2中朝上的表面)延伸到前表面(该表面上形成有有源电路)。在如图2所示的第一实施例中，TSV 20利用先通孔方式形成，并且在形成互连结构12之前形成。因此，TSV 20仅延伸到用来覆盖有源器件的ILD上，并没有延伸到互连结构12的IMD层中。在替代实施例中，TSV 20利用后通孔方式形成，并且在形成互连结构12之后形成。因此，TSV 20穿过衬底10和互连结构12。绝缘层22形成在TSV20的侧壁，并且将TSV20与衬底10电绝缘。绝缘层22可以由普通使用的电介质材料，例如氮化硅、氧化硅(例如四乙基原硅酸盐TEOS氧化物)等形成。
TSV 20穿过衬底10的后表面暴露并向外突出。优选地，形成背面绝缘层24来覆盖衬底10的背面。在一个实施例中，背面绝缘层24的形成包括：蚀刻衬底10的后表面，覆盖形成背面绝缘层24，以及执行轻微化学机械抛光以去除直接位于TSV 20上方的部分背面绝缘层24。因此，穿过背面绝缘层24中的开口暴露出TSV 20。在替代实施例中，穿过其暴露出TVS20的背面绝缘层24中的开口可以通过蚀刻工艺形成。
参考图3，薄种子层26，也称作为凸点下金属层(UBM)被覆盖形成在背面绝缘层24和TSV 20上。UBM 26可以使用的材料包括铜或者铜合金。但是，其他金属例如银、金、铝以及它们的组合也可以包括。在一个实施例中，UBM 26是利用溅射工艺形成。在另一实施例中，可以使用物理气相沉积(PVD)或者电镀。
图3也显示了掩模46的形成。掩模46可以由光致抗蚀剂形成，其中光致抗蚀剂可以是干薄膜或者液态光抗蚀剂。然后，图案化掩模46，从而形成掩模46中的开口50，并且TSV 20穿过开口50被暴露。
在图4中，开口50选择性地填充有金属化材料，从而在开口50中形成再分布线(RDL)52。由于TSV 20从衬底10的后表面向外突出，因此TSV 20延伸到RDL 52内部。这有利地增加了TSV 20与RDL 52之间结合的强度。在一个实施例中，填充材料包括铜或者铜合金，但是其他金属，例如银、金、铝以及它们的组合也可以包括。该形成方法优选包括电化学镀(ECP)、电镀或者其它公开使用的沉积方法，例如溅射、印刷及化学气相沉积(CVD)方法等。然后，除去掩模46。因此，将位于掩模46下方的部分UBM 26暴露出来。
参考图5，通过闪光蚀刻(flash etching)除去暴露的部分UBM 26。保留的RDL 52可以包括RDL带(也称为再分布迹线)521，其包括直接位于TSV20正上方并与其连接的部分，所述RDL52还可选地包含与RDL带521连接的RDL垫522。RDL 52可能的顶视图如图7A及图7B所示。在图5及随后的附图中，没有显示UBM 26，由于UBM 26通常由类似于RDL 52的材料形成，因而其与RDL 52结合出现。在优选实施例中，RDL 52具有锥形轮廓，其中顶部宽度和顶部长度大于对应的底部宽度和底部长度。换言之，RDL 52的侧壁53以小于90度的内角α倾斜，并且优选小于大约80度，更优选地为小于大约70度。这样的锥形轮廓可以通过在除去暴露的部分UBM 26的闪光蚀刻中执行过度蚀刻来形成，例如通过将蚀刻时间延长到除去暴露的UBM 26所需时间的两倍或三倍。有利地，利用具有锥形轮廓的RDL 52，在钝化层56图案化过程中容易将不需要的部分钝化层56充分移除。
然后如图6A所示，覆盖形成钝化层56，并进行图案化以形成开口58。钝化层56可以由氮、氧、聚酰亚胺等形成。部分RDL垫522通过钝化层56中的开口58暴露出。优选地，除RDL垫522中心部分之外，RDL垫522的侧壁也通过开口58暴露。RDL带521保持由钝化层56覆盖。应当了解，一个芯片可以包括多个TSV 20，如图6B所示，其中该图为芯片2的顶视图。在优选实施例中，整个芯片2上的开口58的尺寸基本上一致的。一致尺寸的开口58使得焊接各个TSV所需的焊料为相同量，因此减少了具有冷接(cold-joint)或非连接(non-joint)的可能性。
图7A显示了开口58和RDL 52的顶视图。优选地，RDL 52的至少一个侧壁53通过开口58暴露。因此，剩余部分的钝化层56优选与侧壁53间隔开。开口58可以具有比RDL垫522更大的面积，并因此全部的(或者基本上全部的，例如大于约90％的部分)RDL垫522通过开口58暴露。因此，RDL垫522其他侧壁53也暴露出。或者，仅暴露出部分的RDL垫522。在一个实施例中，RDL带521的宽度W1为大约5μm到大约1.5μm之间。RDL垫522的宽度W2为大约60μm到大约80μm之间，同时开口58具有大约为100μm的宽度W3。请注意，图示结构的尺寸没有按照比例绘制。在替代实施例中，如图7B所示，RDL 52不具有比RDL带521宽的RDL垫522。因此，开口58仅暴露RDL带521，并且优选包括RDL带521的端部。
接着，如图8所示，在开口58中形成金属整精层60。金属整精层60的形成方法包括EPC、化学镀及类似方法等。在优选实施例中，金属整精层60包括直接位于RDL垫522上方并与其接触的镍层62。选择地，例如金层66或者钯层64上的金层66的附加层可以形成在镍层62上。镍层62的厚度大于钝化层56的厚度，因此镍层62的顶面高于钝化层56顶面。钯层64和金层66的形成进一步增加了金属整精层60的高度，从而芯片2与其所在的对应晶片之间的间距足够用于后续封装步骤中将填充的底层填料的流动。利用上述金属整精的形成，则不需要在开口58中形成铜垫，或者在开口58中形成共熔焊垫，其中共熔焊垫通常包括例如由Sn-Pb合金形成的共熔焊接材料。
本发明的实施例具有多个优点。通过形成具有锥形轮廓的再分布线，容易将例如钝化层残留物的残渣清除，尤其是靠近RDL侧壁的区域。利用接触RDL带和/或RDL垫侧壁的金属整精层，可以改善金属整精层与对应底层RDL之间的粘结力，从而产生更可靠的封装结构。
虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种变化、替换和修改。此外，本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容，作为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤，其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进行应用。因此，本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。

Claims (14)

1.一种集成电路结构，包括：
包括前面和背面的半导体衬底；
穿过所述半导体衬底的穿透硅通孔，所述穿透硅通孔包括延伸到所述半导体衬底背面的后端；
位于所述半导体衬底背面上方并连接到所述穿透硅通孔后端的再分布线；
位于所述再分布线上方并具有开口的钝化层，其中所述再分布线的一部分顶面和与所述一部分顶面邻接的侧壁通过所述开口暴露出；以及
与所述再分布线的暴露的部分顶面和侧壁接触的金属整精层，
其中所述穿透硅通孔的后端延伸到所述再分布线中。
2.如权利要求1所述的集成电路结构，其中所述再分布线包括：
连接到所述穿透硅通孔的再分布线带；
宽度大于所述再分布线带宽度的再分布线垫，其中通过所述开口暴露的所述再分布线的侧壁包括所述再分布线垫的侧壁。
3.如权利要求2所述的集成电路结构，其中所述再分布线垫的基本所有侧壁都通过所述开口暴露，并且其中所述金属整精层与所述再分布线垫的基本所有侧壁接触。
4.如权利要求1所述的集成电路结构，其中基本上全部的所述再分布线具有大体一致的宽度，其中所述再分布线包括位于所述穿透硅通孔相对侧上的第一端和第二端，其中通过所述开口暴露的所述再分布线的侧壁属于所述第一端。
5.如权利要求1所述的集成电路结构，其中所述金属整精层包括镍层；或者，其中所述金属整精层还包括在所述镍层之上的金层；或者，所述金属整精层还包括在所述镍层与所述金层之间并连接所述镍层与所述金层的钯层。
6.如权利要求1所述的集成电路结构，其中面向所述再分布线侧壁的所述钝化层边缘与所述金属整精层的对应边缘间隔开。
7.一种集成电路结构，包括：
包括前面和背面的半导体衬底；
穿过所述半导体衬底的穿透硅通孔，所述穿透硅通孔包括超出所述半导体衬底背面延伸的后端；
位于所述半导体衬底背面上方并连接到所述穿透硅通孔后端的再分布线，所述再分布线包括：
与所述穿透硅通孔接触的再分布线带；和
宽度大于所述再分布线带宽度的再分布线垫，其中所述再分布线垫与所述再分布线带连接；
位于所述再分布线上方的钝化层；
位于所述钝化层中的开口，其中所述再分布线垫的基本所有侧壁通过所述开口暴露；以及
位于所述开口中并与所述再分布线垫侧壁接触的镍层，其中所述镍层与所述再分布线垫的基本所有侧壁接触，并且其中所述镍层的顶面高于所述钝化层的顶面。
8.如权利要求1或7所述的集成电路结构，其中所述再分布线远离所述半导体衬底的边的宽度窄于与之相对的邻近所述半导体衬底的边的宽度。
9.如权利要求7所述的集成电路结构，还包括位于所述镍层上方的金层；或者还包括位于所述镍层与所述金层之间并连接所述镍层与所述金层的钯层。
10.一种集成电路结构，包括：
包括前面和背面的半导体衬底；
穿过所述半导体衬底的穿透硅通孔，所述穿透硅通孔包括超出所述半导体衬底背面延伸的后端；
位于所述半导体衬底背面上方并连接到所述穿透硅通孔后端的再分布线，其中所述再分布线远离所述半导体衬底的边的宽度窄于与之相对的邻近所述半导体衬底的边的宽度；
位于所述再分布线上方的钝化层；
位于所述钝化层中的开口，其中部分的所述再分布线通过所述开口暴露；以及
位于所述开口中并与所述部分的再分布线接触的金属整精层。
11.如权利要求10所述的集成电路结构，其中所述再分布线通过所述开口暴露的侧壁与所述金属整精层接触。
12.如权利要求10所述的集成电路结构，其中所述再分布线包括：
连接到所述穿透硅通孔的再分布线带；
宽度大于所述再分布线带宽度的再分布线垫，其中与所述金属整精层接触的所述再分布线的侧壁为所述再分布线垫的侧壁。
13.如权利要求12所述的集成电路结构，其中所述再分布线垫的基本所有侧壁都通过所述开口暴露，并都与所述金属整精层接触。
14.如权利要求10所述的集成电路结构，其中基本上全部的所述再分布线具有大体一致的宽度，其中所述再分布线包括位于所述穿透硅通孔相对侧上的第一端和第二端，并且其中所述第一端的侧壁与所述金属整精层接触。
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US20110165776A1 (en) 2011-07-07
US8461045B2 (en) 2013-06-11
TW201023330A (en) 2010-06-16
US20100090319A1 (en) 2010-04-15
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KR101109559B1 (ko) 2012-01-31
TWI397985B (zh) 2013-06-01

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