CN101728371B - 集成电路结构 - Google Patents

集成电路结构 Download PDF

Info

Publication number
CN101728371B
CN101728371B CN200910179462.3A CN200910179462A CN101728371B CN 101728371 B CN101728371 B CN 101728371B CN 200910179462 A CN200910179462 A CN 200910179462A CN 101728371 B CN101728371 B CN 101728371B
Authority
CN
China
Prior art keywords
joint sheet
patterning
integrated circuit
silicon
positions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN200910179462.3A
Other languages
English (en)
Other versions
CN101728371A (zh
Inventor
余振华
邱文智
吴文进
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN101728371A publication Critical patent/CN101728371A/zh
Application granted granted Critical
Publication of CN101728371B publication Critical patent/CN101728371B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/16106—Disposition relative to the bonding area, e.g. bond pad the bump connector connecting one bonding area to at least two respective bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明公开一种集成电路结构，包括一半导体芯片，其还包括一第一表面以及一第一图案化接合垫，露出于第一表面。第一图案化接合垫包括彼此电性连接的多个部位以及位于其内的至少一开口。集成电路结构还包括一介电材料，填入开口的至少一部分。本发明提供的集成电路结构能够降低大型接合垫制作中的碟化效应，因而改善接合垫的品质。

Description

集成电路结构
技术领域
本发明涉及一种集成电路，尤其涉及一种接合垫（bond pad）的设计。
背景技术
自集成电路的发明创造以来，由于各个电子部件（即，晶体管、二极管、电阻、电容等等）的集成度（integration density）持续的改进，使半导体业持续不断的快速成长发展。主要来说，集成度的改进来自于最小特征尺寸（minimum feature size）不断缩小而容许更多的部件整合至既有的芯片面积内。
这些集成度的改进实质上是朝二维（two-dimensional,2D）方面的，因为集成部件所占的体积实际上位于半导体晶片的表面。尽管微影（lithography）技术的精进为2D集成电路制作带来相当大的助益，二维空间所能拥有的密度还是有其物理限制。这些限制其中之一在于制作这些部件所需的最小尺寸。再者，当更多的装置放入一芯片中，需具备更复杂的电路设计。
另外的一个限制因素来自于当装置的数量增加时，装置之间内连线（interconnection）的长度及数量也明显增加。
为了解决上述限制因素，已开始创作三维（3D）集成电路（three-dimensional integrated circuit,3DIC）。在典型的3DIC制造工艺中形成二个具有集成电路的晶片。接着连同装置对准而接合上述晶片。硅通孔电极（through-silicon vias,TSV）可用于两晶片上装置的内连接。
传统接合两晶片的方法包括胶合法（adhesive bonding）、直接覆铜法（direct copper bonding）及直接覆氧化物法（direct oxide bonding）。一般所使用的直接覆铜法中，每一晶片具有铜接合垫露出于晶片的表面，并通过施加高压来接合两晶片，使铜接合垫彼此接合例如，在彼此上方接合两个芯片。
由于客制化（customized）电路需求，有些需要大的接合垫。这些大的接合垫面临一些问题。图1示出经由大型接合垫进行两晶片的接合。芯片2包括大型接合垫4而芯片6包括大型接合垫8。接合垫4及8是以直接覆铜法进行接合。在接合垫4及8的制造中，通常需进行化学机械研磨（chemicalmechanical polish,CMP）。然而，由于接合垫4及8较大，接合垫4及8的各自区域属图案密集区。因此，当进行CMP制造工艺以形成接合垫4及8的期间，会发生碟化效应（dishing effect），使接合垫4及8中心区域磨除的比边缘区域来得多。
可从图1发现到碟化效应所引发的各种问题。首先，接合可靠度受到严重的影响。由于碟化效应，只有少部分的接合垫4及8彼此接合，因而接合不佳。第二，由于接合面缩小，导致流经接合面的电流降低。这些问题导致大型接合垫的设计目的失效，因而有待解决。
发明内容
本发明一实施例提供一种集成电路结构，包括一半导体芯片，该半导体芯片包括：一第一介电材料，位于一半导体基底的一第一表面上；一第二介电材料，位于该半导体基底的一第二表面上；一第一图案化接合垫，位于该第一介电材料内且突出于该第一介电材料，其中该第一图案化接合垫包括多个部位以及电性内连接所述多个部位的多个内连线，且该第一图案化接合垫内包括至少一开口，使该第一介电材料延伸于该开口内；一未图案化接合垫，位于该第二介电材料内且突出于该第二介电材料，其中该未图案化接合垫为实心，其内不具有开口；多个硅通孔电极，位于该半导体基底内，且电性连接该第一图案化接合垫与该未图案化接合垫；以及一实心接合垫，与该第一图案化接合垫位于同一层位而未与其电性连接且露出于该第一介电材料，其中该实心接合垫小于该第一图案化接合垫。
本发明另一实施例提供一种集成电路结构，包括一半导体芯片，该半导体芯片包括：一第一表面及相对于该第一表面的一第二表面；一第一图案化接合垫，突出于该第一表面，其中该第一图案化接合垫包括彼此电性连接的多个部位以及位于所述多个部位之间的多个开口；多个连接结构，以连接该第一图案化接合垫的所述多个部位；一半导体基底，位于该第一图案化接合垫下方；一硅通孔电极，位于该半导体基底内且电性连接至该第一图案化接合垫；一未图案化接合垫，突出于该第二表面，其中该未图案化接合垫包括彼此电性连接的多个附加的部位；一附加的硅通孔电极，位于该半导体基底内且相邻于该硅通孔电极，其中该硅通孔电极与该附加的硅通孔电极均将该第一图案化接合垫的所述多个部位的其中一个连接至该未图案化接合垫的所述多个部位的其中一个；以及一实心接合垫，露出于该第一表面，其中该实心接合垫小于该第一图案化接合垫。
本发明又另一实施例提供一种集成电路结构，包括：第一及第二半导体芯片。第一半导体芯片，包括一第一表面以及一第一图案化接合垫，露出于第一表面。第一图案化接合垫包括彼此电性连接的多个部位以及位于这些部位之间的多个开口。其中该第一半导体芯片还包括一实心接合垫，露出于该第一表面且未与该第一图案化接合垫电性连接，该实心接合垫小于该第一图案化接合垫。第二半导体芯片，包括一第二表面以及一第二图案化接合垫，露出于第二表面，且经由直接接合而接合至第一图案化接合垫。
本发明的特征的优点包括降低大型接合垫制作中的碟化效应，因而改善接合垫的品质。
附图说明
图1示出传统具有大型接合垫的接合，其中大型接合垫发生碟化效应。
图2示出根据本发明实施例的剖面示意图，其中大型接合垫内具有开口。
图3A至图3D示出图2中接合垫的平面示意图。
图4A示出图3A中接合垫沿4A-4A’线的剖面示意图。
图4B示出图3B中接合垫沿4B-4B’线的剖面示意图。
图5示出根据本发明实施例的多个硅通孔电极连接至相同大型接合垫。
图6示出芯片正面对正面（face to face）接合。
图7示出芯片正面对背面（face to back）接合。
图8A至图8C示出从相同的接合芯片对中不同面的剖面示意图。
其中，附图标记说明如下：
公知
2、6～芯片；
4、8～大型接合垫。
实施例
10、110～半导体芯片；
20～半导体基底；
24～内连结构；
26～介电层；
30、30’～金属线；
32、32’～介层窗；
40、50、501、502、503～硅通孔电极；
42、52、62、72、152～接合垫；
521～部位；
522～内连部位；
53～开口；
64、74～重布局线。
具体实施方式
以下说明本发明实施例的制作与使用。然而，必须了解的是本发明提供许多适当的实施例的发明概念，可实施于不同的特定技术背景。述及的特定实施例仅用于说明以特定的方法来制作及使用本发明，而并非用以局限本发明的范围。
本发明实施例提供一种改良的接合垫结构，其适用于半导体芯片中。本发明一实施例中，接合垫的一较佳设计为内部具有狭缝/开口，以降低局部的图案密度。其具有将碟化效应最小化的优点。以下将说明本发明诸多实施例，可使用于，例如，直接金属对金属接合（direct metal-to-metal bonding）的技术背景。然而，本发明任何的实施例亦可应用于其他技术背景。
图2示出一半导体芯片10，其为晶片的一部分。半导体芯片10包括半导体基底20，其可由一般公知的半导体材料所构成，例如硅、硅锗等等。集成电路（未示出）形成于半导体基底20的表面，其中集成电路包括互补式金属氧化物半导体（complementary metal-oxide-semiconductor,CMOS）晶体管以及其他装置，诸如电容、电阻等等。集成电路上方为内连结构24，其包括多个介电层26，包括但不限定为金属层间介电（inter-metal dielectric,IMD）层、保护（passivation）层等等。内连结构24内连至下方的集成电路，且将集成电路与硅通孔电极（TSV）40及50连接至各自的接合垫42及52，其形成于半导体芯片10的正面。在整个说明叙述中，半导体芯片10靠近内连结构24的一侧（此处为顶侧）称为正面，而与其相对的一侧则称为背面。
如所公知一般，IMD层26可由低介电常数（low-k）材料所构成，举例来说，其k值低于2.5。金属线30及介层窗（via）32形成于介电层26内，且可为利用公知镶嵌（damascene）制造工艺所构成的铜，或是由其他金属所构成，例如铝、钨、银等等。
在本发明一实施例中，半导体芯片10包括硅通孔电极40及50，其延伸贯穿基底20，且将正面的特征元件（feature）内连至基底的背面。硅通孔电极40电性连接至接合垫42，而硅通孔电极50电性连接至接合垫52，其中硅通孔电极40及50皆形成于半导体芯片的正面。接合垫42及52同时形成，因而由同一材料所构成。在本发明一实施例中，接合垫42小于接合垫52（对于上视而言）。硅通孔电极50的截面积大于或等于硅通孔电极40（对于上视而言）。因此，接合垫42及硅通孔电极40可用于传送一相对小的电流，例如信号电流，而接合垫52及硅通孔电极50可用于传送一相对大的电流，例如供电电流。接合垫42未与接合垫52电性连接。
在本发明一实施例中，接合垫42为内部不具有狭缝或开口的实心接合垫。另一方面，接合垫52内部具有图案化的开口。图3A至图3D为接合垫52的诸多可能的设计平面示意图。在整个说明叙述中，图3A至图3D所示的接合垫52称为图案化接合垫。图3A及图3B所示的接合垫52皆包括被开口53所隔开的部位521及连接部位521的内连部位522。内连部位522与部位521由同一层所构成。
另一方面，图3C示出另一实施例，其中接合垫52包括多个被开口53所隔开的分离部位521。在接合垫52所处的膜层中，分离的部位521之间并无电性连接，而是通过下方介层窗及金属线来电性连接。在一实施例中，如图2所示，分离的部位521之间的电性连接是通过金属线30’及介层窗32’。金属线30’及介层窗32’可由接合垫52正下方的一金属化层（或位于保护层内）所构成，其可为一顶部金属化层（一般称为Mtop）或一重布局（redistribution）层。在其他实施例中，分离的部位521之间的电性内连接可通过底部金属化层（一般称为M1）至顶部金属化层Mtop之间任何的金属化层。在图3A至图3C中所示的结构中，接合垫52可视为一完整的接合垫，亦即任何接合垫部位521的连接等同于其他部位的连接。
可结合图3A、3B及3C所示实施例而构成另一实施例，在该结合的实施例中，一些部位521通过多个群组的内连部位522进行内连接，而不同群组的内连部位522并未彼此连接。图3D示出一实施例，其中每一行的部位521是内连接的，而行与行之间是不连接的。此外，至少一位于下方的介层窗32’连接至每一行，且这些介层窗32’市内连接的（如图2所示）。
请参照图3A至3D，至少局部的开口53填有介电材料。请参照图2，至少开口53的下半部填有多个介电层26中顶层的材料。
采用图3A或图3B所示的实施例时，会有一个以上的介层窗32’连接至接合垫部位521，如图2所示。另外，由于部位521已内连接，仅有一个介层窗32’（请参照图2）形成且连接至单一的接合垫部位521（请参照图3A及图3B）。然而，采用图3C或图3D所示的实施例时，每一分离的部位521必须有一下方的介层窗32’与其连接。否则没有介层窗32’的部位521将无法连接至其他部位。
需注意的是依据图2所示的剖面图，接合垫52的剖面可为本体接合（solidbond），如图4A所示，或是一连续的接合垫，如图4B所示。图4A是图3A的平面中沿4A-4A’线的剖面示意图，而图4B示出图3B的平面中沿4B-4B’线的剖面示意图。
整个半导体芯片10（也可能是整个晶片）中，临界横向尺寸（thresholdlateral dimension）较佳为既定的，且任何横向尺寸大于临界横向尺寸的接合垫的图案化设计示出于图3A至图3D。举例而言，当任何横向尺寸（宽度及/或长度）小于临界横向尺寸的接合垫时，接合垫为实心的。
请参照图2，在半导体芯片10的背面上可形成接合垫62及72。在一实施例中，接合垫62及72的规格分别相似于接合垫42及52。因此，接合垫72可大于接合垫62。此外，接合垫72的结构本质上可相同于图3A至4B所示的结构。重布局线64及74可形成于基底20的背面，以将接合垫62连接至硅通孔电极40，且将接合垫72连接至硅通孔电极50。重布局线64及74的制作细节为公知技术，在此不再予以赘述。在另一实施例中，可将硅通孔电极40及50以铜柱的形式（同样作为接合之用）露出于基底20的背面来取代接合垫62及72。
图5示出另一实施例，以利用一个以上硅通孔电极电性连接至一相同的接合垫来取代利用单一硅通孔电极内连接位于基底20两相对侧的特征元件。需注意的是虽然图5中所示的接合垫52具有分离的部位，其可具有图3A、3B、3C或3D所示的结构。另一方面，虽然图5中所示的接合垫72为一连续片，其也可具有图3A、3B、3C或3D所示的结构。因此，硅通孔电极501、502及503可通过接合垫52或72任一者而电性内连接。另外，相似于金属线30及重布局线74（请参照图2）的金属线及/或重布局线可用于内连接硅通孔电极501、502及503。
图6示出半导体芯片正面对正面（face to face）接合。半导体芯片110可具有相同或不同于图2至图5的结构。
采用本发明实施例的益处在于大型接合垫52及152的制作无须担心发生碟化效应（发生于制作接合垫52及152时所进行的化学机械研磨）。如此一来，接合垫52及152的表面更为平坦。当进行直接接合时，接合垫52有更多的部分可与接合垫152直接接合，使接合更为稳靠而能够传导更大的电流。图8A、8B及8C示出接合垫52及152之间三种可能的接合方式剖面示意图，其中由于不同的剖面位置（请参照图4A及4B）及/或接合垫52及152具有相同或不同的结构而呈现出不同的图面。
以上所述的实施例也可应用于正面对背面（face to back）接合，如图7所示。再者，同样可应用于背面对背面（back to back）接合（未示出）。本领域普通技术人员可理解其中各自的结构。
本发明实施例具有许多的有益的特点。在接合垫内形成开口/狭缝，接合垫局部的图案密度会降低，至少可降低甚至完全消除CMP所引发的碟化效应。而本发明实施例无需额外制造工艺步骤，使本发明能够在不增加制造成本的情形下获益。
虽然本发明已以较佳实施例公开如上，然其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明之精神和范围内，当可作更动与润饰。再者，本发明之保护范围并未局限于说明书内所述特定实施例中的制造工艺、机器、制造、物质组成、装置、方法及步骤，任何所属技术领域中具有通常知识者可从本发明公开内容中理解现行或未来所发展出的制造工艺、机器、制造、物质组成、装置、方法及步骤，只要可以在此处所述实施例中实施大体相同功能或获得大体相同结果皆可使用于本发明中。因此，本发明之保护范围包括上述制造工艺、机器、制造、物质组成、装置、方法及步骤。

Claims (11)

1.一种集成电路结构，包括：
一第一半导体芯片，包括：
一第一介电材料，位于一半导体基底的一第一表面上；
一第二介电材料，位于该半导体基底的一第二表面上；
一第一图案化接合垫，位于该第一介电材料内且突出于该第一介电材料，其中该第一图案化接合垫包括多个部位以及电性内连接所述多个部位的多个内连线，且该第一图案化接合垫内包括至少一开口，使该第一介电材料延伸于该开口内；其特征在于，还包括：
一未图案化接合垫，位于该第二介电材料内且突出于该第二介电材料，其中该未图案化接合垫为实心，其内不具有开口；
多个硅通孔电极，位于该半导体基底内，且电性连接该第一图案化接合垫与该未图案化接合垫；以及
一实心接合垫，与该第一图案化接合垫位于同一层位而未与其电性连接且露出于该第一介电材料，其中该实心接合垫小于该第一图案化接合垫。
2.如权利要求1所述的集成电路结构，其中所述多个内连线与所述多个部位由同一层所构成。
3.如权利要求1所述的集成电路结构，其中所述多个部位为分离的，且其中所述多个内连线与所述多个部位由不同层所构成。
4.如权利要求1所述的集成电路结构，还包括：
一第二半导体芯片，包括
一第三表面；以及
一第二图案化接合垫，露出于该第三表面，其中该第二图案化接合垫包括彼此电性连接的多个附加的部位，且其中该第二图案化接合垫内包括至少一开口，而该第一图案化接合垫经由直接接合而接合至该第二图案化接合垫。
5.一种集成电路结构，包括：
一半导体芯片，包括
一第一表面及相对于该第一表面的一第二表面；
一第一图案化接合垫，突出于该第一表面，其中该第一图案化接合垫包括彼此电性连接的多个部位以及位于所述多个部位之间的多个开口；
多个连接结构，以连接该第一图案化接合垫的所述多个部位；
一半导体基底，位于该第一图案化接合垫下方；
一硅通孔电极，位于该半导体基底内且电性连接至该第一图案化接合垫；其特征在于，还包括：
一未图案化接合垫，突出于该第二表面，其中该未图案化接合垫包括彼此电性连接的多个附加的部位；
一附加的硅通孔电极，位于该半导体基底内且相邻于该硅通孔电极，其中该硅通孔电极与该附加的硅通孔电极均将该第一图案化接合垫的所述多个部位的其中一个连接至该未图案化接合垫的所述多个部位的其中一个；以及
一实心接合垫，露出于该第一表面，其中该实心接合垫小于该第一图案化接合垫。
6.如权利要求5所述的集成电路结构，其中所述多个连接结构由构成该第一图案化接合垫或该未图案化接合垫的一层所构成。
7.如权利要求5所述的集成电路结构，其中所述多个连接结构由位于该第一图案化接合垫与该半导体基底之间的一金属化层或位于该半导体基底与该未图案化接合垫之间的一层所构成。
8.一种集成电路结构，包括：
一第一半导体芯片，包括
一第一表面；
一第一图案化接合垫，露出且突出于该第一表面，其中该第一图案化接合垫包括彼此电性连接的多个部位以及位于所述多个部位之间的多个开口；其特征在于，还包括：
一实心接合垫，露出于该第一表面且未与该第一图案化接合垫电性连接，该实心接合垫小于该第一图案化接合垫，以及
一第二半导体芯片，包括
一第二表面；以及
一第二图案化接合垫，露出且突出于该第二表面，且经由直接接合而接合至该第一图案化接合垫，使该第一表面与该第二表面之间具有一间隙空间。
9.如权利要求8所述的集成电路结构，其中该第一半导体芯片还包括：
一半导体基底，位于该第一表面下方；以及
一硅通孔电极，位于该半导体基底内，且电性连接至该第一图案化接合垫。
10.如权利要求8所述的集成电路结构，其中该第二半导体芯片还包括一附加的实心接合垫，露出于该第二表面，该附加的实心接合垫接合至该实心接合垫。
11.如权利要求8所述的集成电路结构，还包括：
一第三图案化接合垫，位于该第一半导体芯片内，且位于该第一半导体芯片的该第一图案化接合垫的一相对侧；以及
多个硅通孔电极，位于该第一半导体芯片内，每一硅通孔电极将该第一图案化接合垫的所述多个部位的其中一个连接至该第三图案化接合垫的多个附加的部位的其中一个。
CN200910179462.3A 2008-10-21 2009-10-20 集成电路结构 Active CN101728371B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/255,060 2008-10-21
US12/255,060 US8053900B2 (en) 2008-10-21 2008-10-21 Through-substrate vias (TSVs) electrically connected to a bond pad design with reduced dishing effect

Publications (2)

Publication Number Publication Date
CN101728371A CN101728371A (zh) 2010-06-09
CN101728371B true CN101728371B (zh) 2014-03-12

Family

ID=42108001

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200910179462.3A Active CN101728371B (zh) 2008-10-21 2009-10-20 集成电路结构

Country Status (5)

Country Link
US (1) US8053900B2 (zh)
JP (1) JP5430338B2 (zh)
KR (1) KR101107806B1 (zh)
CN (1) CN101728371B (zh)
TW (1) TWI399842B (zh)

Families Citing this family (66)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8134235B2 (en) 2007-04-23 2012-03-13 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional semiconductor device
US8264067B2 (en) * 2009-10-09 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Through silicon via (TSV) wire bond architecture
US8304863B2 (en) * 2010-02-09 2012-11-06 International Business Machines Corporation Electromigration immune through-substrate vias
KR20110134198A (ko) * 2010-06-08 2011-12-14 삼성전자주식회사 관통 전극을 갖는 반도체 장치
CN102299133B (zh) * 2010-06-22 2014-02-19 中国科学院微电子研究所 半导体结构及其制造方法
JP5709418B2 (ja) 2010-06-30 2015-04-30 キヤノン株式会社 固体撮像装置
JP5610905B2 (ja) 2010-08-02 2014-10-22 パナソニック株式会社 半導体装置
US9224647B2 (en) * 2010-09-24 2015-12-29 Stats Chippac, Ltd. Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer
US8766457B2 (en) * 2010-12-01 2014-07-01 SK Hynix Inc. Bonding structure of semiconductor package, method for fabricating the same, and stack-type semiconductor package
JP5922331B2 (ja) * 2011-02-02 2016-05-24 ラピスセミコンダクタ株式会社 半導体装置の配線構造及びその製造方法
KR102235927B1 (ko) 2011-05-24 2021-04-05 소니 주식회사 반도체 장치
US8896125B2 (en) 2011-07-05 2014-11-25 Sony Corporation Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
JP5982748B2 (ja) * 2011-08-01 2016-08-31 ソニー株式会社 半導体装置、半導体装置の製造方法、および電子機器
US8697493B2 (en) * 2011-07-18 2014-04-15 Soitec Bonding surfaces for direct bonding of semiconductor structures
FR2978606B1 (fr) * 2011-07-27 2014-02-21 Soitec Silicon On Insulator Surfaces de liaison améliorées pour le collage direct de structures semi-conductrices
TWI493690B (zh) * 2011-07-18 2015-07-21 Soitec Silicon On Insulator 半導體構造直接鍵結之改良鍵結表面
JP5682496B2 (ja) * 2011-07-28 2015-03-11 富士通セミコンダクター株式会社 半導体装置、マルチチップ半導体装置、デバイス、及び半導体装置の製造方法
KR20130016466A (ko) 2011-08-08 2013-02-18 삼성전자주식회사 반도체 패키지
US8642385B2 (en) * 2011-08-09 2014-02-04 Alpha & Omega Semiconductor, Inc. Wafer level package structure and the fabrication method thereof
JP2013131738A (ja) * 2011-11-24 2013-07-04 Elpida Memory Inc 半導体装置
JP5922915B2 (ja) 2011-12-02 2016-05-24 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8710607B2 (en) 2012-07-12 2014-04-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for image sensor packaging
US8895360B2 (en) * 2012-07-31 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated semiconductor device and wafer level method of fabricating the same
US9699897B2 (en) * 2012-09-28 2017-07-04 Taiwan Semiconductor Manufacturing Company Limited Pad structure
US8912844B2 (en) 2012-10-09 2014-12-16 United Microelectronics Corp. Semiconductor structure and method for reducing noise therein
JP2014107308A (ja) * 2012-11-22 2014-06-09 Toshiba Corp 半導体装置及びその製造方法
US9035457B2 (en) 2012-11-29 2015-05-19 United Microelectronics Corp. Substrate with integrated passive devices and method of manufacturing the same
JP6017297B2 (ja) * 2012-12-14 2016-10-26 オリンパス株式会社 半導体装置の製造方法
US8716104B1 (en) 2012-12-20 2014-05-06 United Microelectronics Corp. Method of fabricating isolation structure
US9105485B2 (en) * 2013-03-08 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding structures and methods of forming the same
US8884398B2 (en) 2013-04-01 2014-11-11 United Microelectronics Corp. Anti-fuse structure and programming method thereof
US9287173B2 (en) 2013-05-23 2016-03-15 United Microelectronics Corp. Through silicon via and process thereof
US9123730B2 (en) 2013-07-11 2015-09-01 United Microelectronics Corp. Semiconductor device having through silicon trench shielding structure surrounding RF circuit
US9929050B2 (en) 2013-07-16 2018-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure
US9087821B2 (en) 2013-07-16 2015-07-21 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bonding with through substrate via (TSV)
JP2015023235A (ja) 2013-07-23 2015-02-02 株式会社東芝 半導体装置及びその製造方法
US9024416B2 (en) 2013-08-12 2015-05-05 United Microelectronics Corp. Semiconductor structure
US8916471B1 (en) 2013-08-26 2014-12-23 United Microelectronics Corp. Method for forming semiconductor structure having through silicon via for signal and shielding structure
US9048223B2 (en) 2013-09-03 2015-06-02 United Microelectronics Corp. Package structure having silicon through vias connected to ground potential
US9117804B2 (en) 2013-09-13 2015-08-25 United Microelectronics Corporation Interposer structure and manufacturing method thereof
KR102094473B1 (ko) 2013-10-15 2020-03-27 삼성전자주식회사 Ｔｓｖ 구조를 구비한 집적회로 소자 및 그 제조 방법
US9343359B2 (en) 2013-12-25 2016-05-17 United Microelectronics Corp. Integrated structure and method for fabricating the same
KR20150078008A (ko) * 2013-12-30 2015-07-08 에스케이하이닉스 주식회사 반도체 장치, 이의 제조 방법 및 이의 테스트 방법
US10340203B2 (en) 2014-02-07 2019-07-02 United Microelectronics Corp. Semiconductor structure with through silicon via and method for fabricating and testing the same
US9478509B2 (en) * 2014-03-06 2016-10-25 GlobalFoundries, Inc. Mechanically anchored backside C4 pad
US9356009B2 (en) * 2014-05-27 2016-05-31 Micron Technology, Inc. Interconnect structure with redundant electrical connectors and associated systems and methods
US20160093583A1 (en) * 2014-09-25 2016-03-31 Micron Technology, Inc. Bond pad with micro-protrusions for direct metallic bonding
US9536848B2 (en) * 2014-10-16 2017-01-03 Globalfoundries Inc. Bond pad structure for low temperature flip chip bonding
JP6468071B2 (ja) * 2015-05-25 2019-02-13 富士通株式会社 半導体装置及び電子装置並びに半導体装置の製造方法
US9704827B2 (en) 2015-06-25 2017-07-11 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bond pad structure
US9620488B2 (en) * 2015-08-19 2017-04-11 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional integrated circuit structure and bonded structure
KR102423813B1 (ko) 2015-11-27 2022-07-22 삼성전자주식회사 반도체 소자
KR102473664B1 (ko) * 2016-01-19 2022-12-02 삼성전자주식회사 Tsv 구조체를 가진 다중 적층 소자
JP2018026451A (ja) * 2016-08-10 2018-02-15 エスアイアイ・セミコンダクタ株式会社 半導体装置
JP6328190B2 (ja) * 2016-08-24 2018-05-23 キヤノン株式会社 固体撮像装置
JP2018064758A (ja) 2016-10-19 2018-04-26 ソニーセミコンダクタソリューションズ株式会社 半導体装置、製造方法、および電子機器
CN109285825B (zh) * 2017-07-21 2021-02-05 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
CN109698208B (zh) * 2017-10-20 2023-06-30 新加坡有限公司 图像传感器的封装方法、图像传感器封装结构和镜头模组
JP6952629B2 (ja) * 2018-03-20 2021-10-20 株式会社東芝 半導体装置
KR102297701B1 (ko) * 2018-03-22 2021-09-06 샌디스크 테크놀로지스 엘엘씨 관통-기판 비아 구조들을 갖는 본딩된 칩 어셈블리를 포함하는 3차원 메모리 디바이스 및 그 제조 방법
KR102593085B1 (ko) 2018-11-21 2023-10-24 삼성전자주식회사 반도체 장치, 반도체 패키지 및 이의 제조 방법
KR102626314B1 (ko) 2019-01-28 2024-01-17 삼성전자주식회사 접합 패드를 갖는 반도체 소자
KR20220000294A (ko) * 2020-06-25 2022-01-03 삼성전자주식회사 반도체 패키지
KR20220126135A (ko) * 2021-03-08 2022-09-15 삼성전자주식회사 반도체 칩 구조물
US20230245987A1 (en) * 2022-01-28 2023-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Slotted bond pad in stacked wafer structure
CN115084082B (zh) * 2022-07-19 2022-11-22 甬矽电子(宁波)股份有限公司 扇出型封装结构和扇出型封装方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5786238A (en) * 1997-02-13 1998-07-28 Generyal Dynamics Information Systems, Inc. Laminated multilayer substrates

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3396790B2 (ja) * 1994-08-02 2003-04-14 富士通株式会社 半導体装置及びその製造方法
JP3526376B2 (ja) * 1996-08-21 2004-05-10 株式会社東芝 半導体装置及びその製造方法
WO1999038204A1 (fr) * 1998-01-23 1999-07-29 Rohm Co., Ltd. Interconnexion damasquinee et dispositif a semi-conducteur
US6013877A (en) * 1998-03-12 2000-01-11 Lucent Technologies Inc. Solder bonding printed circuit boards
JP2000208702A (ja) * 1999-01-14 2000-07-28 Hitachi Ltd 半導体装置およびその製造方法
US6524876B1 (en) * 1999-04-08 2003-02-25 Samsung Electronics Co., Ltd. Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same
JP4209033B2 (ja) * 1999-05-21 2009-01-14 パナソニック株式会社 半導体装置の製造方法
JP3440057B2 (ja) * 2000-07-05 2003-08-25 唯知 須賀 半導体装置およびその製造方法
KR100370238B1 (ko) * 2000-10-20 2003-01-30 삼성전자 주식회사 반도체 소자의 본드패드 및 그 형성방법
KR100421043B1 (ko) * 2000-12-21 2004-03-04 삼성전자주식회사 비정렬되고 소정 거리 이격된 섬형 절연체들의 배열을 갖는 도전막을 포함하는 집적 회로 본딩 패드
JP3685722B2 (ja) * 2001-02-28 2005-08-24 三洋電機株式会社 半導体装置及びその製造方法
US6531384B1 (en) * 2001-09-14 2003-03-11 Motorola, Inc. Method of forming a bond pad and structure thereof
US6642081B1 (en) * 2002-04-11 2003-11-04 Robert Patti Interlocking conductor method for bonding wafers to produce stacked integrated circuits
US20040188696A1 (en) * 2003-03-28 2004-09-30 Gelcore, Llc LED power package
JP3891299B2 (ja) * 2003-05-06 2007-03-14 セイコーエプソン株式会社 半導体装置の製造方法、半導体装置、半導体デバイス、電子機器
JP2005039078A (ja) * 2003-07-16 2005-02-10 Masaki Esashi 薄板基板構造形成用ウエーハ基板、この製造方法およびｍｅｍｓ素子の製造方法
US7081679B2 (en) * 2003-12-10 2006-07-25 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for reinforcing a bond pad on a chip
JP2005251828A (ja) 2004-03-02 2005-09-15 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2006041148A (ja) * 2004-07-27 2006-02-09 Seiko Epson Corp 半導体装置の製造方法、半導体装置、及び電子機器
US7199050B2 (en) * 2004-08-24 2007-04-03 Micron Technology, Inc. Pass through via technology for use during the manufacture of a semiconductor device
US7262495B2 (en) * 2004-10-07 2007-08-28 Hewlett-Packard Development Company, L.P. 3D interconnect with protruding contacts
JP4433298B2 (ja) * 2004-12-16 2010-03-17 パナソニック株式会社 多段構成半導体モジュール
JP4426482B2 (ja) * 2005-02-28 2010-03-03 Ｏｋｉセミコンダクタ株式会社 パッケージ基台およびその製造方法、並びにそのパッケージ基台を備えた半導体パッケージ
JP4577687B2 (ja) * 2005-03-17 2010-11-10 エルピーダメモリ株式会社 半導体装置
US7265441B2 (en) * 2005-08-15 2007-09-04 Infineon Technologies Ag Stackable single package and stacked multi-chip assembly
JP4869664B2 (ja) * 2005-08-26 2012-02-08 本田技研工業株式会社 半導体装置の製造方法
US7626257B2 (en) * 2006-01-18 2009-12-01 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
US7579258B2 (en) * 2006-01-25 2009-08-25 Freescale Semiconductor, Inc. Semiconductor interconnect having adjacent reservoir for bonding and method for formation
KR100694424B1 (ko) 2006-02-17 2007-03-12 주식회사 하이닉스반도체 멀티 칩 패키지 장치 및 그 형성 방법
US7750488B2 (en) * 2006-07-10 2010-07-06 Tezzaron Semiconductor, Inc. Method for bonding wafers to produce stacked integrated circuits
US7494846B2 (en) * 2007-03-09 2009-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Design techniques for stacking identical memory dies
US8134235B2 (en) * 2007-04-23 2012-03-13 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5786238A (en) * 1997-02-13 1998-07-28 Generyal Dynamics Information Systems, Inc. Laminated multilayer substrates

Also Published As

Publication number Publication date
US8053900B2 (en) 2011-11-08
JP2010103533A (ja) 2010-05-06
KR101107806B1 (ko) 2012-01-25
US20100096760A1 (en) 2010-04-22
KR20100044100A (ko) 2010-04-29
TWI399842B (zh) 2013-06-21
JP5430338B2 (ja) 2014-02-26
TW201017847A (en) 2010-05-01
CN101728371A (zh) 2010-06-09

Similar Documents

Publication Publication Date Title
CN101728371B (zh) 集成电路结构
CN101719488B (zh) 具有锥形轮廓的再分布线的焊垫连接
JP6548377B2 (ja) 集積回路素子及びその製造方法
US9698080B2 (en) Conductor structure for three-dimensional semiconductor device
JP5271985B2 (ja) 集積回路構造
CN101771018B (zh) 具有气隙的穿透硅通孔
JP6399887B2 (ja) Ｔｓｖ構造を具備した集積回路素子及びその製造方法
US9646930B2 (en) Semiconductor device having through-substrate vias
CN103219325B (zh) 多维集成电路结构及其形成方法
CN101752270B (zh) 堆叠集成电路半导体晶粒的形成方法
US8053277B2 (en) Three-dimensional integrated circuits with protection layers
CN102347320B (zh) 装置及其制造方法
CN101783329B (zh) 半导体元件及其制法
CN102867777B (zh) 在半导体衬底中形成接地硅通孔
US20090305502A1 (en) Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein and Chips Formed Thereby
CN101740417B (zh) 可堆叠芯片的制造方法
CN101719484A (zh) 具有再分布线的tsv的背连接
CN107731667B (zh) 具备金属连线的混合键合方法及混合键合结构
KR20130082315A (ko) 집적회로 소자
US9059067B2 (en) Semiconductor device with interposer and method manufacturing same
KR102545434B1 (ko) 칩릿 3D SoIC 시스템 집적 및 제조 방법
KR20230035173A (ko) 반도체 칩, 반도체 패키지 및 제조 방법
CN117936502A (zh) 半导体封装件
CN117525021A (zh) 半导体封装
TW201442170A (zh) 半導體裝置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant